From 4807d0bdb6bda1154cc39a619d0432de5ec14571 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Wed, 22 Jul 2020 20:51:31 +1000 Subject: [PATCH] FPU: Implement fmrgew and fmrgow and add tests for them Signed-off-by: Paul Mackerras --- decode1.vhdl | 2 ++ fpu.vhdl | 27 +++++++++++++++++++++++---- tests/fpu/fpu.c | 21 +++++++++++++++++++++ tests/test_fpu.bin | Bin 21208 -> 21208 bytes tests/test_fpu.console_out | 1 + 5 files changed, 47 insertions(+), 4 deletions(-) diff --git a/decode1.vhdl b/decode1.vhdl index a42899d..34170dd 100644 --- a/decode1.vhdl +++ b/decode1.vhdl @@ -434,6 +434,8 @@ architecture behaviour of decode1 is 2#011000001# => (FPU, OP_FPOP, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 1/6=mtfsb1 2#011000010# => (FPU, OP_FPOP, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 2/6=mtfsb0 2#011000100# => (FPU, OP_FPOP, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 4/6=mtfsfi + 2#011011010# => (FPU, OP_FPOP_I, FRA, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- 26/6=fmrgow + 2#011011110# => (FPU, OP_FPOP_I, FRA, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- 30/6=fmrgew 2#011110010# => (FPU, OP_FPOP_I, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 18/7=mffs family 2#011110110# => (FPU, OP_FPOP_I, NONE, FRB, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 22/7=mtfsf 2#100000000# => (FPU, OP_FPOP, FRA, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 0/8=fcpsgn diff --git a/fpu.vhdl b/fpu.vhdl index 371fdc5..e97461c 100644 --- a/fpu.vhdl +++ b/fpu.vhdl @@ -37,7 +37,7 @@ architecture behaviour of fpu is type state_t is (IDLE, DO_MCRFS, DO_MTFSB, DO_MTFSFI, DO_MFFS, DO_MTFSF, - DO_FMR, + DO_FMR, DO_FMRG, DO_FCFID, DO_FCTI, DO_FRSP, DO_FRI, FRI_1, @@ -450,10 +450,14 @@ begin when "00000" => v.state := DO_MCRFS; when "00110" => - if e_in.insn(8) = '0' then - v.state := DO_MTFSB; + if e_in.insn(10) = '0' then + if e_in.insn(8) = '0' then + v.state := DO_MTFSB; + else + v.state := DO_MTFSFI; + end if; else - v.state := DO_MTFSFI; + v.state := DO_FMRG; end if; when "00111" => if e_in.insn(8) = '0' then @@ -524,6 +528,15 @@ begin v.instr_done := '1'; v.state := IDLE; + when DO_FMRG => + -- fmrgew, fmrgow + opsel_r <= RES_MISC; + misc_sel <= "01" & r.insn(8) & '0'; + v.int_result := '1'; + v.writing_back := '1'; + v.instr_done := '1'; + v.state := IDLE; + when DO_MFFS => v.int_result := '1'; v.writing_back := '1'; @@ -1009,6 +1022,12 @@ begin when "0011" => -- mantissa of max representable SP number misc := x"007fffff80000000"; + when "0100" => + -- fmrgow result + misc := r.a.mantissa(31 downto 0) & r.b.mantissa(31 downto 0); + when "0110" => + -- fmrgew result + misc := r.a.mantissa(63 downto 32) & r.b.mantissa(63 downto 32); when "1000" => -- max positive result for fctiw[z] misc := x"000000007fffffff"; diff --git a/tests/fpu/fpu.c b/tests/fpu/fpu.c index d24fe14..e7a1334 100644 --- a/tests/fpu/fpu.c +++ b/tests/fpu/fpu.c @@ -823,6 +823,26 @@ int fpu_test_11(void) return trapit(0, test11); } +int test12(long arg) +{ + unsigned long vals[2]; + unsigned long results[2]; + + vals[0] = 0xf0f0f0f05a5a5a5aul; + vals[1] = 0x0123456789abcdeful; + asm("lfd 5,0(%0); lfd 6,8(%0); fmrgew 7,5,6; fmrgow 8,5,6; stfd 7,0(%1); stfd 8,8(%1)" + : : "b" (vals), "b" (results) : "memory"); + if (results[0] != 0xf0f0f0f001234567ul || results[1] != 0x5a5a5a5a89abcdeful) + return 1; + return 0; +} + +int fpu_test_12(void) +{ + enable_fp(); + return trapit(0, test12); +} + int fail = 0; void do_test(int num, int (*test)(void)) @@ -859,6 +879,7 @@ int main(void) do_test(9, fpu_test_9); do_test(10, fpu_test_10); do_test(11, fpu_test_11); + do_test(12, fpu_test_12); return fail; } diff --git a/tests/test_fpu.bin b/tests/test_fpu.bin index d2320cd960e8c39417367d3b8d7fc730494c9eca..668ff65367cbf02294b638e77fd93f9173db9532 100755 GIT binary patch delta 1932 zcmZ`&ZA?>V6n<~v*22&fC{Vsz$_5oGEpziCAC@SjQfJWV<`^m+BT9ma%Ot6;qiF7u znUDo{7Nd(UxQNk=C1YUX4_q{pMHiRM#UHqsMHFYt$1IypoWi^3ZR?C|JITp?p68r< z&bjBl??|sS(kpd$X^s^3e{?X>9}1Z&Z}94}P{``}Zh>`oLxZ&i?g?@8LyKgp+*T9O zzu0eWx%-3FGXov5GR96_)Uit!yO!O4-1V|N%h>pcj>TUKg`B8o4oa*^35DuVvu?LV zs%zO+Q|DpzR-cLOThq{Bstj;X0DaQKO`jC^);0S$w>b3atv)g&b!N9raW`YENn)ll zri&?F#r8S9kH-9>`fBP=%9X5iB`J52F@w3D=(CeFm$Y8mOzV=1H1AJRM{G zenEPPhLcxnrY9)gP^vjQK~;ve)@&nlo#*Bm&Ocwl`Mwp5ohw)0JX=0if292AEO&b+ zj{CiTeCw~F(}seD3CQ-|Qo~9j1r1xZ`nOf(%W+zpQmb_~sETKtK252Um%gDYh^M%< zeL&}fv^=#gR!wCt>M1bM$yB{mO;Xx23Z*85`@%ayLGp0_#%p*Q?5bNT}YZlX~fj@pU|%ku*%lGMrKy-OQ+!d}Ph+ zOlfOYvgf$l#5@7)szT2?m6103CbL!=A~|a)5pfy&60z7w?5C{7(gm8$x{%)1t9T#X z@~?jUulIk>u9bSooU;qP4(8<8_Qx}q_~Z29W)JRU8IAH-@E^giL^sV8*av8#bs1Sz)!zNYP8|Crfjo|M@`E%gM!97u)06q!6ZlJwz zd#wK^=VMr&Fg?5&eh*r`5MV-c!tJ*>58)|HXdB=OW1OE90!(Pz;XTkycnTAm58ekY zUkEVq?1m3PyN)NhY+3RdfSuH8E0S@RnU40LDeM|c?77DT1$##T?}Jq=x|AaycEbz!-zHl71C6RMXLf0O;V~o zPumB0Z;GnydFfXHUB5lu)GD+IK-)mO?JKqRSjNWg(jI%&$BtN=7i`z`(~-nhyP)}? ziT8x9f%ib`BZtE+hk$gn*HK`|lF|J>=L`#AHH%D%)gABBkRxCEkVYNJDUbi;Tov!b t3gJ$88^x6tE$(^1xln|OhMn+1XvLxsOlY6LFV75YDLtAnP~tq5^fx0>#!mnM delta 1739 zcmZ{jZ%mt26vpo@eLI*yV04sH7zMgfgs~QkUIn%?D#3LzI6*;O1|rD}Rnd&3Q(U{{ zjoF7~89B?MiHl%hQL`;>bcsta0o^`mHWLgV_5pPW({2m`{sSEI`rNj08R|(+-skz< z^WJ;jbK7f!{MsNtcEoVH=-km0>2zgXmmy`2wq|7W1!~F2<72cxBQJHt%IX7mrh}Zd ziosbrm9dL!w4705*f>j@%o_|#SyX4<#J{6g%(aI1Zqs>lxuN4W{bYW!__Br7kIMWd zDL>pM<)LkijZ_|g?(@p&hW9H^-j%+<%s?>k>zBb<+P%IgC5-C8lpZA)sdxPzlf7LR zO*8a~rHmYzS*C^-T_nxW_RJlcw^!Kg( z5xQ`Lv@I#ypzli7v5hBVtAevvwCCHw;Q+C03IzO~hHKUs4^>pR;; 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