From 480b2348a2a08e518f355e25f62ffbedd51b3068 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 18 Aug 2020 01:34:15 +0100 Subject: [PATCH] add comment in dcache.py --- src/soc/experiment/dcache.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 3144ae1a..26d961a2 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -382,6 +382,10 @@ class Dcache(Elaboratable): # signal dtlb_valids : tlb_valids_t; # signal dtlb_tags : tlb_tags_t; # signal dtlb_ptes : tlb_ptes_t; + +"""note: these are passed to nmigen.hdl.Memory as "attributes". don't + know how, just that they are. +""" # attribute ram_style of dtlb_tags : signal is "distributed"; # attribute ram_style of dtlb_ptes : signal is "distributed"; dtlb_valids = tlb_valids_t; -- 2.30.2