From 48145cee021d75852aeb721cb11faa7336e9254f Mon Sep 17 00:00:00 2001 From: whitequark Date: Sat, 25 May 2019 22:23:03 +0000 Subject: [PATCH] build.dsl: improve repr of Pins() and DiffPairs(). --- nmigen/build/dsl.py | 5 +++-- nmigen/test/test_build_dsl.py | 27 ++++++++++++++------------- 2 files changed, 17 insertions(+), 15 deletions(-) diff --git a/nmigen/build/dsl.py b/nmigen/build/dsl.py index 9205a1b..f3e88f0 100644 --- a/nmigen/build/dsl.py +++ b/nmigen/build/dsl.py @@ -14,7 +14,7 @@ class Pins: self.dir = dir def __repr__(self): - return "(pins {} {})".format(" ".join(self.names), self.dir) + return "(pins {} {})".format(self.dir, " ".join(self.names)) class DiffPairs: @@ -30,7 +30,8 @@ class DiffPairs: self.dir = dir def __repr__(self): - return "(diffpairs {} {})".format(self.p, self.n) + return "(diffpairs {} (p {}) (n {}))".format( + self.dir, " ".join(self.p.names), " ".join(self.n.names)) class Subsignal: diff --git a/nmigen/test/test_build_dsl.py b/nmigen/test/test_build_dsl.py index 176e59f..9af7726 100644 --- a/nmigen/test/test_build_dsl.py +++ b/nmigen/test/test_build_dsl.py @@ -5,7 +5,7 @@ from .tools import * class PinsTestCase(FHDLTestCase): def test_basic(self): p = Pins("A0 A1 A2") - self.assertEqual(repr(p), "(pins A0 A1 A2 io)") + self.assertEqual(repr(p), "(pins io A0 A1 A2)") self.assertEqual(len(p.names), 3) self.assertEqual(p.dir, "io") @@ -23,7 +23,7 @@ class PinsTestCase(FHDLTestCase): class DiffPairsTestCase(FHDLTestCase): def test_basic(self): dp = DiffPairs(p="A0 A1", n="B0 B1") - self.assertEqual(repr(dp), "(diffpairs (pins A0 A1 io) (pins B0 B1 io))") + self.assertEqual(repr(dp), "(diffpairs io (p A0 A1) (n B0 B1))") self.assertEqual(dp.p.names, ["A0", "A1"]) self.assertEqual(dp.n.names, ["B0", "B1"]) self.assertEqual(dp.dir, "io") @@ -36,26 +36,26 @@ class DiffPairsTestCase(FHDLTestCase): def test_wrong_width(self): with self.assertRaises(TypeError, - msg="Positive and negative pins must have the same width, but (pins A0 io) and " - "(pins B0 B1 io) do not"): + msg="Positive and negative pins must have the same width, but (pins io A0) " + "and (pins io B0 B1) do not"): dp = DiffPairs("A0", "B0 B1") class SubsignalTestCase(FHDLTestCase): def test_basic_pins(self): s = Subsignal("a", Pins("A0"), extras=["IOSTANDARD=LVCMOS33"]) - self.assertEqual(repr(s), "(subsignal a (pins A0 io) IOSTANDARD=LVCMOS33)") + self.assertEqual(repr(s), "(subsignal a (pins io A0) IOSTANDARD=LVCMOS33)") def test_basic_diffpairs(self): s = Subsignal("a", DiffPairs("A0", "B0")) - self.assertEqual(repr(s), "(subsignal a (diffpairs (pins A0 io) (pins B0 io)) )") + self.assertEqual(repr(s), "(subsignal a (diffpairs io (p A0) (n B0)) )") def test_basic_subsignals(self): s = Subsignal("a", Subsignal("b", Pins("A0")), Subsignal("c", Pins("A1"))) self.assertEqual(repr(s), - "(subsignal a (subsignal b (pins A0 io) ) (subsignal c (pins A1 io) ) )") + "(subsignal a (subsignal b (pins io A0) ) (subsignal c (pins io A1) ) )") def test_extras(self): s = Subsignal("a", @@ -78,24 +78,25 @@ class SubsignalTestCase(FHDLTestCase): def test_wrong_pins(self): with self.assertRaises(TypeError, msg="Pins and DiffPairs cannot be followed by more I/O constraints, but " - "(pins A0 io) is followed by (pins A1 io)"): + "(pins io A0) is followed by (pins io A1)"): s = Subsignal("a", Pins("A0"), Pins("A1")) def test_wrong_diffpairs(self): with self.assertRaises(TypeError, msg="Pins and DiffPairs cannot be followed by more I/O constraints, but " - "(diffpairs (pins A0 io) (pins B0 io)) is followed by (pins A1 io)"): + "(diffpairs io (p A0) (n B0)) is followed by " + "(pins io A1)"): s = Subsignal("a", DiffPairs("A0", "B0"), Pins("A1")) def test_wrong_subsignals(self): with self.assertRaises(TypeError, msg="A Subsignal can only be followed by more Subsignals, but " - "(subsignal b (pins A0 io) ) is followed by (pins B0 io)"): + "(subsignal b (pins io A0) ) is followed by (pins io B0)"): s = Subsignal("a", Subsignal("b", Pins("A0")), Pins("B0")) def test_wrong_extras(self): with self.assertRaises(TypeError, - msg="Extra constraint must be a string, not (pins B0 io)"): + msg="Extra constraint must be a string, not (pins io B0)"): s = Subsignal("a", Pins("A0"), extras=[Pins("B0")]) @@ -106,6 +107,6 @@ class ResourceTestCase(FHDLTestCase): Subsignal("rx", Pins("A1", dir="i")), extras=["IOSTANDARD=LVCMOS33"]) self.assertEqual(repr(r), "(resource serial 0" - " (subsignal tx (pins A0 o) IOSTANDARD=LVCMOS33)" - " (subsignal rx (pins A1 i) IOSTANDARD=LVCMOS33)" + " (subsignal tx (pins o A0) IOSTANDARD=LVCMOS33)" + " (subsignal rx (pins i A1) IOSTANDARD=LVCMOS33)" " IOSTANDARD=LVCMOS33)") -- 2.30.2