From 481e55f1de819452cf1e86ba72f9bbf6d57a502b Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 8 Sep 2022 18:03:43 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index b2a1fffa8..f02126c24 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -191,14 +191,15 @@ the other space totalling two 75% Majors. Note critically that: -*Unlike EXT001 SVP64's 24-bits may **not** hold also any Scalar operations. +* Unlike EXT001, SVP64's 24-bits may **not** hold also any Scalar + operations. There is no free available space: a 25th bit would be required. The entire 24-bits is **required** for the abstracted Hardware-Looping Concept **even when these 24-bits are zero** -* Any Scalar 64-bit instruction (regardless of how it is encoded) is unsafe to +* Any Scalar 64-bit instruction (regardless of how it is encoded) is unsafe to then Vectorise because this creates the situation of Prefixed-Prefixed, resulting in deep complexity in Hardware Decode at a critical juncture, as - well as bring 96-bit instructions. + well as introducing 96-bit instructions. *Three 75% allocations are thus genuinely needed*, all other options are unsuitable for consideration. @@ -212,7 +213,7 @@ In order of size, for bitmanip and A/V DSP purposes: * QTY 8of 5/6-bit (A-Form): xpermi, bincrflut, bmask, fmvis, fishmv, bmrev, Galois Field * QTY 30of 10-bit (X-Form): cldiv/mul, av-min/max/diff, absdac, xperm -Note: Some of the Galois Field operations will require QTY 1of Polynomial SPR. +Note: Some of the Galois Field operations will require QTY 1of Polynomial SPR (per userspace supervisor hypervisor). **EXT004** -- 2.30.2