From 48241fac1239dba697be28f72e68a741a0e75eb5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 23 Jul 2020 20:28:37 +0100 Subject: [PATCH] try different MEMTEST_xxx sizes with 64 bit bus width --- src/soc/litex/sim.py | 49 ++++++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 22 deletions(-) diff --git a/src/soc/litex/sim.py b/src/soc/litex/sim.py index 3c3dcbae..33149c39 100644 --- a/src/soc/litex/sim.py +++ b/src/soc/litex/sim.py @@ -17,7 +17,7 @@ from litex.soc.integration.soc_core import SoCCore from litex.soc.integration.common import get_mem_data from litex.soc.integration.builder import Builder -from litedram.modules import MT41K128M16 +from litedram.modules import IS42S16160 #, MT41K128M16 from litedram.phy.model import SDRAMPHYModel from litedram.core.controller import ControllerSettings @@ -68,6 +68,7 @@ class SoCSMP(SoCCore): cpu_type = "microwatt", # XXX use microwatt cpu_variant = cpu_variant, cpu_cls = LibreSOC, + bus_data_width = 64, # 64 bit wishbone data bus uart_name = "sim", integrated_rom_size = 0x8000, integrated_main_ram_size = 0x00000000) @@ -79,24 +80,28 @@ class SoCSMP(SoCCore): self.submodules.crg = CRG(platform.request("sys_clk")) # SDRAM ---------------------------------------------------------- - phy_settings = get_sdram_phy_settings( - memtype = "DDR3", - data_width = 16, - clk_freq = 100e6) - self.submodules.sdrphy = SDRAMPHYModel( - module = MT41K128M16(100e6, "1:4"), - settings = phy_settings, - clk_freq = 100e6, - init = sdram_init) - self.add_sdram("sdram", - phy = self.sdrphy, - module = MT41K128M16(100e6, "1:4"), - origin = self.mem_map["main_ram"], - controller_settings = ControllerSettings( - cmd_buffer_buffered = False, - with_auto_precharge = True + if True: + phy_settings = get_sdram_phy_settings( + memtype = "DDR3", + #memtype = "SDR", + data_width = 16, + clk_freq = 100e6) + self.submodules.sdrphy = SDRAMPHYModel( + module = MT41K128M16(100e6, "1:4"), + #module = IS42S16160(100e6, "1:4"), + settings = phy_settings, + clk_freq = 100e6, + init = sdram_init) + self.add_sdram("sdram", + phy = self.sdrphy, + module = MT41K128M16(100e6, "1:4"), + #module = IS42S16160(100e6, "1:4"), + origin = self.mem_map["main_ram"], + controller_settings = ControllerSettings( + cmd_buffer_buffered = False, + with_auto_precharge = True + ) ) - ) if init_memories: addr = 0x40f00000 self.add_constant("MEMTEST_BUS_SIZE", 0) # Skip test if memory is @@ -104,9 +109,9 @@ class SoCSMP(SoCCore): self.add_constant("MEMTEST_DATA_SIZE", 0) # corrumpting the content. self.add_constant("ROM_BOOT_ADDRESS", addr) # Jump to fw_jump.bin else: - self.add_constant("MEMTEST_BUS_SIZE", 4096) - self.add_constant("MEMTEST_ADDR_SIZE", 4096) - self.add_constant("MEMTEST_DATA_SIZE", 4096) + self.add_constant("MEMTEST_BUS_SIZE", 4096//64) + self.add_constant("MEMTEST_ADDR_SIZE", 4096//256) + self.add_constant("MEMTEST_DATA_SIZE", 4096//32) # SDCard ----------------------------------------------------- if with_sdcard: @@ -149,7 +154,7 @@ def main(): trace = args.trace, trace_start = int(args.trace_start), trace_end = int(args.trace_end), - trace_fst = 1) + trace_fst = 0) os.chdir("../") #if not to_run: # os.system("./json2dts.py build/sim/csr.json > build/sim/dts") # FIXME -- 2.30.2