From 483752f94d6eca681d1a7ef6cee574ed32c8517f Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 May 2022 13:21:34 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index cd6215fa7..27a164ff6 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -542,8 +542,9 @@ to connect to standard DIMMs. Extra-V appears to be a remarkable research project that, by leveraging OpenCAPI, assuming that the map of edges in any given arbitrary data graph could be kept by the main CPU in-memory, could distribute and delegate -a limited-capability deterministic node-walking schedule actually right down into the memory itself (on the other side of that L1-4 cache barrier), -where, thanks to the OpenCAPI Standard, many of the nightmare problems +a limited-capability deterministic but most importantly *data-dependent* +node-walking schedule actually right down into the memory itself (on the other side of that L1-4 cache barrier). +Thanks to the OpenCAPI Standard, many of the nightmare problems of other more explicit parallel processing paradigms disappear. **Snitch** -- 2.30.2