From 485dee97c6431267b662b723eb092a6abfa4167c Mon Sep 17 00:00:00 2001 From: Andre Vieira Date: Wed, 15 May 2019 16:52:50 +0100 Subject: [PATCH] [PATCH 3/57][Arm][GAS] Add support for MVE instructions: vabs and vneg gas/ChangeLog: 2019-05-16 Andre Vieira * config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant. (insns): Change vabs and vneg entries to accept MVE variants. * testsuite/gas/arm/mve-vabsneg-bad-1.d: New test. * testsuite/gas/arm/mve-vabsneg-bad-1.l: New test. * testsuite/gas/arm/mve-vabsneg-bad-1.s: New test. * testsuite/gas/arm/mve-vabsneg-bad-2.d: New test. * testsuite/gas/arm/mve-vabsneg-bad-2.l: New test. * testsuite/gas/arm/mve-vabsneg-bad-2.s: New test. --- gas/ChangeLog | 11 +++++++ gas/config/tc-arm.c | 13 ++++---- gas/testsuite/gas/arm/mve-vabsneg-bad-1.d | 6 ++++ gas/testsuite/gas/arm/mve-vabsneg-bad-1.l | 33 ++++++++++++++++++++ gas/testsuite/gas/arm/mve-vabsneg-bad-1.s | 37 +++++++++++++++++++++++ gas/testsuite/gas/arm/mve-vabsneg-bad-2.d | 6 ++++ gas/testsuite/gas/arm/mve-vabsneg-bad-2.l | 29 ++++++++++++++++++ gas/testsuite/gas/arm/mve-vabsneg-bad-2.s | 32 ++++++++++++++++++++ 8 files changed, 161 insertions(+), 6 deletions(-) create mode 100644 gas/testsuite/gas/arm/mve-vabsneg-bad-1.d create mode 100644 gas/testsuite/gas/arm/mve-vabsneg-bad-1.l create mode 100644 gas/testsuite/gas/arm/mve-vabsneg-bad-1.s create mode 100644 gas/testsuite/gas/arm/mve-vabsneg-bad-2.d create mode 100644 gas/testsuite/gas/arm/mve-vabsneg-bad-2.l create mode 100644 gas/testsuite/gas/arm/mve-vabsneg-bad-2.s diff --git a/gas/ChangeLog b/gas/ChangeLog index c26396d2734..c94dd339e4d 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,14 @@ +2019-05-16 Andre Vieira + + * config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant. + (insns): Change vabs and vneg entries to accept MVE variants. + * testsuite/gas/arm/mve-vabsneg-bad-1.d: New test. + * testsuite/gas/arm/mve-vabsneg-bad-1.l: New test. + * testsuite/gas/arm/mve-vabsneg-bad-1.s: New test. + * testsuite/gas/arm/mve-vabsneg-bad-2.d: New test. + * testsuite/gas/arm/mve-vabsneg-bad-2.l: New test. + * testsuite/gas/arm/mve-vabsneg-bad-2.s: New test. + 2019-05-16 Andre Vieira * config/tc-arm.c (enum it_instruction_type): Rename to... diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 46d0f4e7b59..8b1e9fc6262 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -15950,12 +15950,13 @@ do_neon_abs_neg (void) if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) return; - if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) - return; - rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY); + if (check_simd_pred_availability (et.type == NT_float, + NEON_CHECK_ARCH | NEON_CHECK_CC)) + return; + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; inst.instruction |= HI1 (inst.operands[0].reg) << 22; inst.instruction |= LOW4 (inst.operands[1].reg); @@ -21909,9 +21910,6 @@ static const struct asm_opcode insns[] = nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), - NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), - NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), - NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), @@ -22643,6 +22641,9 @@ static const struct asm_opcode insns[] = mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i), mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i), + MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg), + MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg), + #undef ARM_VARIANT #define ARM_VARIANT & fpu_neon_ext_v1 mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), diff --git a/gas/testsuite/gas/arm/mve-vabsneg-bad-1.d b/gas/testsuite/gas/arm/mve-vabsneg-bad-1.d new file mode 100644 index 00000000000..49358335603 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vabsneg-bad-1.d @@ -0,0 +1,6 @@ +#name: bad MVE VABS and VNEG instructions +#as: -march=armv8.1-m.main+mve +#error_output: mve-vabsneg-bad-1.l + +.*: +file format .*arm.* + diff --git a/gas/testsuite/gas/arm/mve-vabsneg-bad-1.l b/gas/testsuite/gas/arm/mve-vabsneg-bad-1.l new file mode 100644 index 00000000000..46fda8b53f7 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vabsneg-bad-1.l @@ -0,0 +1,33 @@ +[^:]*: Assembler messages: +[^:]*:13: Error: bad type in SIMD instruction -- `vabs.p8 q0,q1' +[^:]*:14: Error: bad type in SIMD instruction -- `vabs.p16 q0,q1' +[^:]*:15: Error: bad type in SIMD instruction -- `vabs.u8 q0,q1' +[^:]*:16: Error: bad type in SIMD instruction -- `vabs.u16 q0,q1' +[^:]*:17: Error: bad type in SIMD instruction -- `vabs.u32 q0,q1' +[^:]*:18: Error: selected FPU does not support instruction -- `vabs.f16 q0,q1' +[^:]*:19: Error: selected FPU does not support instruction -- `vabs.f32 q0,q1' +[^:]*:20: Error: bad type in SIMD instruction -- `vabs.s64 q0,q1' +[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Error: bad type in SIMD instruction -- `vneg.p8 q0,q1' +[^:]*:23: Error: bad type in SIMD instruction -- `vneg.p16 q0,q1' +[^:]*:24: Error: bad type in SIMD instruction -- `vneg.u8 q0,q1' +[^:]*:25: Error: bad type in SIMD instruction -- `vneg.u16 q0,q1' +[^:]*:26: Error: bad type in SIMD instruction -- `vneg.u32 q0,q1' +[^:]*:27: Error: selected FPU does not support instruction -- `vneg.f16 q0,q1' +[^:]*:28: Error: selected FPU does not support instruction -- `vneg.f32 q0,q1' +[^:]*:29: Error: bad type in SIMD instruction -- `vneg.s64 q0,q1' +[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:32: Error: syntax error -- `vnegeq.s32 q0,q1' +[^:]*:33: Error: syntax error -- `vnegeq.s32 q0,q1' +[^:]*:35: Error: instruction missing MVE vector predication code -- `vneg.s32 q0,q1' +[^:]*:36: Error: vector predicated instruction should be in VPT/VPST block -- `vnegt.s32 q0,q1' diff --git a/gas/testsuite/gas/arm/mve-vabsneg-bad-1.s b/gas/testsuite/gas/arm/mve-vabsneg-bad-1.s new file mode 100644 index 00000000000..cda955ccc48 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vabsneg-bad-1.s @@ -0,0 +1,37 @@ +.macro cond op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().s32 q0, q1 +.endr +.endm + + + +.syntax unified +.text +.thumb +vabs.p8 q0, q1 +vabs.p16 q0, q1 +vabs.u8 q0, q1 +vabs.u16 q0, q1 +vabs.u32 q0, q1 +vabs.f16 q0, q1 +vabs.f32 q0, q1 +vabs.s64 q0, q1 +cond vabs +vneg.p8 q0, q1 +vneg.p16 q0, q1 +vneg.u8 q0, q1 +vneg.u16 q0, q1 +vneg.u32 q0, q1 +vneg.f16 q0, q1 +vneg.f32 q0, q1 +vneg.s64 q0, q1 +cond vneg +it eq +vnegeq.s32 q0, q1 +vnegeq.s32 q0, q1 +vpst +vneg.s32 q0, q1 +vnegt.s32 q0, q1 + diff --git a/gas/testsuite/gas/arm/mve-vabsneg-bad-2.d b/gas/testsuite/gas/arm/mve-vabsneg-bad-2.d new file mode 100644 index 00000000000..14d0137fd0b --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vabsneg-bad-2.d @@ -0,0 +1,6 @@ +#name: bad MVE FP VABS and VNEG instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vabsneg-bad-2.l + +.*: +file format .*arm.* + diff --git a/gas/testsuite/gas/arm/mve-vabsneg-bad-2.l b/gas/testsuite/gas/arm/mve-vabsneg-bad-2.l new file mode 100644 index 00000000000..26bd0f49c9f --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vabsneg-bad-2.l @@ -0,0 +1,29 @@ +[^:]*: Assembler messages: +[^:]*:13: Error: bad type in SIMD instruction -- `vabs.p8 q0,q1' +[^:]*:14: Error: bad type in SIMD instruction -- `vabs.p16 q0,q1' +[^:]*:15: Error: bad type in SIMD instruction -- `vabs.u8 q0,q1' +[^:]*:16: Error: bad type in SIMD instruction -- `vabs.u16 q0,q1' +[^:]*:17: Error: bad type in SIMD instruction -- `vabs.u32 q0,q1' +[^:]*:18: Error: bad type in SIMD instruction -- `vabs.s64 q0,q1' +[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:20: Error: bad type in SIMD instruction -- `vneg.p8 q0,q1' +[^:]*:21: Error: bad type in SIMD instruction -- `vneg.p16 q0,q1' +[^:]*:22: Error: bad type in SIMD instruction -- `vneg.u8 q0,q1' +[^:]*:23: Error: bad type in SIMD instruction -- `vneg.u16 q0,q1' +[^:]*:24: Error: bad type in SIMD instruction -- `vneg.u32 q0,q1' +[^:]*:25: Error: bad type in SIMD instruction -- `vneg.s64 q0,q1' +[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:28: Error: syntax error -- `vnegeq.f32 q0,q1' +[^:]*:29: Error: syntax error -- `vnegeq.f32 q0,q1' +[^:]*:31: Error: instruction missing MVE vector predication code -- `vneg.f32 q0,q1' +[^:]*:32: Error: vector predicated instruction should be in VPT/VPST block -- `vnegt.f32 q0,q1' diff --git a/gas/testsuite/gas/arm/mve-vabsneg-bad-2.s b/gas/testsuite/gas/arm/mve-vabsneg-bad-2.s new file mode 100644 index 00000000000..aff2e410ab0 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vabsneg-bad-2.s @@ -0,0 +1,32 @@ +.macro cond op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().s32 q0, q1 +.endr +.endm + + + +.syntax unified +.text +.thumb +vabs.p8 q0, q1 +vabs.p16 q0, q1 +vabs.u8 q0, q1 +vabs.u16 q0, q1 +vabs.u32 q0, q1 +vabs.s64 q0, q1 +cond vabs +vneg.p8 q0, q1 +vneg.p16 q0, q1 +vneg.u8 q0, q1 +vneg.u16 q0, q1 +vneg.u32 q0, q1 +vneg.s64 q0, q1 +cond vneg +it eq +vnegeq.f32 q0, q1 +vnegeq.f32 q0, q1 +vpst +vneg.f32 q0, q1 +vnegt.f32 q0, q1 -- 2.30.2