From 4862ecb4bbd49b45dd2e374122ecbdb0121ff822 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 7 Apr 2020 19:46:03 +0100
Subject: [PATCH] try making CR bitrange 32..63 not 0..31

---
 src/soc/decoder/isa/caller.py     |  3 ++-
 src/soc/decoder/power_fields.py   |  2 +-
 src/soc/decoder/selectable_int.py | 13 ++++++++++---
 3 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index deb30fc7..81a294d2 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -148,7 +148,8 @@ class ISACaller:
         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 
         # create CR then allow portions of it to be "selectable" (below)
-        self.cr = SelectableInt(0, 32) # TODO, must be bits range 32-63 not 0-31
+        self._cr = SelectableInt(0, 64) # underlying reg
+        self.cr = FieldSelectableInt(self._cr, list(range(32,64)))
 
         # "undefined", just set to variable-bit-width int (use exts "max")
         self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
diff --git a/src/soc/decoder/power_fields.py b/src/soc/decoder/power_fields.py
index 4e7bee09..9dc07b8e 100644
--- a/src/soc/decoder/power_fields.py
+++ b/src/soc/decoder/power_fields.py
@@ -10,7 +10,7 @@ class BitRange(OrderedDict):
         if isinstance(subscript, slice):
             return list(self)[subscript]
         else:
-            return self[subscript]
+            return OrderedDict.__getitem__(self, subscript)
 
 
 def decode_instructions(form):
diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py
index 78cccc29..c4698c01 100644
--- a/src/soc/decoder/selectable_int.py
+++ b/src/soc/decoder/selectable_int.py
@@ -5,6 +5,8 @@ from operator import (add, sub, mul, truediv, mod, or_, and_, xor, neg, inv)
 
 
 def check_extsign(a, b):
+    if isinstance(b, FieldSelectableInt):
+        b = b.get_range()
     if b.bits != 256:
         return b
     return SelectableInt(b.value, a.bits)
@@ -23,8 +25,12 @@ class FieldSelectableInt:
         self.br = br # map of indices.
 
     def eq(self, b):
-        self.si = copy(b.si)
-        self.br = copy(b.br)
+        if isinstance(b, SelectableInt):
+            for i in range(b.bits):
+                self[i] = b[i]
+        else:
+            self.si = copy(b.si)
+            self.br = copy(b.br)
 
     def _op(self, op, b):
         vi = self.get_range()
@@ -37,12 +43,13 @@ class FieldSelectableInt:
         return self.merge(vi)
 
     def __getitem__(self, key):
+        print ("getitem", key, self.br)
         key = self.br[key] # don't do POWER 1.3.4 bit-inversion
         return self.si[key]
 
     def __setitem__(self, key, value):
         key = self.br[key] # don't do POWER 1.3.4 bit-inversion
-        return self.si__setitem__(key, value)
+        return self.si.__setitem__(key, value)
 
     def __negate__(self):
         return self._op1(negate)
-- 
2.30.2