From 48701f69cf040b06f60b858e3ae047b0557ea9dc Mon Sep 17 00:00:00 2001 From: klehman Date: Tue, 7 Sep 2021 11:47:32 -0400 Subject: [PATCH] added assertion to regression_rlwnm --- src/openpower/decoder/isa/test_caller_shift_rot.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/openpower/decoder/isa/test_caller_shift_rot.py b/src/openpower/decoder/isa/test_caller_shift_rot.py index c143c1a9..e0e32056 100644 --- a/src/openpower/decoder/isa/test_caller_shift_rot.py +++ b/src/openpower/decoder/isa/test_caller_shift_rot.py @@ -16,6 +16,7 @@ class DecoderTestCase(FHDLTestCase): initial_regs[2] = 11 with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs) + self.assertEqual(sim.gpr(3), SelectableInt(0x8800, 64)) def test_case_srw_1(self): lst = ["sraw 3, 1, 2"] -- 2.30.2