From 487d28736e57462b88a2f2c734a955f5065482b0 Mon Sep 17 00:00:00 2001 From: colepoirier Date: Tue, 2 Jun 2020 16:41:37 -0700 Subject: [PATCH] Implement TRAP instructions OP_RFID and OP_SC --- src/soc/fu/trap/main_stage.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index bbd00b64..03e5c2e4 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -163,7 +163,8 @@ class TrapMainStage(PipeModBase): ctrl_tmp.msr(MSR_DR) <= '1'; end if; """ - pass + comb += self.o.msr.data.eq(Cat(b[63:31], b[26:22], b[15:0])) + comb += self.o.msr.ok.eq(a) # TODO with m.Case(InternalOp.OP_SC): @@ -173,7 +174,8 @@ class TrapMainStage(PipeModBase): ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64)); ctrl_tmp.srr1 <= msr_copy(ctrl.msr); """ - pass + comb += self.o.nia.eq(0xC00) + comb += self.o.nia.ok.eq(1) #with m.Case(InternalOp.OP_ADDPCIS): # pass -- 2.30.2