From 48c7f5b88116c894d76209db0f47216ed5ccd333 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Mon, 11 Jan 2021 18:03:21 +0000 Subject: [PATCH] aarch64: Add support for unpacked SVE mult, max and min This patch makes the SVE_INT_BINARY_IMM patterns support unpacked arithmetic, covering MUL, SMAX, SMIN, UMAX and UMIN. For min and max, the type suffix must be taken from the element size rather than the container size. The XFAILs are due to PR98602. gcc/ * config/aarch64/aarch64-sve.md (3) (@aarch64_pred_) (*post_ra_3): Extend from SVE_FULL_I to SVE_I. gcc/testsuite/ PR testsuite/98602 * g++.target/aarch64/sve/max_1.C: New test. * g++.target/aarch64/sve/min_1.C: Likewise. * gcc.target/aarch64/sve/mul_2.c: Likewise. --- gcc/config/aarch64/aarch64-sve.md | 30 ++++---- gcc/testsuite/g++.target/aarch64/sve/max_1.C | 73 ++++++++++++++++++++ gcc/testsuite/g++.target/aarch64/sve/min_1.C | 73 ++++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/sve/mul_2.c | 52 ++++++++++++++ 4 files changed, 213 insertions(+), 15 deletions(-) create mode 100644 gcc/testsuite/g++.target/aarch64/sve/max_1.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/min_1.C create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/mul_2.c diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index a58324da869..697a55e1cad 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -3628,12 +3628,12 @@ ;; Unpredicated integer binary operations that have an immediate form. (define_expand "3" - [(set (match_operand:SVE_FULL_I 0 "register_operand") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand") + (unspec:SVE_I [(match_dup 3) - (SVE_INT_BINARY_IMM:SVE_FULL_I - (match_operand:SVE_FULL_I 1 "register_operand") - (match_operand:SVE_FULL_I 2 "aarch64_sve__operand"))] + (SVE_INT_BINARY_IMM:SVE_I + (match_operand:SVE_I 1 "register_operand") + (match_operand:SVE_I 2 "aarch64_sve__operand"))] UNSPEC_PRED_X))] "TARGET_SVE" { @@ -3647,12 +3647,12 @@ ;; and would make the instruction seem less uniform to the register ;; allocator. (define_insn_and_split "@aarch64_pred_" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, w, ?&w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w, ?&w") + (unspec:SVE_I [(match_operand: 1 "register_operand" "Upl, Upl, Upl, Upl") - (SVE_INT_BINARY_IMM:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "%0, 0, w, w") - (match_operand:SVE_FULL_I 3 "aarch64_sve__operand" ", w, , w"))] + (SVE_INT_BINARY_IMM:SVE_I + (match_operand:SVE_I 2 "register_operand" "%0, 0, w, w") + (match_operand:SVE_I 3 "aarch64_sve__operand" ", w, , w"))] UNSPEC_PRED_X))] "TARGET_SVE" "@ @@ -3665,7 +3665,7 @@ "&& reload_completed && !register_operand (operands[3], mode)" [(set (match_dup 0) - (SVE_INT_BINARY_IMM:SVE_FULL_I (match_dup 2) (match_dup 3)))] + (SVE_INT_BINARY_IMM:SVE_I (match_dup 2) (match_dup 3)))] "" [(set_attr "movprfx" "*,*,yes,yes")] ) @@ -3674,10 +3674,10 @@ ;; These are generated by splitting a predicated instruction whose ;; predicate is unused. (define_insn "*post_ra_3" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (SVE_INT_BINARY_IMM:SVE_FULL_I - (match_operand:SVE_FULL_I 1 "register_operand" "0, w") - (match_operand:SVE_FULL_I 2 "aarch64_sve__immediate")))] + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (SVE_INT_BINARY_IMM:SVE_I + (match_operand:SVE_I 1 "register_operand" "0, w") + (match_operand:SVE_I 2 "aarch64_sve__immediate")))] "TARGET_SVE && reload_completed" "@ \t%0., %0., #%2 diff --git a/gcc/testsuite/g++.target/aarch64/sve/max_1.C b/gcc/testsuite/g++.target/aarch64/sve/max_1.C new file mode 100644 index 00000000000..caf9d7cd9bb --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/max_1.C @@ -0,0 +1,73 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */ + +#include + +#define TEST_OP_IMM(TYPE, OP, NAME, AMT) \ + TYPE test##_##TYPE##_##NAME (TYPE a) { return a > AMT ? a : AMT; } + +#define TEST_OP(TYPE, MINV, MAXV) \ + TYPE test##_##TYPE##_reg (TYPE a, TYPE b) { return a > b ? a : b; } \ + TEST_OP_IMM (TYPE, OP, a, MINV) \ + TEST_OP_IMM (TYPE, OP, b, 50) \ + TEST_OP_IMM (TYPE, OP, c, MAXV) + +#define TEST_TYPE(TYPE, SIZE, MINV, MAXV) \ + typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \ + TEST_OP (TYPE##SIZE, MINV, MAXV) + +TEST_TYPE (int8_t, 32, -100, 100) +TEST_TYPE (uint8_t, 32, 2, 250) + +TEST_TYPE (int8_t, 64, -110, 110) +TEST_TYPE (uint8_t, 64, 3, 253) +TEST_TYPE (int16_t, 64, -128, 127) +TEST_TYPE (uint16_t, 64, 4, 255) + +TEST_TYPE (int8_t, 128, -120, 120) +TEST_TYPE (uint8_t, 128, 5, 251) +TEST_TYPE (int16_t, 128, -128, 127) +TEST_TYPE (uint16_t, 128, 6, 255) +TEST_TYPE (int32_t, 128, -128, 127) +TEST_TYPE (uint32_t, 128, 7, 255) + +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #-100\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #-110\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #-120\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.h, z[0-9]+\.h, #-128\n} 2 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.s, z[0-9]+\.s, #-128\n} 1 { xfail *-*-* } } } */ + +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #50\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.h, z[0-9]+\.h, #50\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.s, z[0-9]+\.s, #50\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #100\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #110\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #120\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.h, z[0-9]+\.h, #127\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.s, z[0-9]+\.s, #127\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #2\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #3\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, z[0-9]+\.h, #4\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #5\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, z[0-9]+\.h, #6\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.s, z[0-9]+\.s, #7\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #50\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, z[0-9]+\.h, #50\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.s, z[0-9]+\.s, #50\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #250\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #251\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #253\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, z[0-9]+\.h, #255\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.s, z[0-9]+\.s, #255\n} 1 } } */ diff --git a/gcc/testsuite/g++.target/aarch64/sve/min_1.C b/gcc/testsuite/g++.target/aarch64/sve/min_1.C new file mode 100644 index 00000000000..9c84690cd1b --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/min_1.C @@ -0,0 +1,73 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */ + +#include + +#define TEST_OP_IMM(TYPE, OP, NAME, AMT) \ + TYPE test##_##TYPE##_##NAME (TYPE a) { return a < AMT ? a : AMT; } + +#define TEST_OP(TYPE, MINV, MAXV) \ + TYPE test##_##TYPE##_reg (TYPE a, TYPE b) { return a < b ? a : b; } \ + TEST_OP_IMM (TYPE, OP, a, MINV) \ + TEST_OP_IMM (TYPE, OP, b, 50) \ + TEST_OP_IMM (TYPE, OP, c, MAXV) + +#define TEST_TYPE(TYPE, SIZE, MINV, MAXV) \ + typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \ + TEST_OP (TYPE##SIZE, MINV, MAXV) + +TEST_TYPE (int8_t, 32, -100, 100) +TEST_TYPE (uint8_t, 32, 2, 250) + +TEST_TYPE (int8_t, 64, -110, 110) +TEST_TYPE (uint8_t, 64, 3, 253) +TEST_TYPE (int16_t, 64, -128, 127) +TEST_TYPE (uint16_t, 64, 4, 255) + +TEST_TYPE (int8_t, 128, -120, 120) +TEST_TYPE (uint8_t, 128, 5, 251) +TEST_TYPE (int16_t, 128, -128, 127) +TEST_TYPE (uint16_t, 128, 6, 255) +TEST_TYPE (int32_t, 128, -128, 127) +TEST_TYPE (uint32_t, 128, 7, 255) + +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #-100\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #-110\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #-120\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.h, z[0-9]+\.h, #-128\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.s, z[0-9]+\.s, #-128\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #50\n} 3 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.h, z[0-9]+\.h, #50\n} 2 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.s, z[0-9]+\.s, #50\n} 1 { xfail *-*-* } } } */ + +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #100\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #110\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #120\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.h, z[0-9]+\.h, #127\n} 2 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.s, z[0-9]+\.s, #127\n} 1 { xfail *-*-* } } } */ + +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #2\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #3\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, z[0-9]+\.h, #4\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #5\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, z[0-9]+\.h, #6\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.s, z[0-9]+\.s, #7\n} 1 { xfail *-*-* } } } */ + +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #50\n} 3 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, z[0-9]+\.h, #50\n} 2 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.s, z[0-9]+\.s, #50\n} 1 { xfail *-*-* } } } */ + +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #250\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #251\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #253\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, z[0-9]+\.h, #255\n} 2 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.s, z[0-9]+\.s, #255\n} 1 { xfail *-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/mul_2.c b/gcc/testsuite/gcc.target/aarch64/sve/mul_2.c new file mode 100644 index 00000000000..ff049f5bec0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/mul_2.c @@ -0,0 +1,52 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */ + +#include + +#define TEST_OP_IMM(TYPE, OP, NAME, AMT) \ + TYPE test##_##TYPE##_##NAME (TYPE a) { return a * AMT; } + +#define TEST_OP(TYPE, MINV, MAXV) \ + TYPE test##_##TYPE##_reg (TYPE a, TYPE b) { return a * b; } \ + TEST_OP_IMM (TYPE, OP, a, MINV) \ + TEST_OP_IMM (TYPE, OP, b, 50) \ + TEST_OP_IMM (TYPE, OP, c, MAXV) + +#define TEST_TYPE(TYPE, SIZE, MINV, MAXV) \ + typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \ + TEST_OP (TYPE##SIZE, MINV, MAXV) + +TEST_TYPE (int8_t, 32, -100, 100) +TEST_TYPE (uint8_t, 32, 2, 250) + +TEST_TYPE (int8_t, 64, -110, 110) +TEST_TYPE (uint8_t, 64, 3, 253) +TEST_TYPE (int16_t, 64, -128, 123) +TEST_TYPE (uint16_t, 64, 3, 255) + +TEST_TYPE (int8_t, 128, -120, 120) +TEST_TYPE (uint8_t, 128, 4, 251) +TEST_TYPE (int16_t, 128, -128, 123) +TEST_TYPE (uint16_t, 128, 2, 255) +TEST_TYPE (int32_t, 128, -128, 123) +TEST_TYPE (uint32_t, 128, 4, 255) + +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #-100\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #-110\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #-120\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.h, z[0-9]+\.h, #-128\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.s, z[0-9]+\.s, #-128\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #50\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.h, z[0-9]+\.h, #50\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.s, z[0-9]+\.s, #50\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #100\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #110\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #120\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.h, z[0-9]+\.h, #123\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.s, z[0-9]+\.s, #123\n} 1 } } */ -- 2.30.2