From 48d000a397f22463d03cdd4f7d91992c79316a39 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 4 Jun 2022 22:47:22 +0100 Subject: [PATCH] --- openpower/sv.mdwn | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn index e16f700f8..f7117b08e 100644 --- a/openpower/sv.mdwn +++ b/openpower/sv.mdwn @@ -49,6 +49,16 @@ Advantages of these design principles: but off of Vectorisation ISAs as well. No more separate Vector instructions. +Comparative instruction count: + +* ARM NEON SIMD: around 2,000 instructions, prerequisite: ARM Scalar. +* ARM SVE: around 4,000 instructions, prerequisite: NEON. +* ARM SVE2: around 1,000 instructions, prerequisite: SVE +* Intel AVX-512: around 4,000 instructions, prerequisite AVX2 etc. +* RISV-V RVV: 192 instructions, prerequisite 96 Scalar RV64GC instructions +* SVP64: **four** instructions, prerequisite SFS (150) or + SFFS (214) Compliancy Subsets + # Major opcodes summary Please be advised that even though below is entirely DRAFT status, there -- 2.30.2