From 48da47c4c2b330409e485ee756f222cdc1839211 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 15 Jul 2020 11:18:27 +0100 Subject: [PATCH] no need to check individual port members, just check the Record (dut.i.ctx.op) --- src/soc/fu/spr/formal/proof_main_stage.py | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/src/soc/fu/spr/formal/proof_main_stage.py b/src/soc/fu/spr/formal/proof_main_stage.py index 457f89a1..b831bc63 100644 --- a/src/soc/fu/spr/formal/proof_main_stage.py +++ b/src/soc/fu/spr/formal/proof_main_stage.py @@ -57,13 +57,16 @@ class Driver(Elaboratable): ca_in.eq(AnyConst(0b11)), so_in.eq(AnyConst(1))] + # and for the context muxid + width = dut.i.ctx.muxid.width + comb += dut.i.ctx.muxid.eq(AnyConst(width)) + + # assign the PowerDecode2 operation subset comb += dut.i.ctx.op.eq(rec) - # Assert that op gets copied from the input to output - for rec_sig in rec.ports(): - name = rec_sig.name - dut_sig = getattr(dut.o.ctx.op, name) - comb += Assert(dut_sig == rec_sig) + # check that the operation (op) is passed through (and muxid) + comb += Assert(dut.o.ctx.op == dut.i.ctx.op ) + comb += Assert(dut.o.ctx.muxid == dut.i.ctx.muxid ) return m -- 2.30.2