From 48e071b306a7491aa2aaffcc711e4f74a51d1979 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 6 Mar 2021 00:30:42 +0000 Subject: [PATCH] add blackbox SPBlock 4k SRAM module --- .../non_generated/full_core_4_4ksram_ls180.il | 207 +++++++++--------- 1 file changed, 109 insertions(+), 98 deletions(-) diff --git a/experiments9/non_generated/full_core_4_4ksram_ls180.il b/experiments9/non_generated/full_core_4_4ksram_ls180.il index f056d58..8c60866 100644 --- a/experiments9/non_generated/full_core_4_4ksram_ls180.il +++ b/experiments9/non_generated/full_core_4_4ksram_ls180.il @@ -28841,6 +28841,21 @@ module \SHIFT_ROT_dec31_dec_sub27 end connect \opcode_switch \opcode_in [10:6] end +attribute \src "SPBlock_512W64B8W.v:2.1-7.10" +attribute \cells_not_processed 1 +attribute \blackbox 1 +module \SPBlock_512W64B8W + attribute \src "SPBlock_512W64B8W.v:2.38-2.39" + wire width 9 input 1 \a + attribute \src "SPBlock_512W64B8W.v:6.11-6.14" + wire input 5 \clk + attribute \src "SPBlock_512W64B8W.v:3.18-3.19" + wire width 64 input 2 \d + attribute \src "SPBlock_512W64B8W.v:4.19-4.20" + wire width 64 output 3 \q + attribute \src "SPBlock_512W64B8W.v:5.17-5.19" + wire width 8 input 4 \we +end attribute \src "libresoc.v:20053.1-20381.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31" @@ -248610,24 +248625,24 @@ module \ls180 wire \builder_sync_rhs_array_muxed6 attribute \src "ls180.v:2011.6-2011.18" wire \builder_wait - attribute \src "ls180.v:9.19-9.23" - wire width 3 input 5 \eint + attribute \src "ls180.v:11.19-11.23" + wire width 3 input 7 \eint attribute \src "ls180.v:175.12-175.18" wire width 3 \eint_1 - attribute \src "ls180.v:10.20-10.26" - wire width 16 input 6 \gpio_i - attribute \src "ls180.v:11.20-11.26" - wire width 16 output 7 \gpio_o - attribute \src "ls180.v:12.20-12.27" - wire width 16 output 8 \gpio_oe - attribute \src "ls180.v:39.14-39.21" - wire output 35 \i2c_scl - attribute \src "ls180.v:40.13-40.22" - wire input 36 \i2c_sda_i - attribute \src "ls180.v:41.14-41.23" - wire output 37 \i2c_sda_o - attribute \src "ls180.v:42.14-42.24" - wire output 38 \i2c_sda_oe + attribute \src "ls180.v:7.20-7.26" + wire width 16 input 3 \gpio_i + attribute \src "ls180.v:8.20-8.26" + wire width 16 output 4 \gpio_o + attribute \src "ls180.v:9.20-9.27" + wire width 16 output 5 \gpio_oe + attribute \src "ls180.v:24.14-24.21" + wire output 20 \i2c_scl + attribute \src "ls180.v:25.13-25.22" + wire input 21 \i2c_sda_i + attribute \src "ls180.v:26.14-26.23" + wire output 22 \i2c_sda_o + attribute \src "ls180.v:27.14-27.24" + wire output 23 \i2c_sda_oe attribute \src "ls180.v:49.13-49.21" wire input 45 \jtag_tck attribute \src "ls180.v:50.13-50.21" @@ -248986,19 +249001,19 @@ module \ls180 wire width 64 \main_libresocsim_libresoc2 attribute \src "ls180.v:169.12-169.45" wire width 2 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:176.13-176.67" + attribute \src "ls180.v:171.13-171.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:177.13-177.67" + attribute \src "ls180.v:172.13-172.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:178.13-178.68" + attribute \src "ls180.v:173.13-173.68" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:200.6-200.61" + attribute \src "ls180.v:188.6-188.61" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:201.6-201.63" + attribute \src "ls180.v:189.6-189.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:202.6-202.63" + attribute \src "ls180.v:190.6-190.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:203.6-203.64" + attribute \src "ls180.v:191.6-191.64" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe attribute \src "ls180.v:196.6-196.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk @@ -249008,43 +249023,43 @@ module \ls180 wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o attribute \src "ls180.v:199.6-199.67" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:179.13-179.68" + attribute \src "ls180.v:176.13-176.68" wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:188.12-188.68" + attribute \src "ls180.v:185.12-185.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:185.6-185.65" + attribute \src "ls180.v:182.6-182.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:187.6-187.63" + attribute \src "ls180.v:184.6-184.63" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:186.6-186.64" + attribute \src "ls180.v:183.6-183.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:189.12-189.68" + attribute \src "ls180.v:186.12-186.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:180.13-180.71" + attribute \src "ls180.v:177.13-177.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:181.13-181.71" + attribute \src "ls180.v:178.13-178.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:182.6-182.65" + attribute \src "ls180.v:179.6-179.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:184.6-184.65" + attribute \src "ls180.v:181.6-181.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:183.6-183.64" + attribute \src "ls180.v:180.6-180.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:171.6-171.67" + attribute \src "ls180.v:192.6-192.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:173.6-173.68" + attribute \src "ls180.v:194.6-194.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:174.6-174.68" + attribute \src "ls180.v:195.6-195.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:172.6-172.68" + attribute \src "ls180.v:193.6-193.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:192.6-192.67" + attribute \src "ls180.v:200.6-200.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:194.6-194.68" + attribute \src "ls180.v:202.6-202.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:195.6-195.68" + attribute \src "ls180.v:203.6-203.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - attribute \src "ls180.v:193.6-193.68" + attribute \src "ls180.v:201.6-201.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi attribute \src "ls180.v:72.6-72.40" wire \main_libresocsim_libresoc_dbus_ack @@ -252374,9 +252389,9 @@ module \ls180 wire width 24 input 48 \nc attribute \src "ls180.v:338.6-338.13" wire \por_clk - attribute \src "ls180.v:25.19-25.22" - wire width 2 output 21 \pwm - attribute \src "ls180.v:191.12-191.17" + attribute \src "ls180.v:10.19-10.22" + wire width 2 output 6 \pwm + attribute \src "ls180.v:174.12-174.17" wire width 2 \pwm_1 attribute \src "ls180.v:32.13-32.23" wire output 28 \sdcard_clk @@ -252392,32 +252407,32 @@ module \ls180 wire width 4 output 33 \sdcard_data_o attribute \src "ls180.v:38.13-38.27" wire output 34 \sdcard_data_oe - attribute \src "ls180.v:13.20-13.27" - wire width 13 output 9 \sdram_a - attribute \src "ls180.v:22.19-22.27" - wire width 2 output 18 \sdram_ba - attribute \src "ls180.v:19.13-19.24" - wire output 15 \sdram_cas_n - attribute \src "ls180.v:21.13-21.22" - wire output 17 \sdram_cke - attribute \src "ls180.v:24.13-24.24" - wire output 20 \sdram_clock - attribute \src "ls180.v:190.6-190.19" + attribute \src "ls180.v:12.20-12.27" + wire width 13 output 8 \sdram_a + attribute \src "ls180.v:21.19-21.27" + wire width 2 output 17 \sdram_ba + attribute \src "ls180.v:18.13-18.24" + wire output 14 \sdram_cas_n + attribute \src "ls180.v:20.13-20.22" + wire output 16 \sdram_cke + attribute \src "ls180.v:23.13-23.24" + wire output 19 \sdram_clock + attribute \src "ls180.v:187.6-187.19" wire \sdram_clock_1 - attribute \src "ls180.v:20.13-20.23" - wire output 16 \sdram_cs_n - attribute \src "ls180.v:23.19-23.27" - wire width 2 output 19 \sdram_dm + attribute \src "ls180.v:19.13-19.23" + wire output 15 \sdram_cs_n + attribute \src "ls180.v:22.19-22.27" + wire width 2 output 18 \sdram_dm + attribute \src "ls180.v:13.20-13.30" + wire width 16 input 9 \sdram_dq_i attribute \src "ls180.v:14.20-14.30" - wire width 16 input 10 \sdram_dq_i - attribute \src "ls180.v:15.20-15.30" - wire width 16 output 11 \sdram_dq_o - attribute \src "ls180.v:16.13-16.24" - wire output 12 \sdram_dq_oe - attribute \src "ls180.v:18.13-18.24" - wire output 14 \sdram_ras_n - attribute \src "ls180.v:17.13-17.23" - wire output 13 \sdram_we_n + wire width 16 output 10 \sdram_dq_o + attribute \src "ls180.v:15.13-15.24" + wire output 11 \sdram_dq_oe + attribute \src "ls180.v:17.13-17.24" + wire output 13 \sdram_ras_n + attribute \src "ls180.v:16.13-16.23" + wire output 12 \sdram_we_n attribute \src "ls180.v:2760.6-2760.15" wire \sdrio_clk attribute \src "ls180.v:2761.6-2761.17" @@ -252556,22 +252571,22 @@ module \ls180 wire \sdrio_clk_8 attribute \src "ls180.v:2769.6-2769.17" wire \sdrio_clk_9 - attribute \src "ls180.v:5.13-5.26" - wire output 1 \spimaster_clk - attribute \src "ls180.v:7.13-7.27" - wire output 3 \spimaster_cs_n - attribute \src "ls180.v:8.13-8.27" - wire input 4 \spimaster_miso - attribute \src "ls180.v:6.13-6.27" - wire output 2 \spimaster_mosi - attribute \src "ls180.v:26.13-26.26" - wire output 22 \spisdcard_clk - attribute \src "ls180.v:28.13-28.27" - wire output 24 \spisdcard_cs_n + attribute \src "ls180.v:28.13-28.26" + wire output 24 \spimaster_clk + attribute \src "ls180.v:30.13-30.27" + wire output 26 \spimaster_cs_n + attribute \src "ls180.v:31.13-31.27" + wire input 27 \spimaster_miso attribute \src "ls180.v:29.13-29.27" - wire input 25 \spisdcard_miso - attribute \src "ls180.v:27.13-27.27" - wire output 23 \spisdcard_mosi + wire output 25 \spimaster_mosi + attribute \src "ls180.v:39.13-39.26" + wire output 35 \spisdcard_clk + attribute \src "ls180.v:41.13-41.27" + wire output 37 \spisdcard_cs_n + attribute \src "ls180.v:42.13-42.27" + wire input 38 \spisdcard_miso + attribute \src "ls180.v:40.13-40.27" + wire output 36 \spisdcard_mosi attribute \src "ls180.v:43.13-43.20" wire input 39 \sys_clk attribute \src "ls180.v:336.6-336.15" @@ -252586,10 +252601,10 @@ module \ls180 wire input 40 \sys_rst attribute \src "ls180.v:337.6-337.15" wire \sys_rst_1 - attribute \src "ls180.v:31.13-31.20" - wire input 27 \uart_rx - attribute \src "ls180.v:30.13-30.20" - wire output 26 \uart_tx + attribute \src "ls180.v:6.13-6.20" + wire input 2 \uart_rx + attribute \src "ls180.v:5.13-5.20" + wire output 1 \uart_tx attribute \src "ls180.v:10348.12-10348.15" memory width 64 size 64 \mem attribute \src "ls180.v:10376.12-10376.17" @@ -295621,14 +295636,14 @@ module \ls180 end attribute \src "ls180.v:7702.1-10346.4" process $proc$ls180.v:7702$2573 + assign $0\uart_tx[0:0] \uart_tx + assign $0\pwm[1:0] \pwm assign $0\spimaster_clk[0:0] \spimaster_clk assign $0\spimaster_mosi[0:0] \spimaster_mosi assign { } { } - assign $0\pwm[1:0] \pwm assign $0\spisdcard_clk[0:0] \spisdcard_clk assign $0\spisdcard_mosi[0:0] \spisdcard_mosi assign { } { } - assign $0\uart_tx[0:0] \uart_tx assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage assign { } { } assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage @@ -300201,14 +300216,14 @@ module \ls180 assign $0\main_libresocsim_scratch_storage[31:0] 305419896 assign $0\main_libresocsim_scratch_re[0:0] 1'0 assign $0\main_libresocsim_bus_errors[31:0] 0 + assign $0\uart_tx[0:0] 1'1 + assign $0\pwm[1:0] 2'00 assign $0\spimaster_clk[0:0] 1'0 assign $0\spimaster_mosi[0:0] 1'0 assign $0\spimaster_cs_n[0:0] 1'0 - assign $0\pwm[1:0] 2'00 assign $0\spisdcard_clk[0:0] 1'0 assign $0\spisdcard_mosi[0:0] 1'0 assign $0\spisdcard_cs_n[0:0] 1'0 - assign $0\uart_tx[0:0] 1'1 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 assign $0\main_libresocsim_load_storage[31:0] 0 assign $0\main_libresocsim_load_re[0:0] 1'0 @@ -300496,14 +300511,14 @@ module \ls180 case end sync posedge \sys_clk_1 + update \uart_tx $0\uart_tx[0:0] + update \pwm $0\pwm[1:0] update \spimaster_clk $0\spimaster_clk[0:0] update \spimaster_mosi $0\spimaster_mosi[0:0] update \spimaster_cs_n $0\spimaster_cs_n[0:0] - update \pwm $0\pwm[1:0] update \spisdcard_clk $0\spisdcard_clk[0:0] update \spisdcard_mosi $0\spisdcard_mosi[0:0] update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] - update \uart_tx $0\uart_tx[0:0] update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] @@ -396044,7 +396059,6 @@ module \sram4k_0 connect \B \sram4k_0_wb__stb connect \Y $and$libresoc.v:189604$13136_Y end - attribute \blackbox 1 attribute \module_not_derived 1 attribute \src "libresoc.v:189608.21-189614.4" cell \SPBlock_512W64B8W \U$$0 @@ -396370,7 +396384,6 @@ module \sram4k_1 connect \B \sram4k_1_wb__stb connect \Y $and$libresoc.v:189749$13149_Y end - attribute \blackbox 1 attribute \module_not_derived 1 attribute \src "libresoc.v:189753.21-189759.4" cell \SPBlock_512W64B8W \U$$0 @@ -396696,7 +396709,6 @@ module \sram4k_2 connect \B \sram4k_2_wb__stb connect \Y $and$libresoc.v:189894$13162_Y end - attribute \blackbox 1 attribute \module_not_derived 1 attribute \src "libresoc.v:189898.21-189904.4" cell \SPBlock_512W64B8W \U$$0 @@ -397022,7 +397034,6 @@ module \sram4k_3 connect \B \sram4k_3_wb__stb connect \Y $and$libresoc.v:190039$13175_Y end - attribute \blackbox 1 attribute \module_not_derived 1 attribute \src "libresoc.v:190043.21-190049.4" cell \SPBlock_512W64B8W \U$$0 -- 2.30.2