From 48fd2fd70295b163b1dd41bc9bc9ddbf258b7bf7 Mon Sep 17 00:00:00 2001
From: Las Safin <me@las.rs>
Date: Sat, 11 Sep 2021 17:07:34 +0000
Subject: [PATCH] wip

---
 flake.nix             | 19 +++++++++++++++++--
 nix/bigfloat.nix      | 20 ++++++++++++++++++++
 nix/ieee754fpu.nix    | 21 +++++++++++++++++++++
 nix/openpower-isa.nix | 19 +++++++++++++++++++
 nix/verilog.nix       | 33 +++++++++++++++++++++++++++++++++
 5 files changed, 110 insertions(+), 2 deletions(-)
 create mode 100644 nix/bigfloat.nix
 create mode 100644 nix/ieee754fpu.nix
 create mode 100644 nix/openpower-isa.nix
 create mode 100644 nix/verilog.nix

diff --git a/flake.nix b/flake.nix
index 3911dde3..5b1e57a5 100644
--- a/flake.nix
+++ b/flake.nix
@@ -14,9 +14,24 @@
       forAllSystems = nixpkgs.lib.genAttrs supportedSystems;
 
       nixpkgsFor = forAllSystems (system: import nixpkgs { inherit system; overlays = [ self.overlay ]; });
-
     in
     {
-      overlay = final: prev: {};
+      overlay = self: super: {
+        python3Packages = super.python3Packages.override {
+          overrides = pself: psuper: {
+            libresoc-ieee754fpu = pself.callPackage ./nix/ieee754fpu.nix {};
+            libresoc-openpower-isa = pself.callPackage ./nix/openpower-isa.nix {};
+            bigfloat = pself.callPackage ./nix/bigfloat.nix {};
+          };
+        };
+
+        libresoc-verilog = self.callPackage (import ./nix/verilog.nix { inherit version; }) {};
+      };
+
+      packages = forAllSystems (system: {
+        verilog = nixpkgsFor.${system}.libresoc-verilog;
+      });
+
+      defaultPackage = forAllSystems (system: self.packages.${system}.verilog);
     };
 }
diff --git a/nix/bigfloat.nix b/nix/bigfloat.nix
new file mode 100644
index 00000000..f7675cf6
--- /dev/null
+++ b/nix/bigfloat.nix
@@ -0,0 +1,20 @@
+{ lib, buildPythonPackage, bigfloat, fetchPypi, gmp, mpfr }:
+
+buildPythonPackage rec {
+  pname = "bigfloat";
+  version = "0.4.0";
+
+  buildInputs = [ gmp mpfr ];
+
+  src = fetchPypi {
+    inherit pname version;
+    sha256 = "WLlr3ocqylmJ0T2C66Os8qoblOIhF91yoWulkRsMDLg=";
+  };
+
+  doCheck = false;
+
+  meta = with lib; {
+    homepage = "https://pypi.org/project/bigfloat/";
+    license = licenses.lgpl3Plus;
+  };
+}
diff --git a/nix/ieee754fpu.nix b/nix/ieee754fpu.nix
new file mode 100644
index 00000000..3ec8486d
--- /dev/null
+++ b/nix/ieee754fpu.nix
@@ -0,0 +1,21 @@
+{ lib, buildPythonPackage, bigfloat, fetchgit }:
+
+buildPythonPackage {
+  pname = "libresoc-ieee754fpu";
+  version = "unstable-2021-06-05";
+
+  src = fetchgit {
+    url = "https://git.libre-soc.org/git/ieee754fpu.git";
+    rev = "c62fa3a7ee95832587d7725729dcdb9a002ae015";
+    sha256 = "wbr1vGFzUlUtBT6IcRsykADYeksiVoq/LacU/dbRQ0o=";
+  };
+
+  propagatedBuildInputs = [ bigfloat ];
+
+  doCheck = false;
+
+  meta = with lib; {
+    homepage = "https://pypi.org/project/libresoc-ieee754fpu/";
+    license = licenses.lgpl3Plus;
+  };
+}
diff --git a/nix/openpower-isa.nix b/nix/openpower-isa.nix
new file mode 100644
index 00000000..67cd8778
--- /dev/null
+++ b/nix/openpower-isa.nix
@@ -0,0 +1,19 @@
+{ lib, buildPythonPackage, fetchgit }:
+
+buildPythonPackage {
+  pname = "libresoc-openpower-isa";
+  version = "unstable-2021-09-04";
+
+  src = fetchgit {
+    url = "https://git.libre-soc.org/git/openpower-isa.git";
+    rev = "6e43a194f3d07ed5a8daa297187a32746c4c4d3c";
+    sha256 = "0EekUouTQruTXGO5jlPJtqh0DOudghILy0nca5eaZz8=";
+  };
+
+  doCheck = false;
+
+  meta = with lib; {
+    homepage = "https://pypi.org/project/libresoc-openpower-isa/";
+    license = licenses.lgpl3Plus;
+  };
+}
diff --git a/nix/verilog.nix b/nix/verilog.nix
new file mode 100644
index 00000000..55755343
--- /dev/null
+++ b/nix/verilog.nix
@@ -0,0 +1,33 @@
+{ version }:
+
+{ stdenv, python3Packages }:
+
+stdenv.mkDerivation {
+  pname = "libresoc.v";
+  inherit version;
+
+  src = ../.;
+
+  strictDeps = true;
+
+  nativeBuildInputs = with python3Packages; [ python libresoc-ieee754fpu libresoc-openpower-isa ];
+
+  configurePhase = "true";
+
+  buildPhase = ''
+    runHook preBuild
+    python3 src/soc/simple/issuer_verilog.py \
+      --debug=jtag --enable-core --enable-pll \
+      --enable-xics --enable-sram4x4kblock --disable-svp64 \
+      libresoc.v
+    runHook postBuild
+  '';
+
+  installPhase = ''
+    runHook preInstall
+    mv libresoc.v $out
+    runHook postInstall
+  '';
+
+  fixupPhase = "true";
+}
-- 
2.30.2