From 49022364813d0a0f33c5554a881c0c13db130e05 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Oct 2018 02:43:21 +0100 Subject: [PATCH] pass in sign-extend argument for use in non-default bitwidth --- riscv/insn_template_sv.cc | 8 +++++++- riscv/sv.cc | 7 +++++-- riscv/sv_decode.h | 5 ++++- 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc index fecb9d0..3d53d78 100644 --- a/riscv/insn_template_sv.cc +++ b/riscv/insn_template_sv.cc @@ -63,7 +63,13 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc) reg_t target_pred = ~0x0; bool zeroingtarg = false; #endif - sv_insn_t insn(p, sv_enabled, bits, floatintmap, xlen, PRED_ARGS, OFFS_ARGS); + sv_insn_t insn(p, sv_enabled, bits, floatintmap, xlen, PRED_ARGS, OFFS_ARGS, +#ifdef INSN_TYPE_SIGNED + true +#else + false +#endif + ); p->s.set_insn(&insn, xlen); #ifdef USING_NOREGS #include INCLUDEFILE diff --git a/riscv/sv.cc b/riscv/sv.cc index c85c23d..955cf46 100644 --- a/riscv/sv.cc +++ b/riscv/sv.cc @@ -17,9 +17,11 @@ sv_insn_t::sv_insn_t(processor_t *pr, bool _sv_enabled, uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3, uint64_t &p_sp, uint64_t *p_im, int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp, - int *o_imm) : + int *o_imm, + bool _sign) : insn_t(bits), p(pr), src_bitwidth(0), xlen(_xlen), - sv_enabled(_sv_enabled), vloop_continue(false), + sv_enabled(_sv_enabled), signextended(_sign), + vloop_continue(false), at_least_one_reg_vectorised(false), fimap(f), offs_rd(o_rd), offs_rs1(o_rs1), offs_rs2(o_rs2), offs_rs3(o_rs3), offs_sp(o_sp), @@ -165,6 +167,7 @@ reg_spec_t sv_insn_t::remap(uint64_t reg, bool intreg, int *voffs) spec.reg = reg; //+ *voffs; spec.offset = voffs; spec.isvec = r->isvec; + spec.signextend = signextended; return spec; } diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h index a364211..7102dd9 100644 --- a/riscv/sv_decode.h +++ b/riscv/sv_decode.h @@ -31,6 +31,7 @@ struct reg_spec_t reg_t reg; int *offset; bool isvec; + bool signextend; }; class sv_insn_t: public insn_t @@ -41,7 +42,8 @@ public: uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3, uint64_t &p_sp, uint64_t *p_im, int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp, - int *o_imm); + int *o_imm, + bool _sign); uint8_t reg_elwidth(reg_t reg, bool intreg); sv_reg_t rvc_addi4spn_imm() { return sv_reg_t(insn_t::rvc_addi4spn_imm()); } @@ -101,6 +103,7 @@ public: uint8_t src_bitwidth; int xlen; bool sv_enabled; + bool signextended; // cached version of remap: if remap is called multiple times // by an emulated instruction it would increment the loop offset -- 2.30.2