From 490948ca36a1b9dc407930eba0e6dd52c83dac4d Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Fri, 19 Jun 2015 17:22:38 +0000 Subject: [PATCH] aarch64.md (mov:GPF): Don't call force_reg if op1 is an fp zero. gcc/ * config/aarch64/aarch64.md (mov:GPF): Don't call force_reg if op1 is an fp zero. (movsf_aarch64): Change condition from register_operand to aarch64_reg_or_fp_zero for op1. Change type for alternative 6 to load1. Change type for alternative 7 to store1. (movdf_aarch64): Likewise. gcc/testsuite/ * gcc.target/aarch64/fmovd-zero-mem.c: New. * gcc.target/aarch64/fmovd-zero-reg.c: New. * gcc.target/aarch64/fmovf-zero-mem.c: New. * gcc.target/aarch64/fmovf-zero-reg.c: New. * gcc.target/aarch64/fmovld-zero-mem.c: New. * gcc.target/aarch64/fmovld-zero-mem.c: New. * gcc.target/aarch64/fmovd-zero.c: Delete. * gcc.target/aarch64/fmovf-zero.c: Delete. From-SVN: r224673 --- gcc/ChangeLog | 9 +++++++++ gcc/config/aarch64/aarch64.md | 12 +++++++----- gcc/testsuite/ChangeLog | 11 +++++++++++ .../aarch64/{fmovd-zero.c => fmovd-zero-mem.c} | 2 +- gcc/testsuite/gcc.target/aarch64/fmovd-zero-reg.c | 11 +++++++++++ .../aarch64/{fmovf-zero.c => fmovf-zero-mem.c} | 2 +- gcc/testsuite/gcc.target/aarch64/fmovf-zero-reg.c | 11 +++++++++++ gcc/testsuite/gcc.target/aarch64/fmovld-zero-mem.c | 10 ++++++++++ gcc/testsuite/gcc.target/aarch64/fmovld-zero-reg.c | 11 +++++++++++ 9 files changed, 72 insertions(+), 7 deletions(-) rename gcc/testsuite/gcc.target/aarch64/{fmovd-zero.c => fmovd-zero-mem.c} (61%) create mode 100644 gcc/testsuite/gcc.target/aarch64/fmovd-zero-reg.c rename gcc/testsuite/gcc.target/aarch64/{fmovf-zero.c => fmovf-zero-mem.c} (61%) create mode 100644 gcc/testsuite/gcc.target/aarch64/fmovf-zero-reg.c create mode 100644 gcc/testsuite/gcc.target/aarch64/fmovld-zero-mem.c create mode 100644 gcc/testsuite/gcc.target/aarch64/fmovld-zero-reg.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b94b85f4325..d33ca138c60 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2015-06-19 Jim Wilson + + * config/aarch64/aarch64.md (mov:GPF): Don't call force_reg if + op1 is an fp zero. + (movsf_aarch64): Change condition from register_operand to + aarch64_reg_or_fp_zero for op1. Change type for alternative 6 to + load1. Change type for alternative 7 to store1. + (movdf_aarch64): Likewise. + 2015-06-19 James Greenhalgh * config/vax/vax.md: Adjust sign/zero extend patterns to diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 1efe57c91b1..d3f5d5b2063 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -986,7 +986,9 @@ FAIL; } - if (GET_CODE (operands[0]) == MEM) + if (GET_CODE (operands[0]) == MEM + && ! (GET_CODE (operands[1]) == CONST_DOUBLE + && aarch64_float_const_zero_rtx_p (operands[1]))) operands[1] = force_reg (mode, operands[1]); " ) @@ -995,7 +997,7 @@ [(set (match_operand:SF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") (match_operand:SF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], SFmode) - || register_operand (operands[1], SFmode))" + || aarch64_reg_or_fp_zero (operands[1], SFmode))" "@ fmov\\t%s0, %w1 fmov\\t%w0, %s1 @@ -1007,14 +1009,14 @@ str\\t%w1, %0 mov\\t%w0, %w1" [(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\ - f_loads,f_stores,f_loads,f_stores,mov_reg")] + f_loads,f_stores,load1,store1,mov_reg")] ) (define_insn "*movdf_aarch64" [(set (match_operand:DF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") (match_operand:DF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], DFmode) - || register_operand (operands[1], DFmode))" + || aarch64_reg_or_fp_zero (operands[1], DFmode))" "@ fmov\\t%d0, %x1 fmov\\t%x0, %d1 @@ -1026,7 +1028,7 @@ str\\t%x1, %0 mov\\t%x0, %x1" [(set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\ - f_loadd,f_stored,f_loadd,f_stored,mov_reg")] + f_loadd,f_stored,load1,store1,mov_reg")] ) (define_expand "movtf" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e117dee16cf..657f167de0b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,14 @@ +2015-06-19 Jim Wilson + + * gcc.target/aarch64/fmovd-zero-mem.c: New. + * gcc.target/aarch64/fmovd-zero-reg.c: New. + * gcc.target/aarch64/fmovf-zero-mem.c: New. + * gcc.target/aarch64/fmovf-zero-reg.c: New. + * gcc.target/aarch64/fmovld-zero-mem.c: New. + * gcc.target/aarch64/fmovld-zero-mem.c: New. + * gcc.target/aarch64/fmovd-zero.c: Delete. + * gcc.target/aarch64/fmovf-zero.c: Delete. + 2015-06-19 James Greenhalgh * gcc.target/vax/bswapdi-1.c: New. diff --git a/gcc/testsuite/gcc.target/aarch64/fmovd-zero.c b/gcc/testsuite/gcc.target/aarch64/fmovd-zero-mem.c similarity index 61% rename from gcc/testsuite/gcc.target/aarch64/fmovd-zero.c rename to gcc/testsuite/gcc.target/aarch64/fmovd-zero-mem.c index 7e4590afe61..9245c482265 100644 --- a/gcc/testsuite/gcc.target/aarch64/fmovd-zero.c +++ b/gcc/testsuite/gcc.target/aarch64/fmovd-zero-mem.c @@ -7,4 +7,4 @@ foo (double *output) *output = 0.0; } -/* { dg-final { scan-assembler "fmov\\td\[0-9\]+, xzr" } } */ +/* { dg-final { scan-assembler "str\\txzr, \\\[x0\\\]" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fmovd-zero-reg.c b/gcc/testsuite/gcc.target/aarch64/fmovd-zero-reg.c new file mode 100644 index 00000000000..0a3e5940297 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmovd-zero-reg.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void bar (double); +void +foo (void) +{ + bar (0.0); +} + +/* { dg-final { scan-assembler "fmov\\td0, xzr" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fmovf-zero.c b/gcc/testsuite/gcc.target/aarch64/fmovf-zero-mem.c similarity index 61% rename from gcc/testsuite/gcc.target/aarch64/fmovf-zero.c rename to gcc/testsuite/gcc.target/aarch64/fmovf-zero-mem.c index 5050ac31038..518eff0626f 100644 --- a/gcc/testsuite/gcc.target/aarch64/fmovf-zero.c +++ b/gcc/testsuite/gcc.target/aarch64/fmovf-zero-mem.c @@ -7,4 +7,4 @@ foo (float *output) *output = 0.0; } -/* { dg-final { scan-assembler "fmov\\ts\[0-9\]+, wzr" } } */ +/* { dg-final { scan-assembler "str\\twzr, \\\[x0\\\]" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fmovf-zero-reg.c b/gcc/testsuite/gcc.target/aarch64/fmovf-zero-reg.c new file mode 100644 index 00000000000..4213450d6e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmovf-zero-reg.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void bar (float); +void +foo (void) +{ + bar (0.0); +} + +/* { dg-final { scan-assembler "fmov\\ts0, wzr" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fmovld-zero-mem.c b/gcc/testsuite/gcc.target/aarch64/fmovld-zero-mem.c new file mode 100644 index 00000000000..e649404ae07 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmovld-zero-mem.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +foo (long double *output) +{ + *output = 0.0; +} + +/* { dg-final { scan-assembler "stp\\txzr, xzr, \\\[x0\\\]" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fmovld-zero-reg.c b/gcc/testsuite/gcc.target/aarch64/fmovld-zero-reg.c new file mode 100644 index 00000000000..ca602cb381f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmovld-zero-reg.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void bar (long double); +void +foo (void) +{ + bar (0.0); +} + +/* { dg-final { scan-assembler "movi\\tv0\.2d, #0" } } */ -- 2.30.2