From 490be63989595cb20aef4b2b5492d4800c60228b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 8 Jul 2021 22:26:30 +0100 Subject: [PATCH] test MSR.SVF bit set after setvl Vertical-First mode set --- src/openpower/decoder/isa/test_caller_setvl.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py index ef0b1831..f9729138 100644 --- a/src/openpower/decoder/isa/test_caller_setvl.py +++ b/src/openpower/decoder/isa/test_caller_setvl.py @@ -47,6 +47,8 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.svstate.dststep.asint(True), 2) print(" gpr1", sim.gpr(0)) self.assertEqual(sim.gpr(0), SelectableInt(0, 64)) + print(" msr", bin(sim.msr.value)) + self.assertEqual(sim.msr, SelectableInt(1<<(63-6), 64)) def test_setvl_1(self): lst = SVP64Asm(["setvl 1, 0, 9, 0, 1, 1", -- 2.30.2