From 4910b71036830ed04b7b8d1ff0fb98f057fabeb0 Mon Sep 17 00:00:00 2001 From: Konstantinos Margaritis Date: Fri, 28 Apr 2023 16:41:22 +0000 Subject: [PATCH] handle negatives correctly by adding sign bit to final result --- openpower/isa/butterfly.mdwn | 14 ++++++++------ src/openpower/test/alu/maddsubrs_cases.py | 1 + 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/openpower/isa/butterfly.mdwn b/openpower/isa/butterfly.mdwn index 277305a8..555e8abd 100644 --- a/openpower/isa/butterfly.mdwn +++ b/openpower/isa/butterfly.mdwn @@ -18,12 +18,14 @@ Pseudo-code: res1 <- ROTL64(prod1, XLEN-n) res2 <- ROTL64(prod2, XLEN-n) m <- MASK(n, (XLEN-1)) - s1 <- res1[0] - s2 <- res2[0] - smask1 <- ([s1]*XLEN) & ¬m - smask2 <- ([s2]*XLEN) & ¬m - RT <- res1 & m | smask1 - RS <- res2 & m | smask2 + signbit1 <- res1[0] + signbit2 <- res2[0] + smask1 <- ([signbit1]*XLEN) & ¬m + smask2 <- ([signbit2]*XLEN) & ¬m + s64_1 <- [0]*(XLEN-1) || signbit1 + s64_2 <- [0]*(XLEN-1) || signbit2 + RT <- (res1 & m | smask1) + s64_1 + RS <- (res2 & m | smask2) + s64_2 Special Registers Altered: diff --git a/src/openpower/test/alu/maddsubrs_cases.py b/src/openpower/test/alu/maddsubrs_cases.py index 9dd48c97..feace48d 100644 --- a/src/openpower/test/alu/maddsubrs_cases.py +++ b/src/openpower/test/alu/maddsubrs_cases.py @@ -24,5 +24,6 @@ class MADDSUBRSTestCase(TestAccumulatorBase): e = ExpectedState(pc=4) e.intregs[1] = 0x0000aa85 e.intregs[2] = 0xffffffffffff643e + e.intregs[3] = 0x00002d41 self.add_case(Program(lst, bigendian), initial_regs, expected=e) -- 2.30.2