From 491c352da7b656aa3979754e0a03182dfaabdd13 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 26 Mar 2018 21:19:00 +0200 Subject: [PATCH] Add .sv support to "hierarchy -libdir" --- passes/hierarchy/hierarchy.cc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 898763c64..71b0cf622 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -179,6 +179,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check goto loaded_module; } + filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".sv"; + if (check_file_exists(filename)) { + Frontend::frontend_call(design, NULL, filename, "verilog -sv"); + goto loaded_module; + } + filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il"; if (check_file_exists(filename)) { Frontend::frontend_call(design, NULL, filename, "ilang"); -- 2.30.2