From 495b0a058993586948d5c22a577a13142cc7a12a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 23 Feb 2022 14:14:53 +0000 Subject: [PATCH] invert CRG reset on PLL see if it makes any difference also reduce power-on-reset delay --- src/crg.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/crg.py b/src/crg.py index 6fb8dd1..f7baa0a 100644 --- a/src/crg.py +++ b/src/crg.py @@ -58,6 +58,7 @@ class PLL(Elaboratable): assert self.nclkouts < self.nclkouts_max self.clkouts[self.nclkouts] = (cd, freq, phase, margin) #create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts) + print("clock domain", cd.domain, freq, margin, self.nclkouts) self.nclkouts += 1 def compute_config(self): @@ -87,6 +88,7 @@ class PLL(Elaboratable): config["vco"] = vco_freq config["clkfb_div"] = clkfb_div #compute_config_log(self.logger, config) + print ("PLL config", config) return config raise ValueError("No PLL config found") @@ -123,6 +125,7 @@ class PLL(Elaboratable): self.params["o_CLKO{}".format(n_to_l[n])] = clk m = Module() + print ("params", self.params) pll = Instance("EHXPLLL", **self.params) m.submodules.pll = pll return m @@ -196,7 +199,7 @@ class ECPIX5CRG(Elaboratable): ] # Power-on delay (655us) - podcnt = Signal(16, reset=2**16-1) + podcnt = Signal(3, reset=-1) pod_done = Signal() with m.If(podcnt != 0): m.d.rawclk += podcnt.eq(podcnt-1) @@ -209,7 +212,7 @@ class ECPIX5CRG(Elaboratable): cd_init = ClockDomain("init", local=False) cd_sync = ClockDomain("sync", local=False) cd_dramsync = ClockDomain("dramsync", local=False) - m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=reset) + m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~reset) pll.set_clkin_freq(100e6) pll.create_clkout(ClockSignal("sync2x_unbuf"), 2*self.sys_clk_freq) pll.create_clkout(ClockSignal("init"), 25e6) -- 2.30.2