From 495e40d1a5837591d2d3ef98334c556d498e4cae Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 4 Jul 2020 11:00:03 +0100 Subject: [PATCH] reduce compare lengths to *2 rather than *3 --- src/ieee754/div_rem_sqrt_rsqrt/core.py | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py index b9a4ee56..e7208ee5 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py @@ -150,12 +150,16 @@ class DivPipeCoreInterstageData: """ Create a ``DivPipeCoreInterstageData`` instance. """ self.core_config = core_config bw = core_config.bit_width + if core_config.supported == [DP.UDivRem]: + self.compare_len = bw * 2 + else: + self.compare_len = bw * 3 self.divisor_radicand = Signal(bw, reset_less=reset_less) self.operation = DP.create_signal(reset_less=reset_less) self.quotient_root = Signal(bw, reset_less=reset_less) self.root_times_radicand = Signal(bw * 2, reset_less=reset_less) - self.compare_lhs = Signal(bw * 3, reset_less=reset_less) - self.compare_rhs = Signal(bw * 3, reset_less=reset_less) + self.compare_lhs = Signal(self.compare_len, reset_less=reset_less) + self.compare_rhs = Signal(self.compare_len, reset_less=reset_less) def __iter__(self): """ Get member signals. """ @@ -268,11 +272,15 @@ class Trial(Elaboratable): self.current_shift = current_shift self.log2_radix = log2_radix bw = core_config.bit_width + if core_config.supported == [DP.UDivRem]: + self.compare_len = bw * 2 + else: + self.compare_len = bw * 3 self.divisor_radicand = Signal(bw, reset_less=True) self.quotient_root = Signal(bw, reset_less=True) self.root_times_radicand = Signal(bw * 2, reset_less=True) self.compare_rhs = Signal(bw * 3, reset_less=True) - self.trial_compare_rhs = Signal(bw * 3, reset_less=True) + self.trial_compare_rhs = Signal(self.compare_len, reset_less=True) self.operation = DP.create_signal(reset_less=True) def elaborate(self, platform): -- 2.30.2