From 4974fd6bc97344d40ba9c32dcc8d0061551d0f2f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Apr 2015 14:27:31 +0200 Subject: [PATCH] liteusb: pep8 (E302) --- misoclib/com/liteusb/common.py | 4 ++++ misoclib/com/liteusb/core/com.py | 1 + misoclib/com/liteusb/core/crc.py | 7 +++++++ misoclib/com/liteusb/core/depacketizer.py | 3 +++ misoclib/com/liteusb/core/packetizer.py | 6 +++++- misoclib/com/liteusb/frontend/crossbar.py | 1 + misoclib/com/liteusb/frontend/dma.py | 4 +++- misoclib/com/liteusb/frontend/uart.py | 1 + misoclib/com/liteusb/phy/ft2232h.py | 5 +++++ 9 files changed, 30 insertions(+), 2 deletions(-) diff --git a/misoclib/com/liteusb/common.py b/misoclib/com/liteusb/common.py index bb357df1..b27e8318 100644 --- a/misoclib/com/liteusb/common.py +++ b/misoclib/com/liteusb/common.py @@ -16,11 +16,13 @@ phy_layout = [ ("d", 8) ] + class LiteUSBPipe: def __init__(self, layout): self.sink = Sink(layout) self.source = Source(layout) + class LiteUSBTimeout(Module): def __init__(self, clk_freq, length): cnt_max = int(clk_freq*length) @@ -43,9 +45,11 @@ class LiteUSBTimeout(Module): # import random + def randn(max_n): return random.randint(0, max_n-1) + class RandRun: def __init__(self, level=0): self.run = True diff --git a/misoclib/com/liteusb/core/com.py b/misoclib/com/liteusb/core/com.py index 22d8beb5..bf4ec069 100644 --- a/misoclib/com/liteusb/core/com.py +++ b/misoclib/com/liteusb/core/com.py @@ -6,6 +6,7 @@ from misoclib.com.liteusb.frontend.crossbar import LiteUSBCrossbar from misoclib.com.liteusb.core.packetizer import LiteUSBPacketizer from misoclib.com.liteusb.core.depacketizer import LiteUSBDepacketizer + class LiteUSBCom(Module): def __init__(self, phy, *ports): # crossbar diff --git a/misoclib/com/liteusb/core/crc.py b/misoclib/com/liteusb/core/crc.py index 4c60d474..95e9db8c 100644 --- a/misoclib/com/liteusb/core/crc.py +++ b/misoclib/com/liteusb/core/crc.py @@ -8,6 +8,7 @@ from migen.actorlib.fifo import SyncFIFO from misoclib.com.liteusb.common import * + class CRCEngine(Module): """Cyclic Redundancy Check Engine @@ -76,6 +77,7 @@ class CRCEngine(Module): xors += [self.d[n]] self.comb += self.next[i].eq(optree("^", xors)) + @DecorateModule(InsertReset) @DecorateModule(InsertCE) class CRC32(Module): @@ -119,6 +121,7 @@ class CRC32(Module): self.error.eq(self.engine.next != self.check) ] + class CRCInserter(Module): """CRC Inserter @@ -193,10 +196,12 @@ class CRCInserter(Module): ) self.comb += self.busy.eq(~fsm.ongoing("IDLE")) + class CRC32Inserter(CRCInserter): def __init__(self, layout): CRCInserter.__init__(self, CRC32, layout) + class CRCChecker(Module): """CRC Checker @@ -279,10 +284,12 @@ class CRCChecker(Module): ) self.comb += self.busy.eq(~fsm.ongoing("IDLE")) + class CRC32Checker(CRCChecker): def __init__(self, layout): CRCChecker.__init__(self, CRC32, layout) + class LiteUSBCRC32(Module): def __init__(self, tag): self.tag = tag diff --git a/misoclib/com/liteusb/core/depacketizer.py b/misoclib/com/liteusb/core/depacketizer.py index 469f0011..cbc919e8 100644 --- a/misoclib/com/liteusb/core/depacketizer.py +++ b/misoclib/com/liteusb/core/depacketizer.py @@ -4,6 +4,7 @@ from migen.genlib.fsm import FSM, NextState from misoclib.com.liteusb.common import * + class LiteUSBDepacketizer(Module): def __init__(self, timeout=10): self.sink = sink = Sink(phy_layout) @@ -96,6 +97,7 @@ src_data = [ 0x5A, 0xA5, 0x5A, 0xA5, 0x12, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ]*4 + class DepacketizerSourceModel(Module, Source, RandRun): def __init__(self, data): Source.__init__(self, phy_layout) @@ -145,6 +147,7 @@ class TB(Module): self.dut.source.connect(self.sink), ] + def main(): from migen.sim.generic import run_simulation run_simulation(TB(), ncycles=400, vcd_name="tb_depacketizer.vcd") diff --git a/misoclib/com/liteusb/core/packetizer.py b/misoclib/com/liteusb/core/packetizer.py index 7ede9db4..dc4b9fe1 100644 --- a/misoclib/com/liteusb/core/packetizer.py +++ b/misoclib/com/liteusb/core/packetizer.py @@ -4,6 +4,7 @@ from migen.genlib.fsm import FSM, NextState from misoclib.com.liteusb.common import * + class LiteUSBPacketizer(Module): def __init__(self): self.sink = sink = Sink(user_layout) @@ -70,9 +71,10 @@ src_data = [ ), (0x22, 16, [0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF] - ), + ) ] + class PacketizerSourceModel(Module, Source, RandRun): def __init__(self, data): Source.__init__(self, user_layout, True) @@ -116,6 +118,7 @@ class PacketizerSourceModel(Module, Source, RandRun): if self._frame_cnt == len(self.data): raise StopSimulation + class PacketizerSinkModel(Module, Sink, RandRun): def __init__(self): Sink.__init__(self, phy_layout) @@ -140,6 +143,7 @@ class TB(Module): self.dut.source.connect(self.sink), ] + def main(): from migen.sim.generic import run_simulation run_simulation(TB(), ncycles=400, vcd_name="tb_packetizer.vcd") diff --git a/misoclib/com/liteusb/frontend/crossbar.py b/misoclib/com/liteusb/frontend/crossbar.py index e76937a4..85ddefbf 100644 --- a/misoclib/com/liteusb/frontend/crossbar.py +++ b/misoclib/com/liteusb/frontend/crossbar.py @@ -4,6 +4,7 @@ from migen.genlib.record import Record from misoclib.com.liteusb.common import * + class LiteUSBCrossbar(Module): def __init__(self, masters, slave=None): if slave is None: diff --git a/misoclib/com/liteusb/frontend/dma.py b/misoclib/com/liteusb/frontend/dma.py index 4e26004e..7cccccde 100644 --- a/misoclib/com/liteusb/frontend/dma.py +++ b/misoclib/com/liteusb/frontend/dma.py @@ -7,9 +7,9 @@ from migen.bank.eventmanager import * from migen.genlib.record import Record from misoclib.mem.sdram.frontend import dma_lasmi - from misoclib.com.liteusb.common import * + class LiteUSBDMAWriter(Module, AutoCSR): def __init__(self, lasmim): self.sink = sink = Sink(user_layout) @@ -50,6 +50,7 @@ class LiteUSBDMAWriter(Module, AutoCSR): self._crc_failed.status.eq(sink.error) ) + class LiteUSBDMAReader(Module, AutoCSR): def __init__(self, lasmim, tag): self.source = source = Source(user_layout) @@ -89,6 +90,7 @@ class LiteUSBDMAReader(Module, AutoCSR): self.ev.finalize() self.comb += self.ev.done.trigger.eq(source.stb & source.eop) + class LiteUSBDMA(Module, AutoCSR): def __init__(self, lasmim_ftdi_dma_wr, lasmim_ftdi_dma_rd, tag): self.tag = tag diff --git a/misoclib/com/liteusb/frontend/uart.py b/misoclib/com/liteusb/frontend/uart.py index ea56a6b5..a03e67eb 100644 --- a/misoclib/com/liteusb/frontend/uart.py +++ b/misoclib/com/liteusb/frontend/uart.py @@ -5,6 +5,7 @@ from migen.genlib.fifo import SyncFIFOBuffered from misoclib.com.liteusb.common import * + class LiteUSBUART(Module, AutoCSR): def __init__(self, tag, fifo_depth=64): self.tag = tag diff --git a/misoclib/com/liteusb/phy/ft2232h.py b/misoclib/com/liteusb/phy/ft2232h.py index 9f2a0d5a..c4d37b34 100644 --- a/misoclib/com/liteusb/phy/ft2232h.py +++ b/misoclib/com/liteusb/phy/ft2232h.py @@ -5,6 +5,7 @@ from migen.fhdl.specials import * from misoclib.com.liteusb.common import * + class FT2232HPHY(Module): def __init__(self, pads, fifo_depth=32, read_time=16, write_time=16): dw = flen(pads.data) @@ -212,6 +213,7 @@ class FT2232HModel(Module, RandRun): self.wr_sim(selfp) self.rd_sim(selfp) + class UserModel(Module, RandRun): def __init__(self, wr_data): RandRun.__init__(self, 50) @@ -256,6 +258,7 @@ LENGTH = 512 model_rd_data = [i%256 for i in range(LENGTH)][::-1] user_wr_data = [i%256 for i in range(LENGTH)] + class TB(Module): def __init__(self): self.submodules.model = FT2232HModel(model_rd_data) @@ -274,6 +277,7 @@ class TB(Module): ResetSignal("ftdi").eq(ResetSignal()) ] + def print_results(s, l1, l2): def comp(l1, l2): r = True @@ -294,6 +298,7 @@ def print_results(s, l1, l2): r += "[KO]" print(r) + def main(): from migen.sim.generic import run_simulation tb = TB() -- 2.30.2