From 497dbefea2be9150455d9e7e8322c48e4bb98a27 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 5 May 2022 17:18:16 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index b8e13be08..a862bb3b8 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -81,9 +81,12 @@ simplifications that went into the RISC-V ISA have an irrevocably damaging effect on its viability for high performance use. That is not to say that its use in low-performance embedded scenarios is not ideal: in -private custom secretive commercial usage it is perfect. Ubiquitous +private custom secretive commercial usage it is perfect. +Trinamic, an early adopter, created their TMC2660 Stepper IC +replacing ARM with RISC-V and saving themselves USD 1 in licensing +royalties per product are a classic case study. Ubiquitous and common everyday usage in scenarios currently occupied by ARM, Intel, -AMD and IBM? not so much. Thus, even though RISC-V has Cray-style Vectors, +AMD and IBM? not so much. Even though RISC-V has Cray-style Vectors, the whole ISA is, unfortunately, fundamentally flawed as far as power efficient high performance is concerned. -- 2.30.2