From 4988858d7a82daac79d3a9393964494fa43f2d01 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Oct 2018 04:09:43 +0100 Subject: [PATCH] alter operation width based on max bitwidth, and sign/zero-extend --- riscv/sv_insn_redirect.cc | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index 62aaaf9..d98f0d8 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -114,7 +114,7 @@ void (sv_proc_t::WRITE_REG)(reg_spec_t const& spec, sv_reg_t const& value) wval = wval << (shift*bitwidth); // gets element within the reg-block uint64_t ndata = data & (uint64_t)(~mask); // masks off the right bits wval |= ndata; - fprintf(stderr, "writereg %d bitwidth %d offs %d shift %d %lx " \ + fprintf(stderr, "writereg %lx bitwidth %d offs %d shift %d %lx " \ " %lx %lx %lx\n", spec.reg, bitwidth, offs, shift, data, ndata, mask, wval); @@ -151,7 +151,7 @@ reg_t (sv_proc_t::READ_REG)(reg_spec_t const& spec) { ndata = data >> (shift*bitwidth); // gets element within the reg-block ndata &= ((1UL<%lx\n", + fprintf(stderr, "readreg %lx bitwidth %d offs %d shift %d %lx->%lx\n", spec.reg, bitwidth, offs, shift, data, ndata); } return ndata; @@ -342,7 +342,21 @@ sv_reg_t::operator sv_reg_t () sv_reg_t sv_proc_t::rv_add(sv_reg_t const & lhs, sv_reg_t const & rhs) { uint8_t bitwidth = _insn->src_bitwidth; - return lhs + rhs; + if (bitwidth == xlen) { + return lhs + rhs; + } + uint64_t vlhs = 0; + uint64_t vrhs = 0; + // sign-extend or zero-extend to max bitwidth of lhs and rhs? + // has the effect of truncating, as well. + if (_insn->signextended) { // sign-extend? + vlhs = sext_bwid(lhs, bitwidth); + vrhs = sext_bwid(rhs, bitwidth); + } else { // nope: zero-extend. + vlhs = zext_bwid(lhs, bitwidth); + vrhs = zext_bwid(rhs, bitwidth); + } + return sv_reg_t(vlhs + vrhs, xlen); // XXX TODO: bitwidth } sv_reg_t sv_proc_t::rv_sub(sv_reg_t const & lhs, sv_reg_t const & rhs) -- 2.30.2