From 49974b6c4e61fbd9b50e7937d848de44f2d232c0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 19 Jun 2019 16:06:51 +0100 Subject: [PATCH] add SV VLIW idea --- simple_v_extension/specification.mdwn | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 2004f5aaa..a06e5fc49 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -2230,10 +2230,10 @@ Optional VL/MAXVL/SubVL Block: Reminder of the variable-length format from Section 1.5 of the RISC-V ISA: -^ base+4 ^ base+2 ^ base ^ number of bits ^ -| ------ | ---------------- | ---------------- | -------------------------- | -| ..xxxx | xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 | -| {ops}{Pred}{Reg}{VL} || SV Prefix | | +| base+4 .. base+2 | base | number of bits | +| ------------------------- | ---------------- | -------------------------- | +| ..xxxx xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 | +| {ops}{Pred}{Reg}{VL} | SV Prefix | | Notes: -- 2.30.2