From 49bd1d27292b2e0dc0269a4eda3404b3b4e92a4d Mon Sep 17 00:00:00 2001 From: Stan Shebs Date: Mon, 16 Aug 2004 18:57:27 +0000 Subject: [PATCH] Basic support for 64-bit Darwin. * config/darwin.c (macho_indirect_data_reference): Add DImode case. (machopic_legitimize_pic_address): Similarly, plus use Pmode instead of SImode. * config/rs6000/darwin.h (PTRDIFF_TYPE): Be "long int" if 64-bit. (TARGET_OS_CPP_BUILTINS): Add 64-bit preprocessor macro. (SUBTARGET_SWITCHES): Add -m32 and -m64 flags. (SUBTARGET_OVERRIDE_OPTIONS): Require 64-bit processor if -m64. (PROCESSOR_DEFAULT64): Define. * config/rs6000/darwin.md: New file, patterns specific to 64-bit Darwin. * config/rs6000/rs6000.md: Include darwin.md. (builtin_setjmp_receiver): Add DImode case. * config/rs6000/rs6000.c (TARGET_ASM_UNALIGNED_DI_OP): Define for Darwin. (TARGET_ASM_ALIGNED_DI_OP): Ditto. (rs6000_emit_move): Add DImode case to Darwin bits. (machopic_output_stub): Use .quad if 64-bit. * invoke.texi: Document -m32 and -m64. From-SVN: r86070 --- gcc/ChangeLog | 22 ++ gcc/config/darwin.c | 16 +- gcc/config/rs6000/darwin.h | 20 +- gcc/config/rs6000/darwin.md | 392 ++++++++++++++++++++++++++++++++++++ gcc/config/rs6000/rs6000.c | 19 +- gcc/config/rs6000/rs6000.md | 9 +- gcc/doc/invoke.texi | 11 + 7 files changed, 477 insertions(+), 12 deletions(-) create mode 100644 gcc/config/rs6000/darwin.md diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cfe11f1b86d..8b8d90ba7fe 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,25 @@ +2004-08-16 Stan Shebs + + Basic support for 64-bit Darwin. + * config/darwin.c (macho_indirect_data_reference): Add DImode case. + (machopic_legitimize_pic_address): Similarly, plus use Pmode + instead of SImode. + * config/rs6000/darwin.h (PTRDIFF_TYPE): Be "long int" if 64-bit. + (TARGET_OS_CPP_BUILTINS): Add 64-bit preprocessor macro. + (SUBTARGET_SWITCHES): Add -m32 and -m64 flags. + (SUBTARGET_OVERRIDE_OPTIONS): Require 64-bit processor if -m64. + (PROCESSOR_DEFAULT64): Define. + * config/rs6000/darwin.md: New file, patterns specific to 64-bit + Darwin. + * config/rs6000/rs6000.md: Include darwin.md. + (builtin_setjmp_receiver): Add DImode case. + * config/rs6000/rs6000.c (TARGET_ASM_UNALIGNED_DI_OP): Define for + Darwin. + (TARGET_ASM_ALIGNED_DI_OP): Ditto. + (rs6000_emit_move): Add DImode case to Darwin bits. + (machopic_output_stub): Use .quad if 64-bit. + * invoke.texi: Document -m32 and -m64. + 2004-08-16 Janis Johnson * doc/extend.texi (AltiVec builtins): Document additional differences diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c index 111abfc465a..9f47dc4607c 100644 --- a/gcc/config/darwin.c +++ b/gcc/config/darwin.c @@ -333,8 +333,12 @@ machopic_indirect_data_reference (rtx orig, rtx reg) if (defined && MACHO_DYNAMIC_NO_PIC_P) { #if defined (TARGET_TOC) - emit_insn (gen_macho_high (reg, orig)); - emit_insn (gen_macho_low (reg, reg, orig)); + emit_insn (GET_MODE (orig) == DImode + ? gen_macho_high_di (reg, orig) + : gen_macho_high (reg, orig)); + emit_insn (GET_MODE (orig) == DImode + ? gen_macho_low_di (reg, reg, orig) + : gen_macho_low (reg, reg, orig)); #else /* some other cpu -- writeme! */ abort (); @@ -529,7 +533,9 @@ machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) rtx asym = XEXP (orig, 0); rtx mem; - emit_insn (gen_macho_high (temp_reg, asym)); + emit_insn (mode == DImode + ? gen_macho_high_di (temp_reg, asym) + : gen_macho_high (temp_reg, asym)); mem = gen_rtx_MEM (GET_MODE (orig), gen_rtx_LO_SUM (Pmode, temp_reg, asym)); RTX_UNCHANGING_P (mem) = 1; @@ -551,7 +557,7 @@ machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) #if defined (TARGET_TOC) /* i.e., PowerPC */ /* Generating a new reg may expose opportunities for common subexpression elimination. */ - rtx hi_sum_reg = no_new_pseudos ? reg : gen_reg_rtx (SImode); + rtx hi_sum_reg = no_new_pseudos ? reg : gen_reg_rtx (Pmode); rtx mem; rtx insn; rtx sum; @@ -634,7 +640,7 @@ machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) if (reload_in_progress) abort (); else - reg = gen_reg_rtx (SImode); + reg = gen_reg_rtx (Pmode); } hi_sum_reg = reg; diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index 1f891ac561e..1f1924fe5b4 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -35,6 +35,10 @@ #define TARGET_TOC 0 #define TARGET_NO_TOC 1 +/* Override the default rs6000 definition. */ +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE (TARGET_64BIT ? "long int" : "int") + /* Darwin switches. */ /* Use dynamic-no-pic codegen (no picbase reg; not suitable for shlibs.) */ #define MASK_MACHO_DYNAMIC_NO_PIC 0x00800000 @@ -48,7 +52,8 @@ #define TARGET_OS_CPP_BUILTINS() \ do \ { \ - builtin_define ("__ppc__"); \ + if (!TARGET_64BIT) builtin_define ("__ppc__"); \ + if (TARGET_64BIT) builtin_define ("__ppc64__"); \ builtin_define ("__POWERPC__"); \ builtin_define ("__NATURAL_ALIGNMENT__"); \ builtin_define ("__MACH__"); \ @@ -60,6 +65,10 @@ /* */ #undef SUBTARGET_SWITCHES #define SUBTARGET_SWITCHES \ + { "64", MASK_64BIT | MASK_POWERPC64, \ + N_("Generate 64-bit code") }, \ + { "32", - (MASK_64BIT | MASK_POWERPC64), \ + N_("Generate 32-bit code") }, \ {"dynamic-no-pic", MASK_MACHO_DYNAMIC_NO_PIC, \ N_("Generate code suitable for executables (NOT shared libs)")}, \ {"no-dynamic-no-pic", -MASK_MACHO_DYNAMIC_NO_PIC, ""}, @@ -87,6 +96,11 @@ do { \ flag_pic = 2; \ } \ } \ + if (TARGET_64BIT && ! TARGET_POWERPC64) \ + { \ + target_flags |= MASK_POWERPC64; \ + warning ("-m64 requires PowerPC64 architecture, enabling"); \ + } \ } while(0) /* Darwin has 128-bit long double support in libc in 10.4 and later. @@ -252,10 +266,12 @@ do { \ #define RS6000_MCOUNT "*mcount" -/* Default processor: a G4. */ +/* Default processor: G4, and G5 for 64-bit. */ #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_PPC7400 +#undef PROCESSOR_DEFAULT64 +#define PROCESSOR_DEFAULT64 PROCESSOR_POWER4 /* Default target flag settings. Despite the fact that STMW/LMW serializes, it's still a big code size win to use them. Use FSEL by diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md new file mode 100644 index 00000000000..12dcf24ace2 --- /dev/null +++ b/gcc/config/rs6000/darwin.md @@ -0,0 +1,392 @@ +/* Machine description patterns for PowerPC running Darwin (Mac OS X). + Copyright (C) 2004 Free Software Foundation, Inc. + Contributed by Apple Computer Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +(define_insn "adddi3_high" + [(set (match_operand:DI 0 "gpc_reg_operand" "=b") + (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b") + (high:DI (match_operand 2 "" ""))))] + "TARGET_MACHO && TARGET_64BIT" + "{cau|addis} %0,%1,ha16(%2)" + [(set_attr "length" "4")]) + +(define_insn "movdf_low_di" + [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") + (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") + (match_operand 2 "" ""))))] + "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT" + "* +{ + switch (which_alternative) + { + case 0: + return \"lfd %0,lo16(%2)(%1)\"; + case 1: + { + rtx operands2[4]; + operands2[0] = operands[0]; + operands2[1] = operands[1]; + operands2[2] = operands[2]; + if (TARGET_POWERPC64 && TARGET_32BIT) + /* Note, old assemblers didn't support relocation here. */ + return \"ld %0,lo16(%2)(%1)\"; + else + { + operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM); + output_asm_insn (\"{l|ld} %0,lo16(%2)(%1)\", operands); +#if TARGET_MACHO + if (MACHO_DYNAMIC_NO_PIC_P) + output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands); + else + /* We cannot rely on ha16(low half)==ha16(high half), alas, + although in practice it almost always is. */ + output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2); +#endif + return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\"); + } + } + default: + abort(); + } +}" + [(set_attr "type" "load") + (set_attr "length" "4,12")]) + +(define_insn "movdf_low_st_di" + [(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") + (match_operand 2 "" ""))) + (match_operand:DF 0 "gpc_reg_operand" "f"))] + "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT" + "stfd %0,lo16(%2)(%1)" + [(set_attr "type" "store") + (set_attr "length" "4")]) + +(define_insn "movsf_low_di" + [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") + (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") + (match_operand 2 "" ""))))] + "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT" + "@ + lfs %0,lo16(%2)(%1) + {l|ld} %0,lo16(%2)(%1)" + [(set_attr "type" "load") + (set_attr "length" "4")]) + +(define_insn "movsf_low_st_di" + [(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") + (match_operand 2 "" ""))) + (match_operand:SF 0 "gpc_reg_operand" "f,!r"))] + "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT" + "@ + stfs %0,lo16(%2)(%1) + {st|stw} %0,lo16(%2)(%1)" + [(set_attr "type" "store") + (set_attr "length" "4")]) + +;; 64-bit MachO load/store support +(define_insn "movdi_low" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") + (match_operand 2 "" ""))))] + "TARGET_MACHO && TARGET_64BIT" + "{l|ld} %0,lo16(%2)(%1)" + [(set_attr "type" "load") + (set_attr "length" "4")]) + +(define_insn "movdi_low_st" + [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") + (match_operand 2 "" ""))) + (match_operand:DI 0 "gpc_reg_operand" "r"))] + "TARGET_MACHO && TARGET_64BIT" + "{st|std} %0,lo16(%2)(%1)" + [(set_attr "type" "store") + (set_attr "length" "4")]) + +(define_insn "macho_high_di" + [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r") + (high:DI (match_operand 1 "" "")))] + "TARGET_MACHO && TARGET_64BIT" + "{liu|lis} %0,ha16(%1)") + +(define_insn "macho_low_di" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r") + (match_operand 2 "" "")))] + "TARGET_MACHO && TARGET_64BIT" + "@ + {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} + {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") + +(define_split + [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "") + (match_operand:DI 1 "short_cint_operand" ""))) + (match_operand:V4SI 2 "register_operand" "")) + (clobber (match_operand:DI 3 "gpc_reg_operand" ""))] + "TARGET_MACHO && TARGET_64BIT" + [(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1))) + (set (mem:V4SI (match_dup 3)) + (match_dup 2))] + "") + +(define_insn "" + [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "b,r") + (match_operand:DI 1 "gpc_reg_operand" "r,b"))) + (match_operand:V4SI 2 "register_operand" "v,v"))] + "TARGET_MACHO && TARGET_64BIT" + "@ + stvx %2,%0,%1 + stvx %2,%1,%0" + [(set_attr "type" "vecstore")]) + +(define_insn "" + [(set (mem:V4SI (match_operand:DI 0 "gpc_reg_operand" "r")) + (match_operand:V4SI 1 "register_operand" "v"))] + "TARGET_MACHO && TARGET_64BIT" + "stvx %1,0,%0" + [(set_attr "type" "vecstore")]) + +(define_split + [(set (match_operand:V4SI 0 "register_operand" "") + (mem:V4SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") + (match_operand:DI 2 "short_cint_operand" "")))) + (clobber (match_operand:DI 3 "gpc_reg_operand" ""))] + "TARGET_MACHO && TARGET_64BIT" + [(set (match_dup 3) (plus:DI (match_dup 1) (match_dup 2))) + (set (match_dup 0) + (mem:V4SI (match_dup 3)))] + "") + +(define_insn "" + [(set (match_operand:V4SI 0 "register_operand" "=v,v") + (mem:V4SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b,r") + (match_operand:DI 2 "gpc_reg_operand" "r,b"))))] + "TARGET_MACHO && TARGET_64BIT" + "@ + lvx %0,%1,%2 + lvx %0,%2,%1" + [(set_attr "type" "vecload")]) + +(define_insn "" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (mem:V4SI (match_operand:DI 1 "gpc_reg_operand" "r")))] + "TARGET_MACHO && TARGET_64BIT" + "lvx %0,0,%1" + [(set_attr "type" "vecload")]) + +(define_insn "load_macho_picbase_di" + [(set (match_operand:DI 0 "register_operand" "=l") + (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")] 15))] + "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" + "bcl 20,31,%1\\n%1:" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + +(define_insn "macho_correct_pic_di" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (plus:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (unspec:DI [(match_operand:DI 2 "immediate_operand" "s") + (match_operand:DI 3 "immediate_operand" "s")] + 16)))] + "DEFAULT_ABI == ABI_DARWIN" + "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)" + [(set_attr "length" "8")]) + +(define_insn "*call_indirect_nonlocal_darwin64" + [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l,c,*l")) + (match_operand 1 "" "g,g,g,g")) + (use (match_operand:SI 2 "immediate_operand" "O,O,n,n")) + (clobber (match_scratch:SI 3 "=l,l,l,l"))] + "DEFAULT_ABI == ABI_DARWIN" +{ + return "b%T0l"; +} + [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg") + (set_attr "length" "4,4,8,8")]) + +(define_insn "*call_nonlocal_darwin64" + [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s")) + (match_operand 1 "" "g,g")) + (use (match_operand:SI 2 "immediate_operand" "O,n")) + (clobber (match_scratch:SI 3 "=l,l"))] + "(DEFAULT_ABI == ABI_DARWIN) + && (INTVAL (operands[2]) & CALL_LONG) == 0" +{ +#if TARGET_MACHO + return output_call(insn, operands, 0, 2); +#endif +} + [(set_attr "type" "branch,branch") + (set_attr "length" "4,8")]) + +(define_insn "*call_value_indirect_nonlocal_darwin64" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l,c,*l")) + (match_operand 2 "" "g,g,g,g"))) + (use (match_operand:SI 3 "immediate_operand" "O,O,n,n")) + (clobber (match_scratch:SI 4 "=l,l,l,l"))] + "DEFAULT_ABI == ABI_DARWIN" +{ + return "b%T1l"; +} + [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg") + (set_attr "length" "4,4,8,8")]) + +(define_insn "*call_value_nonlocal_darwin64" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s")) + (match_operand 2 "" "g,g"))) + (use (match_operand:SI 3 "immediate_operand" "O,n")) + (clobber (match_scratch:SI 4 "=l,l"))] + "(DEFAULT_ABI == ABI_DARWIN) + && (INTVAL (operands[3]) & CALL_LONG) == 0" +{ +#if TARGET_MACHO + return output_call(insn, operands, 1, 3); +#endif +} + [(set_attr "type" "branch,branch") + (set_attr "length" "4,8")]) + +(define_insn "*sibcall_nonlocal_darwin64" + [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s")) + (match_operand 1 "" "")) + (use (match_operand 2 "immediate_operand" "O,n")) + (use (match_operand:SI 3 "register_operand" "l,l")) + (return)] + "(DEFAULT_ABI == ABI_DARWIN) + && (INTVAL (operands[2]) & CALL_LONG) == 0" +{ + return "b %z0"; +} + [(set_attr "type" "branch,branch") + (set_attr "length" "4,8")]) + +(define_insn "*sibcall_value_nonlocal_darwin64" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s")) + (match_operand 2 "" ""))) + (use (match_operand:SI 3 "immediate_operand" "O,n")) + (use (match_operand:SI 4 "register_operand" "l,l")) + (return)] + "(DEFAULT_ABI == ABI_DARWIN) + && (INTVAL (operands[3]) & CALL_LONG) == 0" + "* +{ + return \"b %z1\"; +}" + [(set_attr "type" "branch,branch") + (set_attr "length" "4,8")]) + + +(define_insn "*sibcall_symbolic_64" + [(call (mem:SI (match_operand:DI 0 "call_operand" "s,c")) ; 64 + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (use (match_operand:SI 3 "register_operand" "l,l")) + (return)] + "TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN" + "* +{ + switch (which_alternative) + { + case 0: return \"b %z0\"; + case 1: return \"b%T0\"; + default: abort(); + } +}" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + +(define_insn "*sibcall_value_symbolic_64" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:DI 1 "call_operand" "s,c")) + (match_operand 2 "" ""))) + (use (match_operand:SI 3 "" "")) + (use (match_operand:SI 4 "register_operand" "l,l")) + (return)] + "TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN" + "* +{ + switch (which_alternative) + { + case 0: return \"b %z1\"; + case 1: return \"b%T1\"; + default: abort(); + } +}" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + +(define_insn "*save_fpregs_with_label_di" + [(match_parallel 0 "any_operand" + [(clobber (match_operand:DI 1 "register_operand" "=l")) + (use (match_operand:DI 2 "call_operand" "s")) + (use (match_operand:DI 3 "" "")) + (set (match_operand:DF 4 "memory_operand" "=m") + (match_operand:DF 5 "gpc_reg_operand" "f"))])] + "TARGET_64BIT" + "* +#if TARGET_MACHO + const char *picbase = machopic_function_base_name (); + operands[3] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1)); +#endif + return \"bl %z2\\n%3:\"; +" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + +(define_insn "*save_vregs_di" + [(match_parallel 0 "any_operand" + [(clobber (match_operand:DI 1 "register_operand" "=l")) + (use (match_operand:DI 2 "call_operand" "s")) + (set (match_operand:V4SI 3 "any_operand" "=m") + (match_operand:V4SI 4 "register_operand" "v"))])] + "TARGET_64BIT" + "bl %z2" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + +(define_insn "*restore_vregs_di" + [(match_parallel 0 "any_operand" + [(clobber (match_operand:DI 1 "register_operand" "=l")) + (use (match_operand:DI 2 "call_operand" "s")) + (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) + (set (match_operand:V4SI 4 "register_operand" "=v") + (match_operand:V4SI 5 "any_operand" "m"))])] + "TARGET_64BIT" + "bl %z2") + +(define_insn "*save_vregs_with_label_di" + [(match_parallel 0 "any_operand" + [(clobber (match_operand:DI 1 "register_operand" "=l")) + (use (match_operand:DI 2 "call_operand" "s")) + (use (match_operand:DI 3 "" "")) + (set (match_operand:V4SI 4 "any_operand" "=m") + (match_operand:V4SI 5 "register_operand" "v"))])] + "TARGET_64BIT" + "* +#if TARGET_MACHO + const char *picbase = machopic_function_base_name (); + operands[3] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1)); +#endif + return \"bl %z2\\n%3:\"; +" + [(set_attr "type" "branch") + (set_attr "length" "4")]) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 3331af07083..fc63c315f8b 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -851,6 +851,10 @@ static const char alt_reg_names[][8] = #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" #undef TARGET_ASM_UNALIGNED_SI_OP #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" +#undef TARGET_ASM_UNALIGNED_DI_OP +#define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t" +#undef TARGET_ASM_ALIGNED_DI_OP +#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" #endif #endif @@ -4310,8 +4314,16 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) return; } #endif - emit_insn (gen_macho_high (target, operands[1])); - emit_insn (gen_macho_low (operands[0], target, operands[1])); + if (mode == DImode) + { + emit_insn (gen_macho_high_di (target, operands[1])); + emit_insn (gen_macho_low_di (operands[0], target, operands[1])); + } + else + { + emit_insn (gen_macho_high (target, operands[1])); + emit_insn (gen_macho_low (operands[0], target, operands[1])); + } return; } @@ -16208,7 +16220,8 @@ machopic_output_stub (FILE *file, const char *symb, const char *stub) machopic_lazy_symbol_ptr_section (); fprintf (file, "%s:\n", lazy_ptr_name); fprintf (file, "\t.indirect_symbol %s\n", symbol_name); - fprintf (file, "\t.long dyld_stub_binding_helper\n"); + fprintf (file, "%sdyld_stub_binding_helper\n", + (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t")); } /* Legitimize PIC addresses. If the address is already diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 198291e22b4..149adf7e0e7 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -101,6 +101,7 @@ (include "8540.md") (include "power4.md") (include "power5.md") +(include "darwin.md") ;; Start with fixed-point load and store insns. Here we put only the more @@ -10158,8 +10159,12 @@ CODE_LABEL_NUMBER (operands[0])); tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); - emit_insn (gen_load_macho_picbase (picreg, tmplabrtx)); - emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); + emit_insn (TARGET_64BIT + ? gen_load_macho_picbase_di (picreg, tmplabrtx) + : gen_load_macho_picbase (picreg, tmplabrtx)); + emit_insn (TARGET_64BIT + ? gen_macho_correct_pic_di (picreg, picreg, picrtx, tmplabrtx) + : gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); } else #endif diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 0cc00780498..98b66e29385 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -9974,6 +9974,17 @@ This switch enables or disables the generation of floating point operations on the general purpose registers for architectures that support it. This option is currently only available on the MPC8540. +@item -m32 +@itemx -m64 +@opindex m32 +@opindex m64 +Generate code for 32-bit or 64-bit environments of Darwin and SVR4 +targets (including GNU/Linux). The 32-bit environment sets int, long +and pointer to 32 bits and generates code that runs on any PowerPC +variant. The 64-bit environment sets int to 32 bits and long and +pointer to 64 bits, and generates code for PowerPC64, as for +@option{-mpowerpc64}. + @item -mfull-toc @itemx -mno-fp-in-toc @itemx -mno-sum-in-toc -- 2.30.2