From 49bf0a79fa16d2d524e3d1501858a42166ee6d61 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 8 Oct 2020 21:19:07 -0700 Subject: [PATCH] finish converting mul tests to use common code --- src/soc/fu/mul/test/helper.py | 21 +- src/soc/fu/mul/test/test_pipe_caller.py | 20 +- src/soc/fu/mul/test/test_pipe_caller_long.py | 370 ++++++++----------- 3 files changed, 160 insertions(+), 251 deletions(-) diff --git a/src/soc/fu/mul/test/helper.py b/src/soc/fu/mul/test/helper.py index b32e2dc6..a0099318 100644 --- a/src/soc/fu/mul/test/helper.py +++ b/src/soc/fu/mul/test/helper.py @@ -24,15 +24,14 @@ from soc.fu.mul.pipe_data import MulPipeSpec import random -def get_cu_inputs(dec2, sim, has_third_input): +def get_cu_inputs(dec2, sim): """naming (res) must conform to MulFunctionUnit input regspec """ res = {} yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB - if has_third_input: - yield from ALUHelpers.get_sim_int_rc(res, sim, dec2) # RC + yield from ALUHelpers.get_sim_int_rc(res, sim, dec2) # RC yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so print("alu get_cu_inputs", res) @@ -45,7 +44,7 @@ def set_alu_inputs(alu, dec2, sim, has_third_input): # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) # and place it into data_i.b - inp = yield from get_cu_inputs(dec2, sim, has_third_input) + inp = yield from get_cu_inputs(dec2, sim) print("set alu inputs", inp) yield from ALUHelpers.set_int_ra(alu, dec2, inp) yield from ALUHelpers.set_int_rb(alu, dec2, inp) @@ -60,8 +59,8 @@ def set_alu_inputs(alu, dec2, sim, has_third_input): overflow = pia.OverflowFlags(so=bool(so), ov=False, ov32=False) - rc = inp["rb"] if has_third_input else None - return pia.InstructionInput(ra=inp["ra"], rb=inp["rb"], + rc = inp["rc"] if has_third_input else None + return pia.InstructionInput(ra=inp.get("ra"), rb=inp.get("rb"), rc=rc, overflow=overflow) @@ -104,7 +103,15 @@ class MulTestHelper(unittest.TestCase): opname = code.split(' ')[0] fnname = opname.replace(".", "_") print(f"{fnname}({pia_inputs})") - pia_res = getattr(pia, opname.replace(".", "_"))(pia_inputs) + pia_res = None + try: + pia_res = getattr(pia, fnname)(pia_inputs) + except AttributeError: + EXPECTED_FAILURES = ["mulli"] + if fnname not in EXPECTED_FAILURES: + raise + else: + print("not implemented, as expected.") print(f"-> {pia_res}") yield from isa_sim.call(opname) diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py index ce015d0e..2fb8265c 100644 --- a/src/soc/fu/mul/test/test_pipe_caller.py +++ b/src/soc/fu/mul/test/test_pipe_caller.py @@ -1,24 +1,8 @@ -from nmigen import Module, Signal - -# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell -# Also, check out the cxxsim nmigen branch, and latest yosys from git -from nmutil.sim_tmp_alternative import Simulator, Delay, Settle - -from nmigen.cli import rtlil import unittest -from soc.decoder.isa.caller import ISACaller, special_sprs -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) -from soc.decoder.selectable_int import SelectableInt +from soc.fu.mul.test.helper import MulTestHelper from soc.simulator.program import Program -from soc.decoder.isa.all import ISA from soc.config.endian import bigendian - -from soc.fu.test.common import (TestAccumulatorBase, TestCase, ALUHelpers) -from soc.fu.mul.pipeline import MulBasePipe -from soc.fu.mul.pipe_data import MulPipeSpec -from soc.fu.mul.test.helper import MulTestHelper +from soc.fu.test.common import (TestAccumulatorBase) import random diff --git a/src/soc/fu/mul/test/test_pipe_caller_long.py b/src/soc/fu/mul/test/test_pipe_caller_long.py index d62f1a72..d1363612 100644 --- a/src/soc/fu/mul/test/test_pipe_caller_long.py +++ b/src/soc/fu/mul/test/test_pipe_caller_long.py @@ -1,70 +1,12 @@ -from nmigen import Module, Signal -from nmigen.sim.pysim import Simulator, Delay, Settle -from nmigen.cli import rtlil import unittest -from soc.decoder.isa.caller import ISACaller, special_sprs -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) -from soc.decoder.selectable_int import SelectableInt +from soc.fu.mul.test.helper import MulTestHelper from soc.simulator.program import Program -from soc.decoder.isa.all import ISA from soc.config.endian import bigendian - -from soc.fu.test.common import (TestAccumulatorBase, TestCase, ALUHelpers) -from soc.fu.mul.pipeline import MulBasePipe -from soc.fu.mul.pipe_data import MulPipeSpec +from soc.fu.test.common import (TestAccumulatorBase) import random -def get_cu_inputs(dec2, sim): - """naming (res) must conform to MulFunctionUnit input regspec - """ - res = {} - - yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA - yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB - yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so - - print("alu get_cu_inputs", res) - - return res - - -def set_alu_inputs(alu, dec2, sim): - # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 - # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) - # and place it into data_i.b - - inp = yield from get_cu_inputs(dec2, sim) - print("set alu inputs", inp) - yield from ALUHelpers.set_int_ra(alu, dec2, inp) - yield from ALUHelpers.set_int_rb(alu, dec2, inp) - - yield from ALUHelpers.set_xer_so(alu, dec2, inp) - - -# This test bench is a bit different than is usual. Initially when I -# was writing it, I had all of the tests call a function to create a -# device under test and simulator, initialize the dut, run the -# simulation for ~2 cycles, and assert that the dut output what it -# should have. However, this was really slow, since it needed to -# create and tear down the dut and simulator for every test case. - -# Now, instead of doing that, every test case in MulTestCase puts some -# data into the test_data list below, describing the instructions to -# be tested and the initial state. Once all the tests have been run, -# test_data gets passed to TestRunner which then sets up the DUT and -# simulator once, runs all the data through it, and asserts that the -# results match the pseudocode sim at every cycle. - -# By doing this, I've reduced the time it takes to run the test suite -# massively. Before, it took around 1 minute on my computer, now it -# takes around 3 seconds - - -class MulTestCase(TestAccumulatorBase): - +class MulTestCases2Arg(TestAccumulatorBase): def case_all(self): instrs = ["mulhw", "mulhw.", "mullw", @@ -97,13 +39,13 @@ class MulTestCase(TestAccumulatorBase): for instr in instrs: l = [f"{instr} 3, 1, 2"] - for ra in test_values: - for rb in test_values: - initial_regs = [0] * 32 - initial_regs[1] = ra - initial_regs[2] = rb - # use "with" so as to close the files used - with Program(l, bigendian) as prog: + # use "with" so as to close the files used + with Program(l, bigendian) as prog: + for ra in test_values: + for rb in test_values: + initial_regs = [0] * 32 + initial_regs[1] = ra + initial_regs[2] = rb self.add_case(prog, initial_regs) def case_all_rb_randint(self): @@ -138,12 +80,12 @@ class MulTestCase(TestAccumulatorBase): for instr in instrs: l = [f"{instr} 3, 1, 2"] - for ra in test_values: - initial_regs = [0] * 32 - initial_regs[1] = ra - initial_regs[2] = random.randint(0, (1 << 64)-1) - # use "with" so as to close the files used - with Program(l, bigendian) as prog: + # use "with" so as to close the files used + with Program(l, bigendian) as prog: + for ra in test_values: + initial_regs = [0] * 32 + initial_regs[1] = ra + initial_regs[2] = random.randint(0, (1 << 64)-1) self.add_case(prog, initial_regs) def case_all_rb_close_to_ov(self): @@ -177,17 +119,17 @@ class MulTestCase(TestAccumulatorBase): ] for instr in instrs: - for i in range(20): - x = 0x7fffffff + random.randint((-1 << 31), (1 << 31) - 1) - ra = random.randint(0, (1 << 32)-1) - rb = x // ra - - l = [f"{instr} 3, 1, 2"] - initial_regs = [0] * 32 - initial_regs[1] = ra - initial_regs[2] = rb - # use "with" so as to close the files used - with Program(l, bigendian) as prog: + l = [f"{instr} 3, 1, 2"] + # use "with" so as to close the files used + with Program(l, bigendian) as prog: + for i in range(20): + x = 0x7fffffff + random.randint((-1 << 31), (1 << 31) - 1) + ra = random.randint(0, (1 << 32)-1) + rb = x // ra + + initial_regs = [0] * 32 + initial_regs[1] = ra + initial_regs[2] = rb self.add_case(prog, initial_regs) def case_mulli(self): @@ -219,149 +161,125 @@ class MulTestCase(TestAccumulatorBase): for i in range(14): ra_values.append(random.randint(0, (1 << 64) - 1)) - for ra in ra_values: - for imm in imm_values: - l = [f"mulli 0, 1, {imm}"] - initial_regs = [0] * 32 - initial_regs[1] = ra - # use "with" so as to close the files used - with Program(l, bigendian) as prog: + for imm in imm_values: + l = [f"mulli 0, 1, {imm}"] + # use "with" so as to close the files used + with Program(l, bigendian) as prog: + for ra in ra_values: + initial_regs = [0] * 32 + initial_regs[1] = ra self.add_case(prog, initial_regs) -# TODO add test case for these 3 operand cases (madd -# needs to be implemented) -# "maddhd","maddhdu","maddld" - - def case_ilang(self): - pspec = MulPipeSpec(id_wid=2) - alu = MulBasePipe(pspec) - vl = rtlil.convert(alu, ports=alu.ports()) - with open("mul_pipeline.il", "w") as f: - f.write(vl) - - -class TestRunner(unittest.TestCase): - def __init__(self, test_data): - super().__init__("run_all") - self.test_data = test_data - - def run_all(self): - m = Module() - comb = m.d.comb - instruction = Signal(32) - - pdecode = create_pdecode() - - m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) - - pspec = MulPipeSpec(id_wid=2) - m.submodules.alu = alu = MulBasePipe(pspec) - - comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do) - comb += alu.n.ready_i.eq(1) - comb += pdecode2.dec.raw_opcode_in.eq(instruction) - sim = Simulator(m) - - sim.add_clock(1e-6) - - def process(): - for test in self.test_data: - print(test.name) - program = test.program - self.subTest(test.name) - sim = ISA(pdecode2, test.regs, test.sprs, test.cr, - test.mem, test.msr, - bigendian=bigendian) - gen = program.generate_instructions() - instructions = list(zip(gen, program.assembly.splitlines())) - yield Settle() - - index = sim.pc.CIA.value//4 - while index < len(instructions): - ins, code = instructions[index] - - print("instruction: 0x{:X}".format(ins & 0xffffffff)) - print(code) - if 'XER' in sim.spr: - so = 1 if sim.spr['XER'][XER_bits['SO']] else 0 - ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0 - ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0 - print("before: so/ov/32", so, ov, ov32) - - # ask the decoder to decode this binary data (endian'd) - yield pdecode2.dec.bigendian.eq(bigendian) # little / big? - yield instruction.eq(ins) # raw binary instr. - yield Settle() - fn_unit = yield pdecode2.e.do.fn_unit - self.assertEqual(fn_unit, Function.MUL.value) - yield from set_alu_inputs(alu, pdecode2, sim) - - # set valid for one cycle, propagate through pipeline... - yield alu.p.valid_i.eq(1) - yield - yield alu.p.valid_i.eq(0) - - opname = code.split(' ')[0] - yield from sim.call(opname) - index = sim.pc.CIA.value//4 - - # ...wait for valid to pop out the end - vld = yield alu.n.valid_o - while not vld: - yield - vld = yield alu.n.valid_o - yield - - yield from self.check_alu_outputs(alu, pdecode2, sim, code) - yield Settle() - - sim.add_sync_process(process) - with sim.write_vcd("mul_simulator.vcd", "mul_simulator.gtkw", - traces=[]): - sim.run() - - def check_alu_outputs(self, alu, dec2, sim, code): - - rc = yield dec2.e.do.rc.data - cridx_ok = yield dec2.e.write_cr.ok - cridx = yield dec2.e.write_cr.data - - print("check extra output", repr(code), cridx_ok, cridx) - if rc: - self.assertEqual(cridx, 0, code) - - oe = yield dec2.e.do.oe.oe - oe_ok = yield dec2.e.do.oe.ok - if not oe or not oe_ok: - # if OE not enabled, XER SO and OV must correspondingly be false - so_ok = yield alu.n.data_o.xer_so.ok - ov_ok = yield alu.n.data_o.xer_ov.ok - self.assertEqual(so_ok, False, code) - self.assertEqual(ov_ok, False, code) - - sim_o = {} - res = {} - - yield from ALUHelpers.get_cr_a(res, alu, dec2) - yield from ALUHelpers.get_xer_ov(res, alu, dec2) - yield from ALUHelpers.get_int_o(res, alu, dec2) - yield from ALUHelpers.get_xer_so(res, alu, dec2) - - yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) - yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2) - - ALUHelpers.check_int_o(self, res, sim_o, code) - ALUHelpers.check_xer_ov(self, res, sim_o, code) - ALUHelpers.check_xer_so(self, res, sim_o, code) - ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) +MUL_3_ARG_TEST_VALUES = [ + 0x0, + 0x1, + 0x2, + 0xFFFF_FFFF_FFFF_FFFF, + 0xFFFF_FFFF_FFFF_FFFE, + 0x7FFF_FFFF_FFFF_FFFF, + 0x8000_0000_0000_0000, + 0x1234_5678_0000_0000, + 0x1234_5678_8000_0000, + 0x1234_5678_FFFF_FFFF, + 0x1234_5678_7FFF_FFFF, + 0xffffffff, + 0x7fffffff, + 0x80000000, + 0xfffffffe, + 0xfffffffd +] + + +class MulTestCases3Arg(TestAccumulatorBase): + def __init__(self, subtest_index): + self.subtest_index = subtest_index + super().__init__() -if __name__ == "__main__": - unittest.main(exit=False) - suite = unittest.TestSuite() - suite.addTest(TestRunner(MulTestCase().test_data)) + def case_all(self): + instrs = ["maddhd", "maddhdu", "maddld"] + + for instr in instrs: + l = [f"{instr} 1, 2, 3, 4"] + ra = MUL_3_ARG_TEST_VALUES[self.subtest_index] + for rb in MUL_3_ARG_TEST_VALUES: + for rc in MUL_3_ARG_TEST_VALUES: + initial_regs = [0] * 32 + initial_regs[2] = ra + initial_regs[3] = rb + initial_regs[4] = rc + # use "with" so as to close the files used + with Program(l, bigendian) as prog: + self.add_case(prog, initial_regs) + + +class TestPipeLong(MulTestHelper): + def test_mul_pipe_2_arg(self): + self.run_all(MulTestCases2Arg().test_data, "mul_pipe_caller_long_2_arg", + has_third_input=False) + + def helper_3_arg(self, subtest_index): + self.run_all(MulTestCases3Arg(subtest_index).test_data, + f"mul_pipe_caller_long_3_arg_{subtest_index}", + has_third_input=True) + + # split out as separate functions so some test + # runners can test them all in parallel + def test_mul_pipe_3_arg_0(self): + self.helper_3_arg(0) + + def test_mul_pipe_3_arg_1(self): + self.helper_3_arg(1) + + def test_mul_pipe_3_arg_2(self): + self.helper_3_arg(2) + + def test_mul_pipe_3_arg_3(self): + self.helper_3_arg(3) + + def test_mul_pipe_3_arg_4(self): + self.helper_3_arg(4) - runner = unittest.TextTestRunner() - runner.run(suite) + def test_mul_pipe_3_arg_5(self): + self.helper_3_arg(5) + + def test_mul_pipe_3_arg_6(self): + self.helper_3_arg(6) + + def test_mul_pipe_3_arg_7(self): + self.helper_3_arg(7) + + def test_mul_pipe_3_arg_8(self): + self.helper_3_arg(8) + + def test_mul_pipe_3_arg_9(self): + self.helper_3_arg(9) + + def test_mul_pipe_3_arg_10(self): + self.helper_3_arg(10) + + def test_mul_pipe_3_arg_11(self): + self.helper_3_arg(11) + + def test_mul_pipe_3_arg_12(self): + self.helper_3_arg(12) + + def test_mul_pipe_3_arg_13(self): + self.helper_3_arg(13) + + def test_mul_pipe_3_arg_14(self): + self.helper_3_arg(14) + + def test_mul_pipe_3_arg_15(self): + self.helper_3_arg(15) + + def test_all_values_covered(self): + count = len(MUL_3_ARG_TEST_VALUES) + for i in range(count): + getattr(self, f"test_mul_pipe_3_arg_{i}") + with self.assertRaises(AttributeError): + getattr(self, f"test_mul_pipe_3_arg_{count}") + + +if __name__ == "__main__": + unittest.main() -- 2.30.2