From 4a0b3a5423175eed7f1de9e975ee1fb20a2eb3ae Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 6 Jan 2015 14:37:50 +0100 Subject: [PATCH] Various small improvements to synth_xilinx --- passes/techmap/iopadmap.cc | 4 ++-- techlibs/xilinx/synth_xilinx.cc | 14 ++++++-------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 76d6115ae..75d02c828 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -62,8 +62,8 @@ struct IopadmapPass : public Pass { log("\n"); log(" -bits\n"); log(" create individual bit-wide buffers even for ports that\n"); - log(" are wider. (the default behavio is to create word-wide\n"); - log(" buffers use -widthparam to set the word size on the cell.)\n"); + log(" are wider. (the default behavior is to create word-wide\n"); + log(" buffers using -widthparam to set the word size on the cell.)\n"); log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 7b7dbd0fd..a0783740b 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -74,8 +74,7 @@ struct SynthXilinxPass : public Pass { log(" techmap -map +/xilinx/brams.v\n"); log("\n"); log(" fine:\n"); - log(" techmap\n"); - log(" opt -fast -full\n"); + log(" synth -run fine\n"); log("\n"); log(" map_luts:\n"); log(" abc -lut 6\n"); @@ -91,11 +90,11 @@ struct SynthXilinxPass : public Pass { log("\n"); log(" clkbuf:\n"); log(" select -set xilinx_clocks /t:FDRE %%x:+FDRE[C] /t:FDRE %%d\n"); - log(" iopadmap -inpad BUFGP O:I @xilinx_clocks\n"); + log(" iopadmap -bits -inpad BUFGP O:I @xilinx_clocks\n"); log("\n"); log(" iobuf:\n"); log(" select -set xilinx_nonclocks /w:* /t:BUFGP %%x:+BUFGP[I] %%d\n"); - log(" iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n"); + log(" iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n"); log("\n"); log(" edif:\n"); log(" write_edif synth.edif\n"); @@ -171,8 +170,7 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "fine")) { - Pass::call(design, "techmap"); - Pass::call(design, "opt -fast -full"); + Pass::call(design, "synth -run fine"); } if (check_label(active, run_from, run_to, "map_luts")) @@ -196,13 +194,13 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "clkbuf")) { Pass::call(design, stringf("select -set xilinx_clocks %s/t:FDRE %%x:+FDRE[C] %s/t:FDRE %%d", top_module.c_str(), top_module.c_str())); - Pass::call(design, "iopadmap -inpad BUFGP O:I @xilinx_clocks"); + Pass::call(design, "iopadmap -bits -inpad BUFGP O:I @xilinx_clocks"); } if (check_label(active, run_from, run_to, "iobuf")) { Pass::call(design, stringf("select -set xilinx_nonclocks %s/w:* %s/t:BUFGP %%x:+BUFGP[I] %%d", top_module.c_str(), top_module.c_str())); - Pass::call(design, "iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks"); + Pass::call(design, "iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks"); } if (check_label(active, run_from, run_to, "edif")) -- 2.30.2