From 4a0d2e2880fb4752666bbd4faaf340437aea1a04 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 20 Sep 2019 00:54:22 -0400 Subject: [PATCH] ac: reorder and print all radeon_info fields Reviewed-by: Bas Nieuwenhuizen --- src/amd/common/ac_gpu_info.c | 47 ++++++++++++++++++++++++++++++------ src/amd/common/ac_gpu_info.h | 25 ++++++++++--------- 2 files changed, 53 insertions(+), 19 deletions(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 885206fbe78..b1225985234 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -685,16 +685,35 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n", info->pci_domain, info->pci_bus, info->pci_dev, info->pci_func); + + printf(" name = %s\n", info->name); + printf(" marketing_name = %s\n", info->marketing_name); + printf(" is_pro_graphics = %u\n", info->is_pro_graphics); printf(" pci_id = 0x%x\n", info->pci_id); printf(" family = %i\n", info->family); printf(" chip_class = %i\n", info->chip_class); + printf(" family_id = %i\n", info->family_id); printf(" chip_external_rev = %i\n", info->chip_external_rev); - printf(" num_compute_rings = %u\n", info->num_compute_rings); - printf(" num_sdma_rings = %i\n", info->num_sdma_rings); printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq); - printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size); - printf(" tcc_harvested = %u\n", info->tcc_harvested); + printf("Features:\n"); + printf(" has_graphics = %i\n", info->has_graphics); + printf(" num_compute_rings = %u\n", info->num_compute_rings); + printf(" num_sdma_rings = %i\n", info->num_sdma_rings); + printf(" has_clear_state = %u\n", info->has_clear_state); + printf(" has_distributed_tess = %u\n", info->has_distributed_tess); + printf(" has_dcc_constant_encode = %u\n", info->has_dcc_constant_encode); + printf(" has_rbplus = %u\n", info->has_rbplus); + printf(" rbplus_allowed = %u\n", info->rbplus_allowed); + printf(" has_load_ctx_reg_pkt = %u\n", info->has_load_ctx_reg_pkt); + printf(" has_out_of_order_rast = %u\n", info->has_out_of_order_rast); + printf(" cpdma_prefetch_writes_memory = %u\n", info->cpdma_prefetch_writes_memory); + printf(" has_gfx9_scissor_bug = %i\n", info->has_gfx9_scissor_bug); + printf(" has_tc_compat_zrange_bug = %i\n", info->has_tc_compat_zrange_bug); + printf(" has_msaa_sample_loc_bug = %i\n", info->has_msaa_sample_loc_bug); + printf(" has_ls_vgpr_init_bug = %i\n", info->has_ls_vgpr_init_bug); + + printf("Display features:\n"); printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned); printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit); @@ -711,6 +730,10 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" min_alloc_size = %u\n", info->min_alloc_size); printf(" address32_hi = %u\n", info->address32_hi); printf(" has_dedicated_vram = %u\n", info->has_dedicated_vram); + printf(" num_sdp_interfaces = %u\n", info->num_sdp_interfaces); + printf(" num_tcc_blocks = %i\n", info->num_tcc_blocks); + printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size); + printf(" tcc_harvested = %u\n", info->tcc_harvested); printf("CP info:\n"); printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2); @@ -758,9 +781,11 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" max_shader_clock = %i\n", info->max_shader_clock); printf(" num_good_compute_units = %i\n", info->num_good_compute_units); printf(" num_good_cu_per_sh = %i\n", info->num_good_cu_per_sh); - printf(" num_tcc_blocks = %i\n", info->num_tcc_blocks); printf(" max_se = %i\n", info->max_se); printf(" max_sh_per_se = %i\n", info->max_sh_per_se); + printf(" max_wave64_per_simd = %i\n", info->max_wave64_per_simd); + printf(" num_physical_sgprs_per_simd = %i\n", info->num_physical_sgprs_per_simd); + printf(" num_physical_wave64_vgprs_per_simd = %i\n", info->num_physical_wave64_vgprs_per_simd); printf("Render backend info:\n"); printf(" pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override); @@ -769,9 +794,17 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes); printf(" enabled_rb_mask = 0x%x\n", info->enabled_rb_mask); printf(" max_alignment = %u\n", (unsigned)info->max_alignment); + printf(" pbb_max_alloc_count = %u\n", info->pbb_max_alloc_count); - printf("GB_ADDR_CONFIG:\n"); - if (info->chip_class >= GFX9) { + printf("GB_ADDR_CONFIG: 0x%08x\n", info->gb_addr_config); + if (info->chip_class >= GFX10) { + printf(" num_pipes = %u\n", + 1 << G_0098F8_NUM_PIPES(info->gb_addr_config)); + printf(" pipe_interleave_size = %u\n", + 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config)); + printf(" max_compressed_frags = %u\n", + 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config)); + } else if (info->chip_class == GFX9) { printf(" num_pipes = %u\n", 1 << G_0098F8_NUM_PIPES(info->gb_addr_config)); printf(" pipe_interleave_size = %u\n", diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index a2adab88ec4..c9e3e90848b 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -53,12 +53,12 @@ struct radeon_info { enum chip_class chip_class; uint32_t family_id; uint32_t chip_external_rev; + uint32_t clock_crystal_freq; + + /* Features. */ bool has_graphics; /* false if the chip is compute-only */ uint32_t num_compute_rings; uint32_t num_sdma_rings; - uint32_t clock_crystal_freq; - uint32_t tcc_cache_line_size; - bool tcc_harvested; bool has_clear_state; bool has_distributed_tess; bool has_dcc_constant_encode; @@ -67,9 +67,12 @@ struct radeon_info { bool has_load_ctx_reg_pkt; bool has_out_of_order_rast; bool cpdma_prefetch_writes_memory; - uint32_t pbb_max_alloc_count; - uint32_t num_sdp_interfaces; + bool has_gfx9_scissor_bug; + bool has_tc_compat_zrange_bug; + bool has_msaa_sample_loc_bug; + bool has_ls_vgpr_init_bug; + /* Display features. */ /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ bool use_display_dcc_unaligned; @@ -89,6 +92,10 @@ struct radeon_info { uint32_t address32_hi; bool has_dedicated_vram; bool r600_has_virtual_memory; + uint32_t num_sdp_interfaces; + uint32_t num_tcc_blocks; + uint32_t tcc_cache_line_size; + bool tcc_harvested; /* CP info. */ bool gfx_ib_pad_with_type2; @@ -139,7 +146,6 @@ struct radeon_info { uint32_t max_shader_clock; uint32_t num_good_compute_units; uint32_t num_good_cu_per_sh; - uint32_t num_tcc_blocks; uint32_t max_se; /* shader engines */ uint32_t max_sh_per_se; /* shader arrays per shader engine */ uint32_t max_wave64_per_simd; @@ -159,16 +165,11 @@ struct radeon_info { uint32_t pipe_interleave_bytes; uint32_t enabled_rb_mask; /* GCN harvest config */ uint64_t max_alignment; /* from addrlib */ + uint32_t pbb_max_alloc_count; /* Tile modes. */ uint32_t si_tile_mode_array[32]; uint32_t cik_macrotile_mode_array[16]; - - /* Hardware bugs. */ - bool has_gfx9_scissor_bug; - bool has_tc_compat_zrange_bug; - bool has_msaa_sample_loc_bug; - bool has_ls_vgpr_init_bug; }; bool ac_query_gpu_info(int fd, void *dev_p, -- 2.30.2