From 4a232b87d4f30726b98bd897430808de6645ee83 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 25 Mar 2020 12:33:24 +0000 Subject: [PATCH] Re: [libre-riscv-dev] cache SRAM organisation --- 9a/b1ba6229d4be5f35993944c2bacb205527b2fc | 161 ++++++++++++++++++++++ 1 file changed, 161 insertions(+) create mode 100644 9a/b1ba6229d4be5f35993944c2bacb205527b2fc diff --git a/9a/b1ba6229d4be5f35993944c2bacb205527b2fc b/9a/b1ba6229d4be5f35993944c2bacb205527b2fc new file mode 100644 index 0000000..425499c --- /dev/null +++ b/9a/b1ba6229d4be5f35993944c2bacb205527b2fc @@ -0,0 +1,161 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Wed, 25 Mar 2020 12:33:58 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jH5EL-0007W7-Oa; Wed, 25 Mar 2020 12:33:57 +0000 +Received: from lkcl.net ([217.147.94.29]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + 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