From 4a2588399fd9840a4b64f68f10077f767a5162bf Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 30 Jan 2022 22:08:38 +0000 Subject: [PATCH] remove CacheTagArray in icache.py --- src/soc/experiment/icache.py | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index 71b3f989..697e8e25 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -187,10 +187,6 @@ assert (REAL_ADDR_BITS == (TAG_BITS + ROW_BITS + ROW_OFF_BITS)), \ # The cache tags LUTRAM has a row per set. Vivado is a pain and will # not handle a clean (commented) definition of the cache tags as a 3d # memory. For now, work around it by putting all the tags -def CacheTagArray(): - return Array(Signal(TAG_RAM_WIDTH, name="tag%d" % x) \ - for x in range(NUM_LINES)) - def CacheValidsArray(): return Array(Signal(NUM_WAYS, name="tag_valids%d" % x) \ for x in range(NUM_LINES)) -- 2.30.2