From 4a306116670c5747b682948e0fd3f9a62051c7c6 Mon Sep 17 00:00:00 2001 From: Dave Brolley Date: Fri, 29 Aug 2003 16:41:31 +0000 Subject: [PATCH] New sim testsuite for Fujitsu FRV. Contributed by Red Hat. --- sim/testsuite/frv-elf/ChangeLog | 34 + sim/testsuite/frv-elf/Makefile.in | 159 + sim/testsuite/frv-elf/cache.s | 164 + sim/testsuite/frv-elf/configure | 905 +++++ sim/testsuite/frv-elf/configure.in | 19 + sim/testsuite/frv-elf/exit47.s | 5 + sim/testsuite/frv-elf/grloop.s | 10 + sim/testsuite/frv-elf/hello.s | 16 + sim/testsuite/frv-elf/loop.s | 2 + sim/testsuite/sim/frv/add.cgs | 23 + sim/testsuite/sim/frv/add.pcgs | 25 + sim/testsuite/sim/frv/addcc.cgs | 36 + sim/testsuite/sim/frv/addi.cgs | 25 + sim/testsuite/sim/frv/addicc.cgs | 30 + sim/testsuite/sim/frv/addx.cgs | 49 + sim/testsuite/sim/frv/addxcc.cgs | 49 + sim/testsuite/sim/frv/addxi.cgs | 46 + sim/testsuite/sim/frv/addxicc.cgs | 46 + sim/testsuite/sim/frv/allinsn.exp | 19 + sim/testsuite/sim/frv/and.cgs | 29 + sim/testsuite/sim/frv/andcc.cgs | 29 + sim/testsuite/sim/frv/andcr.cgs | 59 + sim/testsuite/sim/frv/andi.cgs | 26 + sim/testsuite/sim/frv/andicc.cgs | 26 + sim/testsuite/sim/frv/andncr.cgs | 59 + sim/testsuite/sim/frv/bar.cgs | 12 + sim/testsuite/sim/frv/bc.cgs | 61 + sim/testsuite/sim/frv/bcclr.cgs | 293 ++ sim/testsuite/sim/frv/bceqlr.cgs | 293 ++ sim/testsuite/sim/frv/bcgelr.cgs | 293 ++ sim/testsuite/sim/frv/bcgtlr.cgs | 284 ++ sim/testsuite/sim/frv/bchilr.cgs | 284 ++ sim/testsuite/sim/frv/bclelr.cgs | 301 ++ sim/testsuite/sim/frv/bclr.cgs | 84 + sim/testsuite/sim/frv/bclslr.cgs | 301 ++ sim/testsuite/sim/frv/bcltlr.cgs | 292 ++ sim/testsuite/sim/frv/bcnclr.cgs | 293 ++ sim/testsuite/sim/frv/bcnelr.cgs | 292 ++ sim/testsuite/sim/frv/bcnlr.cgs | 293 ++ sim/testsuite/sim/frv/bcnolr.cgs | 246 ++ sim/testsuite/sim/frv/bcnvlr.cgs | 292 ++ sim/testsuite/sim/frv/bcplr.cgs | 292 ++ sim/testsuite/sim/frv/bcralr.cgs | 309 ++ sim/testsuite/sim/frv/bctrlr.cgs | 29 + sim/testsuite/sim/frv/bcvlr.cgs | 293 ++ sim/testsuite/sim/frv/beq.cgs | 61 + sim/testsuite/sim/frv/beqlr.cgs | 71 + sim/testsuite/sim/frv/bge.cgs | 61 + sim/testsuite/sim/frv/bgelr.cgs | 84 + sim/testsuite/sim/frv/bgt.cgs | 53 + sim/testsuite/sim/frv/bgtlr.cgs | 80 + sim/testsuite/sim/frv/bhi.cgs | 53 + sim/testsuite/sim/frv/bhilr.cgs | 80 + sim/testsuite/sim/frv/ble.cgs | 69 + sim/testsuite/sim/frv/blelr.cgs | 88 + sim/testsuite/sim/frv/bls.cgs | 69 + sim/testsuite/sim/frv/blslr.cgs | 88 + sim/testsuite/sim/frv/blt.cgs | 61 + sim/testsuite/sim/frv/bltlr.cgs | 84 + sim/testsuite/sim/frv/bn.cgs | 61 + sim/testsuite/sim/frv/bnc.cgs | 61 + sim/testsuite/sim/frv/bnclr.cgs | 84 + sim/testsuite/sim/frv/bne.cgs | 61 + sim/testsuite/sim/frv/bnelr.cgs | 84 + sim/testsuite/sim/frv/bnlr.cgs | 84 + sim/testsuite/sim/frv/bno.cgs | 45 + sim/testsuite/sim/frv/bnolr.cgs | 61 + sim/testsuite/sim/frv/bnv.cgs | 61 + sim/testsuite/sim/frv/bnvlr.cgs | 84 + sim/testsuite/sim/frv/bp.cgs | 61 + sim/testsuite/sim/frv/bplr.cgs | 84 + sim/testsuite/sim/frv/bra.cgs | 75 + sim/testsuite/sim/frv/bralr.cgs | 91 + sim/testsuite/sim/frv/branch.pcgs | 63 + sim/testsuite/sim/frv/break.cgs | 58 + sim/testsuite/sim/frv/bv.cgs | 61 + sim/testsuite/sim/frv/bvlr.cgs | 84 + sim/testsuite/sim/frv/cadd.cgs | 90 + sim/testsuite/sim/frv/caddcc.cgs | 163 + sim/testsuite/sim/frv/call.cgs | 17 + sim/testsuite/sim/frv/call.pcgs | 30 + sim/testsuite/sim/frv/callil.cgs | 26 + sim/testsuite/sim/frv/calll.cgs | 28 + sim/testsuite/sim/frv/cand.cgs | 126 + sim/testsuite/sim/frv/candcc.cgs | 126 + sim/testsuite/sim/frv/ccalll.cgs | 101 + sim/testsuite/sim/frv/cckc.cgs | 490 +++ sim/testsuite/sim/frv/cckeq.cgs | 490 +++ sim/testsuite/sim/frv/cckge.cgs | 490 +++ sim/testsuite/sim/frv/cckgt.cgs | 490 +++ sim/testsuite/sim/frv/cckhi.cgs | 490 +++ sim/testsuite/sim/frv/cckle.cgs | 490 +++ sim/testsuite/sim/frv/cckls.cgs | 490 +++ sim/testsuite/sim/frv/ccklt.cgs | 490 +++ sim/testsuite/sim/frv/cckn.cgs | 490 +++ sim/testsuite/sim/frv/ccknc.cgs | 490 +++ sim/testsuite/sim/frv/cckne.cgs | 490 +++ sim/testsuite/sim/frv/cckno.cgs | 490 +++ sim/testsuite/sim/frv/ccknv.cgs | 490 +++ sim/testsuite/sim/frv/cckp.cgs | 490 +++ sim/testsuite/sim/frv/cckra.cgs | 480 +++ sim/testsuite/sim/frv/cckv.cgs | 490 +++ sim/testsuite/sim/frv/ccmp.cgs | 134 + sim/testsuite/sim/frv/cfabss.cgs | 96 + sim/testsuite/sim/frv/cfadds.cgs | 456 +++ sim/testsuite/sim/frv/cfckeq.cgs | 490 +++ sim/testsuite/sim/frv/cfckge.cgs | 490 +++ sim/testsuite/sim/frv/cfckgt.cgs | 490 +++ sim/testsuite/sim/frv/cfckle.cgs | 490 +++ sim/testsuite/sim/frv/cfcklg.cgs | 490 +++ sim/testsuite/sim/frv/cfcklt.cgs | 490 +++ sim/testsuite/sim/frv/cfckne.cgs | 490 +++ sim/testsuite/sim/frv/cfckno.cgs | 490 +++ sim/testsuite/sim/frv/cfcko.cgs | 490 +++ sim/testsuite/sim/frv/cfckra.cgs | 490 +++ sim/testsuite/sim/frv/cfcku.cgs | 490 +++ sim/testsuite/sim/frv/cfckue.cgs | 490 +++ sim/testsuite/sim/frv/cfckug.cgs | 490 +++ sim/testsuite/sim/frv/cfckuge.cgs | 490 +++ sim/testsuite/sim/frv/cfckul.cgs | 410 ++ sim/testsuite/sim/frv/cfckule.cgs | 490 +++ sim/testsuite/sim/frv/cfcmps.cgs | 3542 +++++++++++++++++ sim/testsuite/sim/frv/cfdivs.cgs | 696 ++++ sim/testsuite/sim/frv/cfitos.cgs | 88 + sim/testsuite/sim/frv/cfmadds.cgs | 627 +++ sim/testsuite/sim/frv/cfmas.cgs | 775 ++++ sim/testsuite/sim/frv/cfmovs.cgs | 216 + sim/testsuite/sim/frv/cfmss.cgs | 697 ++++ sim/testsuite/sim/frv/cfmsubs.cgs | 629 +++ sim/testsuite/sim/frv/cfmuls.cgs | 696 ++++ sim/testsuite/sim/frv/cfnegs.cgs | 96 + sim/testsuite/sim/frv/cfsqrts.cgs | 60 + sim/testsuite/sim/frv/cfstoi.cgs | 83 + sim/testsuite/sim/frv/cfsubs.cgs | 412 ++ sim/testsuite/sim/frv/cjmpl.cgs | 55 + sim/testsuite/sim/frv/ckc.cgs | 90 + sim/testsuite/sim/frv/ckeq.cgs | 90 + sim/testsuite/sim/frv/ckge.cgs | 90 + sim/testsuite/sim/frv/ckgt.cgs | 90 + sim/testsuite/sim/frv/ckhi.cgs | 90 + sim/testsuite/sim/frv/ckle.cgs | 90 + sim/testsuite/sim/frv/ckls.cgs | 90 + sim/testsuite/sim/frv/cklt.cgs | 90 + sim/testsuite/sim/frv/ckn.cgs | 90 + sim/testsuite/sim/frv/cknc.cgs | 90 + sim/testsuite/sim/frv/ckne.cgs | 90 + sim/testsuite/sim/frv/ckno.cgs | 90 + sim/testsuite/sim/frv/cknv.cgs | 90 + sim/testsuite/sim/frv/ckp.cgs | 90 + sim/testsuite/sim/frv/ckra.cgs | 90 + sim/testsuite/sim/frv/ckv.cgs | 90 + sim/testsuite/sim/frv/cld.cgs | 126 + sim/testsuite/sim/frv/cldbf.cgs | 114 + sim/testsuite/sim/frv/cldbfu.cgs | 154 + sim/testsuite/sim/frv/cldd.cgs | 168 + sim/testsuite/sim/frv/clddf.cgs | 174 + sim/testsuite/sim/frv/clddfu.cgs | 212 + sim/testsuite/sim/frv/clddu.cgs | 219 + sim/testsuite/sim/frv/cldf.cgs | 126 + sim/testsuite/sim/frv/cldfu.cgs | 164 + sim/testsuite/sim/frv/cldhf.cgs | 114 + sim/testsuite/sim/frv/cldhfu.cgs | 152 + sim/testsuite/sim/frv/cldq.cgs | 276 ++ sim/testsuite/sim/frv/cldqu.cgs | 318 ++ sim/testsuite/sim/frv/cldsb.cgs | 114 + sim/testsuite/sim/frv/cldsbu.cgs | 162 + sim/testsuite/sim/frv/cldsh.cgs | 114 + sim/testsuite/sim/frv/cldshu.cgs | 159 + sim/testsuite/sim/frv/cldu.cgs | 172 + sim/testsuite/sim/frv/cldub.cgs | 114 + sim/testsuite/sim/frv/cldubu.cgs | 155 + sim/testsuite/sim/frv/clduh.cgs | 114 + sim/testsuite/sim/frv/clduhu.cgs | 159 + sim/testsuite/sim/frv/clrfa.cgs | 27 + sim/testsuite/sim/frv/clrfr.cgs | 27 + sim/testsuite/sim/frv/clrga.cgs | 27 + sim/testsuite/sim/frv/clrgr.cgs | 27 + sim/testsuite/sim/frv/cmaddhss.cgs | 562 +++ sim/testsuite/sim/frv/cmaddhus.cgs | 496 +++ sim/testsuite/sim/frv/cmand.cgs | 89 + sim/testsuite/sim/frv/cmbtoh.cgs | 74 + sim/testsuite/sim/frv/cmbtohe.cgs | 100 + sim/testsuite/sim/frv/cmcpxis.cgs | 971 +++++ sim/testsuite/sim/frv/cmcpxiu.cgs | 508 +++ sim/testsuite/sim/frv/cmcpxrs.cgs | 649 +++ sim/testsuite/sim/frv/cmcpxru.cgs | 544 +++ sim/testsuite/sim/frv/cmexpdhd.cgs | 116 + sim/testsuite/sim/frv/cmexpdhw.cgs | 91 + sim/testsuite/sim/frv/cmhtob.cgs | 103 + sim/testsuite/sim/frv/cmmachs.cgs | 1631 ++++++++ sim/testsuite/sim/frv/cmmachu.cgs | 864 ++++ sim/testsuite/sim/frv/cmmulhs.cgs | 814 ++++ sim/testsuite/sim/frv/cmmulhu.cgs | 460 +++ sim/testsuite/sim/frv/cmnot.cgs | 60 + sim/testsuite/sim/frv/cmor.cgs | 101 + sim/testsuite/sim/frv/cmov.cgs | 54 + sim/testsuite/sim/frv/cmovfg.cgs | 84 + sim/testsuite/sim/frv/cmovfgd.cgs | 132 + sim/testsuite/sim/frv/cmovgf.cgs | 84 + sim/testsuite/sim/frv/cmovgfd.cgs | 132 + sim/testsuite/sim/frv/cmp.cgs | 31 + sim/testsuite/sim/frv/cmpb.cgs | 41 + sim/testsuite/sim/frv/cmpba.cgs | 41 + sim/testsuite/sim/frv/cmpi.cgs | 50 + sim/testsuite/sim/frv/cmqmachs.cgs | 1268 ++++++ sim/testsuite/sim/frv/cmqmachu.cgs | 876 ++++ sim/testsuite/sim/frv/cmqmulhs.cgs | 734 ++++ sim/testsuite/sim/frv/cmqmulhu.cgs | 464 +++ sim/testsuite/sim/frv/cmsubhss.cgs | 562 +++ sim/testsuite/sim/frv/cmsubhus.cgs | 442 ++ sim/testsuite/sim/frv/cmxor.cgs | 132 + sim/testsuite/sim/frv/cnot.cgs | 60 + sim/testsuite/sim/frv/commitfa.cgs | 61 + sim/testsuite/sim/frv/commitfr.cgs | 61 + sim/testsuite/sim/frv/commitga.cgs | 62 + sim/testsuite/sim/frv/commitgr.cgs | 62 + sim/testsuite/sim/frv/cop1.cgs | 14 + sim/testsuite/sim/frv/cop2.cgs | 14 + sim/testsuite/sim/frv/cor.cgs | 138 + sim/testsuite/sim/frv/corcc.cgs | 138 + sim/testsuite/sim/frv/cscan.cgs | 394 ++ sim/testsuite/sim/frv/csdiv.cgs | 190 + sim/testsuite/sim/frv/csll.cgs | 180 + sim/testsuite/sim/frv/csllcc.cgs | 180 + sim/testsuite/sim/frv/csmul.cgs | 1044 +++++ sim/testsuite/sim/frv/csmulcc.cgs | 1380 +++++++ sim/testsuite/sim/frv/csra.cgs | 180 + sim/testsuite/sim/frv/csracc.cgs | 180 + sim/testsuite/sim/frv/csrl.cgs | 180 + sim/testsuite/sim/frv/csrlcc.cgs | 180 + sim/testsuite/sim/frv/cst.cgs | 126 + sim/testsuite/sim/frv/cstb.cgs | 120 + sim/testsuite/sim/frv/cstbf.cgs | 120 + sim/testsuite/sim/frv/cstbfu.cgs | 152 + sim/testsuite/sim/frv/cstbu.cgs | 152 + sim/testsuite/sim/frv/cstd.cgs | 221 + sim/testsuite/sim/frv/cstdf.cgs | 222 ++ sim/testsuite/sim/frv/cstdfu.cgs | 248 ++ sim/testsuite/sim/frv/cstdu.cgs | 251 ++ sim/testsuite/sim/frv/cstf.cgs | 126 + sim/testsuite/sim/frv/cstfu.cgs | 158 + sim/testsuite/sim/frv/csth.cgs | 120 + sim/testsuite/sim/frv/csthf.cgs | 120 + sim/testsuite/sim/frv/csthfu.cgs | 150 + sim/testsuite/sim/frv/csthu.cgs | 150 + sim/testsuite/sim/frv/cstq.cgs | 355 ++ sim/testsuite/sim/frv/cstu.cgs | 152 + sim/testsuite/sim/frv/csub.cgs | 108 + sim/testsuite/sim/frv/csubcc.cgs | 156 + sim/testsuite/sim/frv/cswap.cgs | 212 + sim/testsuite/sim/frv/cudiv.cgs | 96 + sim/testsuite/sim/frv/cxor.cgs | 180 + sim/testsuite/sim/frv/cxorcc.cgs | 180 + sim/testsuite/sim/frv/dcef.cgs | 50 + sim/testsuite/sim/frv/dcei.cgs | 27 + sim/testsuite/sim/frv/dcf.cgs | 39 + sim/testsuite/sim/frv/dci.cgs | 22 + sim/testsuite/sim/frv/fabsd.cgs | 26 + sim/testsuite/sim/frv/fabss.cgs | 25 + sim/testsuite/sim/frv/faddd.cgs | 93 + sim/testsuite/sim/frv/fadds.cgs | 92 + sim/testsuite/sim/frv/fbeq.cgs | 61 + sim/testsuite/sim/frv/fbeqlr.cgs | 84 + sim/testsuite/sim/frv/fbge.cgs | 69 + sim/testsuite/sim/frv/fbgelr.cgs | 88 + sim/testsuite/sim/frv/fbgt.cgs | 61 + sim/testsuite/sim/frv/fbgtlr.cgs | 84 + sim/testsuite/sim/frv/fble.cgs | 69 + sim/testsuite/sim/frv/fblelr.cgs | 89 + sim/testsuite/sim/frv/fblg.cgs | 69 + sim/testsuite/sim/frv/fblglr.cgs | 88 + sim/testsuite/sim/frv/fblt.cgs | 61 + sim/testsuite/sim/frv/fbltlr.cgs | 84 + sim/testsuite/sim/frv/fbne.cgs | 73 + sim/testsuite/sim/frv/fbnelr.cgs | 90 + sim/testsuite/sim/frv/fbno.cgs | 45 + sim/testsuite/sim/frv/fbnolr.cgs | 47 + sim/testsuite/sim/frv/fbo.cgs | 73 + sim/testsuite/sim/frv/fbolr.cgs | 90 + sim/testsuite/sim/frv/fbra.cgs | 75 + sim/testsuite/sim/frv/fbralr.cgs | 91 + sim/testsuite/sim/frv/fbu.cgs | 61 + sim/testsuite/sim/frv/fbue.cgs | 69 + sim/testsuite/sim/frv/fbuelr.cgs | 88 + sim/testsuite/sim/frv/fbug.cgs | 69 + sim/testsuite/sim/frv/fbuge.cgs | 73 + sim/testsuite/sim/frv/fbugelr.cgs | 90 + sim/testsuite/sim/frv/fbuglr.cgs | 88 + sim/testsuite/sim/frv/fbul.cgs | 69 + sim/testsuite/sim/frv/fbule.cgs | 73 + sim/testsuite/sim/frv/fbulelr.cgs | 90 + sim/testsuite/sim/frv/fbullr.cgs | 88 + sim/testsuite/sim/frv/fbulr.cgs | 84 + sim/testsuite/sim/frv/fcbeqlr.cgs | 262 ++ sim/testsuite/sim/frv/fcbgelr.cgs | 270 ++ sim/testsuite/sim/frv/fcbgtlr.cgs | 262 ++ sim/testsuite/sim/frv/fcblelr.cgs | 270 ++ sim/testsuite/sim/frv/fcblglr.cgs | 270 ++ sim/testsuite/sim/frv/fcbltlr.cgs | 262 ++ sim/testsuite/sim/frv/fcbnelr.cgs | 274 ++ sim/testsuite/sim/frv/fcbnolr.cgs | 185 + sim/testsuite/sim/frv/fcbolr.cgs | 274 ++ sim/testsuite/sim/frv/fcbralr.cgs | 276 ++ sim/testsuite/sim/frv/fcbuelr.cgs | 270 ++ sim/testsuite/sim/frv/fcbugelr.cgs | 274 ++ sim/testsuite/sim/frv/fcbuglr.cgs | 270 ++ sim/testsuite/sim/frv/fcbulelr.cgs | 274 ++ sim/testsuite/sim/frv/fcbullr.cgs | 270 ++ sim/testsuite/sim/frv/fcbulr.cgs | 262 ++ sim/testsuite/sim/frv/fckeq.cgs | 90 + sim/testsuite/sim/frv/fckge.cgs | 90 + sim/testsuite/sim/frv/fckgt.cgs | 90 + sim/testsuite/sim/frv/fckle.cgs | 90 + sim/testsuite/sim/frv/fcklg.cgs | 90 + sim/testsuite/sim/frv/fcklt.cgs | 90 + sim/testsuite/sim/frv/fckne.cgs | 90 + sim/testsuite/sim/frv/fckno.cgs | 90 + sim/testsuite/sim/frv/fcko.cgs | 90 + sim/testsuite/sim/frv/fckra.cgs | 90 + sim/testsuite/sim/frv/fcku.cgs | 90 + sim/testsuite/sim/frv/fckue.cgs | 90 + sim/testsuite/sim/frv/fckug.cgs | 90 + sim/testsuite/sim/frv/fckuge.cgs | 90 + sim/testsuite/sim/frv/fckul.cgs | 90 + sim/testsuite/sim/frv/fckule.cgs | 90 + sim/testsuite/sim/frv/fcmpd.cgs | 601 +++ sim/testsuite/sim/frv/fcmps.cgs | 600 +++ sim/testsuite/sim/frv/fdabss.cgs | 25 + sim/testsuite/sim/frv/fdadds.cgs | 134 + sim/testsuite/sim/frv/fdcmps.cgs | 985 +++++ sim/testsuite/sim/frv/fddivs.cgs | 195 + sim/testsuite/sim/frv/fditos.cgs | 25 + sim/testsuite/sim/frv/fdivd.cgs | 128 + sim/testsuite/sim/frv/fdivs.cgs | 127 + sim/testsuite/sim/frv/fdmadds.cgs | 226 ++ sim/testsuite/sim/frv/fdmas.cgs | 265 ++ sim/testsuite/sim/frv/fdmovs.cgs | 45 + sim/testsuite/sim/frv/fdmss.cgs | 235 ++ sim/testsuite/sim/frv/fdmulcs.cgs | 201 + sim/testsuite/sim/frv/fdmuls.cgs | 193 + sim/testsuite/sim/frv/fdnegs.cgs | 25 + sim/testsuite/sim/frv/fdsads.cgs | 119 + sim/testsuite/sim/frv/fdsqrts.cgs | 17 + sim/testsuite/sim/frv/fdstoi.cgs | 23 + sim/testsuite/sim/frv/fdsubs.cgs | 117 + sim/testsuite/sim/frv/fdtoi.cgs | 32 + sim/testsuite/sim/frv/fitod.cgs | 26 + sim/testsuite/sim/frv/fitos.cgs | 25 + sim/testsuite/sim/frv/fmad.cgs | 161 + sim/testsuite/sim/frv/fmaddd.cgs | 143 + sim/testsuite/sim/frv/fmadds.cgs | 143 + sim/testsuite/sim/frv/fmas.cgs | 161 + sim/testsuite/sim/frv/fmovd.cgs | 48 + sim/testsuite/sim/frv/fmovs.cgs | 45 + sim/testsuite/sim/frv/fmsd.cgs | 146 + sim/testsuite/sim/frv/fmss.cgs | 146 + sim/testsuite/sim/frv/fmsubd.cgs | 144 + sim/testsuite/sim/frv/fmsubs.cgs | 144 + sim/testsuite/sim/frv/fmuld.cgs | 126 + sim/testsuite/sim/frv/fmuls.cgs | 125 + sim/testsuite/sim/frv/fnegd.cgs | 26 + sim/testsuite/sim/frv/fnegs.cgs | 25 + sim/testsuite/sim/frv/fnop.cgs | 12 + sim/testsuite/sim/frv/fr400/allinsn.exp | 19 + sim/testsuite/sim/frv/fr400/csdiv.cgs | 187 + sim/testsuite/sim/frv/fr400/maveh.cgs | 319 ++ sim/testsuite/sim/frv/fr400/mclracc.cgs | 79 + sim/testsuite/sim/frv/fr400/mhdseth.cgs | 22 + sim/testsuite/sim/frv/fr400/mhdsets.cgs | 20 + sim/testsuite/sim/frv/fr400/mhsethih.cgs | 22 + sim/testsuite/sim/frv/fr400/mhsethis.cgs | 25 + sim/testsuite/sim/frv/fr400/mhsetloh.cgs | 27 + sim/testsuite/sim/frv/fr400/mhsetlos.cgs | 25 + sim/testsuite/sim/frv/fr400/sdiv.cgs | 71 + sim/testsuite/sim/frv/fr400/sdivi.cgs | 70 + sim/testsuite/sim/frv/fr400/udiv.cgs | 46 + sim/testsuite/sim/frv/fr400/udivi.cgs | 47 + sim/testsuite/sim/frv/fr500/allinsn.exp | 19 + sim/testsuite/sim/frv/fr500/cmqaddhss.cgs | 444 +++ sim/testsuite/sim/frv/fr500/cmqaddhus.cgs | 360 ++ sim/testsuite/sim/frv/fr500/cmqsubhss.cgs | 448 +++ sim/testsuite/sim/frv/fr500/cmqsubhus.cgs | 370 ++ sim/testsuite/sim/frv/fr500/dcpl.cgs | 65 + sim/testsuite/sim/frv/fr500/dcul.cgs | 118 + sim/testsuite/sim/frv/fr500/mclracc.cgs | 79 + sim/testsuite/sim/frv/fr500/mqaddhss.cgs | 79 + sim/testsuite/sim/frv/fr500/mqaddhus.cgs | 65 + sim/testsuite/sim/frv/fr500/mqsubhss.cgs | 79 + sim/testsuite/sim/frv/fr500/mqsubhus.cgs | 66 + sim/testsuite/sim/frv/fsqrtd.cgs | 22 + sim/testsuite/sim/frv/fsqrts.cgs | 19 + sim/testsuite/sim/frv/fstoi.cgs | 24 + sim/testsuite/sim/frv/fsubd.cgs | 83 + sim/testsuite/sim/frv/fsubs.cgs | 82 + sim/testsuite/sim/frv/fteq.cgs | 101 + sim/testsuite/sim/frv/ftge.cgs | 109 + sim/testsuite/sim/frv/ftgt.cgs | 101 + sim/testsuite/sim/frv/ftieq.cgs | 100 + sim/testsuite/sim/frv/ftige.cgs | 108 + sim/testsuite/sim/frv/ftigt.cgs | 100 + sim/testsuite/sim/frv/ftile.cgs | 108 + sim/testsuite/sim/frv/ftilg.cgs | 108 + sim/testsuite/sim/frv/ftilt.cgs | 100 + sim/testsuite/sim/frv/ftine.cgs | 112 + sim/testsuite/sim/frv/ftino.cgs | 53 + sim/testsuite/sim/frv/ftio.cgs | 112 + sim/testsuite/sim/frv/ftira.cgs | 114 + sim/testsuite/sim/frv/ftiu.cgs | 100 + sim/testsuite/sim/frv/ftiue.cgs | 108 + sim/testsuite/sim/frv/ftiug.cgs | 108 + sim/testsuite/sim/frv/ftiuge.cgs | 112 + sim/testsuite/sim/frv/ftiul.cgs | 108 + sim/testsuite/sim/frv/ftle.cgs | 109 + sim/testsuite/sim/frv/ftlg.cgs | 109 + sim/testsuite/sim/frv/ftlt.cgs | 101 + sim/testsuite/sim/frv/ftne.cgs | 113 + sim/testsuite/sim/frv/ftno.cgs | 54 + sim/testsuite/sim/frv/fto.cgs | 113 + sim/testsuite/sim/frv/ftra.cgs | 115 + sim/testsuite/sim/frv/ftu.cgs | 101 + sim/testsuite/sim/frv/ftue.cgs | 109 + sim/testsuite/sim/frv/ftug.cgs | 109 + sim/testsuite/sim/frv/ftuge.cgs | 113 + sim/testsuite/sim/frv/ftul.cgs | 109 + sim/testsuite/sim/frv/ftule.cgs | 113 + sim/testsuite/sim/frv/icei.cgs | 15 + sim/testsuite/sim/frv/ici.cgs | 39 + sim/testsuite/sim/frv/icpl.cgs | 39 + sim/testsuite/sim/frv/icul.cgs | 53 + sim/testsuite/sim/frv/interrupts.exp | 19 + sim/testsuite/sim/frv/interrupts/Ipipe.cgs | 35 + sim/testsuite/sim/frv/interrupts/badalign.cgs | 73 + sim/testsuite/sim/frv/interrupts/compound.cgs | 66 + .../sim/frv/interrupts/data_store_error.cgs | 53 + .../sim/frv/interrupts/fp_exception.cgs | 191 + sim/testsuite/sim/frv/interrupts/illinsn.cgs | 34 + .../sim/frv/interrupts/insn_access_error.cgs | 56 + .../sim/frv/interrupts/mp_exception.cgs | 289 ++ .../frv/interrupts/privileged_instruction.cgs | 54 + sim/testsuite/sim/frv/interrupts/regalign.cgs | 96 + sim/testsuite/sim/frv/interrupts/reset.cgs | 81 + .../sim/frv/interrupts/shadow_regs.cgs | 205 + sim/testsuite/sim/frv/interrupts/timer.cgs | 31 + sim/testsuite/sim/frv/jmpil.cgs | 17 + sim/testsuite/sim/frv/jmpl.cgs | 18 + sim/testsuite/sim/frv/jmpl.pcgs | 42 + sim/testsuite/sim/frv/ld.cgs | 29 + sim/testsuite/sim/frv/ldbf.cgs | 27 + sim/testsuite/sim/frv/ldbfi.cgs | 24 + sim/testsuite/sim/frv/ldbfu.cgs | 34 + sim/testsuite/sim/frv/ldc.cgs | 30 + sim/testsuite/sim/frv/ldcu.cgs | 34 + sim/testsuite/sim/frv/ldd.cgs | 43 + sim/testsuite/sim/frv/lddc.cgs | 45 + sim/testsuite/sim/frv/lddcu.cgs | 42 + sim/testsuite/sim/frv/lddf.cgs | 46 + sim/testsuite/sim/frv/lddfi.cgs | 34 + sim/testsuite/sim/frv/lddfu.cgs | 41 + sim/testsuite/sim/frv/lddi.cgs | 34 + sim/testsuite/sim/frv/lddu.cgs | 50 + sim/testsuite/sim/frv/ldf.cgs | 29 + sim/testsuite/sim/frv/ldfi.cgs | 26 + sim/testsuite/sim/frv/ldfu.cgs | 33 + sim/testsuite/sim/frv/ldhf.cgs | 27 + sim/testsuite/sim/frv/ldhfi.cgs | 24 + sim/testsuite/sim/frv/ldhfu.cgs | 33 + sim/testsuite/sim/frv/ldi.cgs | 26 + sim/testsuite/sim/frv/ldq.cgs | 64 + sim/testsuite/sim/frv/ldqc.cgs | 60 + sim/testsuite/sim/frv/ldqcu.cgs | 57 + sim/testsuite/sim/frv/ldqf.cgs | 61 + sim/testsuite/sim/frv/ldqfi.cgs | 51 + sim/testsuite/sim/frv/ldqfu.cgs | 58 + sim/testsuite/sim/frv/ldqi.cgs | 51 + sim/testsuite/sim/frv/ldqu.cgs | 71 + sim/testsuite/sim/frv/ldsb.cgs | 27 + sim/testsuite/sim/frv/ldsbi.cgs | 24 + sim/testsuite/sim/frv/ldsbu.cgs | 40 + sim/testsuite/sim/frv/ldsh.cgs | 27 + sim/testsuite/sim/frv/ldshi.cgs | 24 + sim/testsuite/sim/frv/ldshu.cgs | 39 + sim/testsuite/sim/frv/ldu.cgs | 39 + sim/testsuite/sim/frv/ldub.cgs | 27 + sim/testsuite/sim/frv/ldubi.cgs | 24 + sim/testsuite/sim/frv/ldubu.cgs | 39 + sim/testsuite/sim/frv/lduh.cgs | 27 + sim/testsuite/sim/frv/lduhi.cgs | 24 + sim/testsuite/sim/frv/lduhu.cgs | 39 + sim/testsuite/sim/frv/lrbranch.pcgs | 51 + sim/testsuite/sim/frv/mabshs.cgs | 67 + sim/testsuite/sim/frv/maddaccs.cgs | 131 + sim/testsuite/sim/frv/maddhss.cgs | 100 + sim/testsuite/sim/frv/maddhus.cgs | 89 + sim/testsuite/sim/frv/mand.cgs | 23 + sim/testsuite/sim/frv/masaccs.cgs | 151 + sim/testsuite/sim/frv/maveh.cgs | 72 + sim/testsuite/sim/frv/mbtoh.cgs | 20 + sim/testsuite/sim/frv/mbtohe.cgs | 24 + sim/testsuite/sim/frv/mclracc.cgs | 79 + sim/testsuite/sim/frv/mcmpsh.cgs | 138 + sim/testsuite/sim/frv/mcmpuh.cgs | 138 + sim/testsuite/sim/frv/mcop1.cgs | 40 + sim/testsuite/sim/frv/mcop2.cgs | 40 + sim/testsuite/sim/frv/mcplhi.cgs | 53 + sim/testsuite/sim/frv/mcpli.cgs | 61 + sim/testsuite/sim/frv/mcpxis.cgs | 115 + sim/testsuite/sim/frv/mcpxiu.cgs | 76 + sim/testsuite/sim/frv/mcpxrs.cgs | 115 + sim/testsuite/sim/frv/mcpxru.cgs | 94 + sim/testsuite/sim/frv/mcut.cgs | 509 +++ sim/testsuite/sim/frv/mcuti.cgs | 381 ++ sim/testsuite/sim/frv/mcutss.cgs | 505 +++ sim/testsuite/sim/frv/mcutssi.cgs | 380 ++ sim/testsuite/sim/frv/mdaddaccs.cgs | 102 + sim/testsuite/sim/frv/mdasaccs.cgs | 122 + sim/testsuite/sim/frv/mdcutssi.cgs | 513 +++ sim/testsuite/sim/frv/mdpackh.cgs | 18 + sim/testsuite/sim/frv/mdrotli.cgs | 34 + sim/testsuite/sim/frv/mdsubaccs.cgs | 102 + sim/testsuite/sim/frv/mdunpackh.cgs | 26 + sim/testsuite/sim/frv/membar.cgs | 12 + sim/testsuite/sim/frv/mexpdhd.cgs | 27 + sim/testsuite/sim/frv/mexpdhw.cgs | 23 + sim/testsuite/sim/frv/mhdseth.cgs | 26 + sim/testsuite/sim/frv/mhdsets.cgs | 26 + sim/testsuite/sim/frv/mhsethih.cgs | 26 + sim/testsuite/sim/frv/mhsethis.cgs | 26 + sim/testsuite/sim/frv/mhsetloh.cgs | 26 + sim/testsuite/sim/frv/mhsetlos.cgs | 26 + sim/testsuite/sim/frv/mhtob.cgs | 25 + sim/testsuite/sim/frv/mmachs.cgs | 259 ++ sim/testsuite/sim/frv/mmachu.cgs | 146 + sim/testsuite/sim/frv/mmrdhs.cgs | 263 ++ sim/testsuite/sim/frv/mmrdhu.cgs | 151 + sim/testsuite/sim/frv/mmulhs.cgs | 141 + sim/testsuite/sim/frv/mmulhu.cgs | 82 + sim/testsuite/sim/frv/mmulxhs.cgs | 141 + sim/testsuite/sim/frv/mmulxhu.cgs | 82 + sim/testsuite/sim/frv/mnop.cgs | 12 + sim/testsuite/sim/frv/mnot.cgs | 18 + sim/testsuite/sim/frv/mor.cgs | 25 + sim/testsuite/sim/frv/mov.cgs | 18 + sim/testsuite/sim/frv/movfg.cgs | 16 + sim/testsuite/sim/frv/movfgd.cgs | 20 + sim/testsuite/sim/frv/movfgq.cgs | 29 + sim/testsuite/sim/frv/movgf.cgs | 16 + sim/testsuite/sim/frv/movgfd.cgs | 20 + sim/testsuite/sim/frv/movgfq.cgs | 29 + sim/testsuite/sim/frv/movgs.cgs | 22 + sim/testsuite/sim/frv/movsg.cgs | 16 + sim/testsuite/sim/frv/mpackh.cgs | 15 + sim/testsuite/sim/frv/mqcpxis.cgs | 103 + sim/testsuite/sim/frv/mqcpxiu.cgs | 60 + sim/testsuite/sim/frv/mqcpxrs.cgs | 103 + sim/testsuite/sim/frv/mqcpxru.cgs | 78 + sim/testsuite/sim/frv/mqmachs.cgs | 211 + sim/testsuite/sim/frv/mqmachu.cgs | 144 + sim/testsuite/sim/frv/mqmacxhs.cgs | 211 + sim/testsuite/sim/frv/mqmulhs.cgs | 125 + sim/testsuite/sim/frv/mqmulhu.cgs | 80 + sim/testsuite/sim/frv/mqmulxhs.cgs | 125 + sim/testsuite/sim/frv/mqmulxhu.cgs | 80 + sim/testsuite/sim/frv/mqsaths.cgs | 50 + sim/testsuite/sim/frv/mqxmachs.cgs | 211 + sim/testsuite/sim/frv/mqxmacxhs.cgs | 211 + sim/testsuite/sim/frv/mrdacc.cgs | 26 + sim/testsuite/sim/frv/mrdaccg.cgs | 26 + sim/testsuite/sim/frv/mrotli.cgs | 34 + sim/testsuite/sim/frv/mrotri.cgs | 34 + sim/testsuite/sim/frv/msaths.cgs | 55 + sim/testsuite/sim/frv/msathu.cgs | 55 + sim/testsuite/sim/frv/msllhi.cgs | 30 + sim/testsuite/sim/frv/msrahi.cgs | 30 + sim/testsuite/sim/frv/msrlhi.cgs | 30 + sim/testsuite/sim/frv/msubaccs.cgs | 131 + sim/testsuite/sim/frv/msubhss.cgs | 100 + sim/testsuite/sim/frv/msubhus.cgs | 80 + sim/testsuite/sim/frv/mtrap.cgs | 50 + sim/testsuite/sim/frv/munpackh.cgs | 22 + sim/testsuite/sim/frv/mwcut.cgs | 269 ++ sim/testsuite/sim/frv/mwcuti.cgs | 205 + sim/testsuite/sim/frv/mwtacc.cgs | 23 + sim/testsuite/sim/frv/mwtaccg.cgs | 23 + sim/testsuite/sim/frv/mxor.cgs | 30 + sim/testsuite/sim/frv/nandcr.cgs | 59 + sim/testsuite/sim/frv/nandncr.cgs | 59 + sim/testsuite/sim/frv/nfadds.cgs | 179 + sim/testsuite/sim/frv/nfdadds.cgs | 225 ++ sim/testsuite/sim/frv/nfdcmps.cgs | 1549 +++++++ sim/testsuite/sim/frv/nfddivs.cgs | 306 ++ sim/testsuite/sim/frv/nfditos.cgs | 31 + sim/testsuite/sim/frv/nfdivs.cgs | 234 ++ sim/testsuite/sim/frv/nfdmadds.cgs | 310 ++ sim/testsuite/sim/frv/nfdmas.cgs | 349 ++ sim/testsuite/sim/frv/nfdmss.cgs | 319 ++ sim/testsuite/sim/frv/nfdmulcs.cgs | 313 ++ sim/testsuite/sim/frv/nfdmuls.cgs | 300 ++ sim/testsuite/sim/frv/nfdsads.cgs | 212 + sim/testsuite/sim/frv/nfdsqrts.cgs | 21 + sim/testsuite/sim/frv/nfdstoi.cgs | 29 + sim/testsuite/sim/frv/nfdsubs.cgs | 202 + sim/testsuite/sim/frv/nfitos.cgs | 44 + sim/testsuite/sim/frv/nfmadds.cgs | 227 ++ sim/testsuite/sim/frv/nfmas.cgs | 297 ++ sim/testsuite/sim/frv/nfmss.cgs | 279 ++ sim/testsuite/sim/frv/nfmsubs.cgs | 227 ++ sim/testsuite/sim/frv/nfmuls.cgs | 228 ++ sim/testsuite/sim/frv/nfsqrts.cgs | 35 + sim/testsuite/sim/frv/nfstoi.cgs | 49 + sim/testsuite/sim/frv/nfsubs.cgs | 163 + sim/testsuite/sim/frv/nld.cgs | 42 + sim/testsuite/sim/frv/nldbf.cgs | 42 + sim/testsuite/sim/frv/nldbfi.cgs | 39 + sim/testsuite/sim/frv/nldbfu.cgs | 46 + sim/testsuite/sim/frv/nldd.cgs | 50 + sim/testsuite/sim/frv/nlddf.cgs | 50 + sim/testsuite/sim/frv/nlddfi.cgs | 47 + sim/testsuite/sim/frv/nlddfu.cgs | 53 + sim/testsuite/sim/frv/nlddi.cgs | 47 + sim/testsuite/sim/frv/nlddu.cgs | 66 + sim/testsuite/sim/frv/nldf.cgs | 42 + sim/testsuite/sim/frv/nldfi.cgs | 39 + sim/testsuite/sim/frv/nldfu.cgs | 45 + sim/testsuite/sim/frv/nldhf.cgs | 41 + sim/testsuite/sim/frv/nldhfi.cgs | 38 + sim/testsuite/sim/frv/nldhfu.cgs | 45 + sim/testsuite/sim/frv/nldi.cgs | 39 + sim/testsuite/sim/frv/nldq.cgs | 67 + sim/testsuite/sim/frv/nldqf.cgs | 67 + sim/testsuite/sim/frv/nldqfi.cgs | 64 + sim/testsuite/sim/frv/nldqfu.cgs | 70 + sim/testsuite/sim/frv/nldqi.cgs | 64 + sim/testsuite/sim/frv/nldqu.cgs | 87 + sim/testsuite/sim/frv/nldsb.cgs | 42 + sim/testsuite/sim/frv/nldsbi.cgs | 39 + sim/testsuite/sim/frv/nldsbu.cgs | 56 + sim/testsuite/sim/frv/nldsh.cgs | 41 + sim/testsuite/sim/frv/nldshi.cgs | 38 + sim/testsuite/sim/frv/nldshu.cgs | 55 + sim/testsuite/sim/frv/nldu.cgs | 55 + sim/testsuite/sim/frv/nldub.cgs | 42 + sim/testsuite/sim/frv/nldubi.cgs | 39 + sim/testsuite/sim/frv/nldubu.cgs | 55 + sim/testsuite/sim/frv/nlduh.cgs | 41 + sim/testsuite/sim/frv/nlduhi.cgs | 38 + sim/testsuite/sim/frv/nlduhu.cgs | 55 + sim/testsuite/sim/frv/nop.cgs | 12 + sim/testsuite/sim/frv/norcr.cgs | 59 + sim/testsuite/sim/frv/norncr.cgs | 59 + sim/testsuite/sim/frv/not.cgs | 18 + sim/testsuite/sim/frv/notcr.cgs | 23 + sim/testsuite/sim/frv/nsdiv.cgs | 64 + sim/testsuite/sim/frv/nsdivi.cgs | 64 + sim/testsuite/sim/frv/nudiv.cgs | 49 + sim/testsuite/sim/frv/nudivi.cgs | 51 + sim/testsuite/sim/frv/or.cgs | 31 + sim/testsuite/sim/frv/orcc.cgs | 31 + sim/testsuite/sim/frv/orcr.cgs | 59 + sim/testsuite/sim/frv/ori.cgs | 34 + sim/testsuite/sim/frv/oricc.cgs | 34 + sim/testsuite/sim/frv/orncr.cgs | 59 + sim/testsuite/sim/frv/parallel.exp | 19 + sim/testsuite/sim/frv/ret.cgs | 91 + sim/testsuite/sim/frv/rett.cgs | 30 + sim/testsuite/sim/frv/rst.cgs | 107 + sim/testsuite/sim/frv/rstb.cgs | 72 + sim/testsuite/sim/frv/rstbf.cgs | 76 + sim/testsuite/sim/frv/rstd.cgs | 171 + sim/testsuite/sim/frv/rstdf.cgs | 186 + sim/testsuite/sim/frv/rstf.cgs | 112 + sim/testsuite/sim/frv/rsth.cgs | 83 + sim/testsuite/sim/frv/rsthf.cgs | 87 + sim/testsuite/sim/frv/rstq.cgs | 297 ++ sim/testsuite/sim/frv/rstqf.cgs | 332 ++ sim/testsuite/sim/frv/scan.cgs | 73 + sim/testsuite/sim/frv/scani.cgs | 55 + sim/testsuite/sim/frv/sdiv.cgs | 75 + sim/testsuite/sim/frv/sdivi.cgs | 74 + sim/testsuite/sim/frv/sethi.cgs | 18 + sim/testsuite/sim/frv/sethilo.pcgs | 18 + sim/testsuite/sim/frv/setlo.cgs | 18 + sim/testsuite/sim/frv/setlos.cgs | 21 + sim/testsuite/sim/frv/sll.cgs | 38 + sim/testsuite/sim/frv/sllcc.cgs | 38 + sim/testsuite/sim/frv/slli.cgs | 34 + sim/testsuite/sim/frv/sllicc.cgs | 34 + sim/testsuite/sim/frv/smul.cgs | 182 + sim/testsuite/sim/frv/smulcc.cgs | 238 ++ sim/testsuite/sim/frv/smuli.cgs | 210 + sim/testsuite/sim/frv/smulicc.cgs | 210 + sim/testsuite/sim/frv/sra.cgs | 38 + sim/testsuite/sim/frv/sracc.cgs | 38 + sim/testsuite/sim/frv/srai.cgs | 34 + sim/testsuite/sim/frv/sraicc.cgs | 34 + sim/testsuite/sim/frv/srl.cgs | 38 + sim/testsuite/sim/frv/srlcc.cgs | 38 + sim/testsuite/sim/frv/srli.cgs | 34 + sim/testsuite/sim/frv/srlicc.cgs | 34 + sim/testsuite/sim/frv/st.cgs | 16 + sim/testsuite/sim/frv/stb.cgs | 16 + sim/testsuite/sim/frv/stbf.cgs | 16 + sim/testsuite/sim/frv/stbfi.cgs | 24 + sim/testsuite/sim/frv/stbfu.cgs | 19 + sim/testsuite/sim/frv/stbi.cgs | 24 + sim/testsuite/sim/frv/stbu.cgs | 19 + sim/testsuite/sim/frv/stc.cgs | 17 + sim/testsuite/sim/frv/stcu.cgs | 33 + sim/testsuite/sim/frv/std.cgs | 32 + sim/testsuite/sim/frv/std.pcgs | 37 + sim/testsuite/sim/frv/stdc.cgs | 21 + sim/testsuite/sim/frv/stdc.pcgs | 38 + sim/testsuite/sim/frv/stdcu.cgs | 44 + sim/testsuite/sim/frv/stdf.cgs | 21 + sim/testsuite/sim/frv/stdf.pcgs | 37 + sim/testsuite/sim/frv/stdfi.cgs | 56 + sim/testsuite/sim/frv/stdfu.cgs | 24 + sim/testsuite/sim/frv/stdi.cgs | 56 + sim/testsuite/sim/frv/stdu.cgs | 24 + sim/testsuite/sim/frv/stf.cgs | 16 + sim/testsuite/sim/frv/stfi.cgs | 37 + sim/testsuite/sim/frv/stfu.cgs | 19 + sim/testsuite/sim/frv/sth.cgs | 16 + sim/testsuite/sim/frv/sthf.cgs | 16 + sim/testsuite/sim/frv/sthfi.cgs | 31 + sim/testsuite/sim/frv/sthfu.cgs | 19 + sim/testsuite/sim/frv/sthi.cgs | 31 + sim/testsuite/sim/frv/sthu.cgs | 19 + sim/testsuite/sim/frv/sti.cgs | 37 + sim/testsuite/sim/frv/stq.cgs | 53 + sim/testsuite/sim/frv/stq.pcgs | 59 + sim/testsuite/sim/frv/stqc.cgs | 32 + sim/testsuite/sim/frv/stqc.pcgs | 60 + sim/testsuite/sim/frv/stqcu.cgs | 66 + sim/testsuite/sim/frv/stqf.cgs | 32 + sim/testsuite/sim/frv/stqf.pcgs | 59 + sim/testsuite/sim/frv/stqfi.cgs | 95 + sim/testsuite/sim/frv/stqfu.cgs | 35 + sim/testsuite/sim/frv/stqi.cgs | 95 + sim/testsuite/sim/frv/stqu.cgs | 35 + sim/testsuite/sim/frv/stu.cgs | 19 + sim/testsuite/sim/frv/sub.cgs | 26 + sim/testsuite/sim/frv/subcc.cgs | 34 + sim/testsuite/sim/frv/subi.cgs | 56 + sim/testsuite/sim/frv/subicc.cgs | 56 + sim/testsuite/sim/frv/subx.cgs | 60 + sim/testsuite/sim/frv/subxcc.cgs | 60 + sim/testsuite/sim/frv/subxi.cgs | 61 + sim/testsuite/sim/frv/subxicc.cgs | 61 + sim/testsuite/sim/frv/swap.cgs | 42 + sim/testsuite/sim/frv/swapi.cgs | 39 + sim/testsuite/sim/frv/tc.cgs | 101 + sim/testsuite/sim/frv/teq.cgs | 101 + sim/testsuite/sim/frv/testutils.inc | 646 +++ sim/testsuite/sim/frv/tge.cgs | 101 + sim/testsuite/sim/frv/tgt.cgs | 93 + sim/testsuite/sim/frv/thi.cgs | 93 + sim/testsuite/sim/frv/tic.cgs | 100 + sim/testsuite/sim/frv/tieq.cgs | 101 + sim/testsuite/sim/frv/tige.cgs | 101 + sim/testsuite/sim/frv/tigt.cgs | 92 + sim/testsuite/sim/frv/tihi.cgs | 92 + sim/testsuite/sim/frv/tile.cgs | 108 + sim/testsuite/sim/frv/tils.cgs | 108 + sim/testsuite/sim/frv/tilt.cgs | 100 + sim/testsuite/sim/frv/tin.cgs | 100 + sim/testsuite/sim/frv/tinc.cgs | 100 + sim/testsuite/sim/frv/tine.cgs | 100 + sim/testsuite/sim/frv/tino.cgs | 53 + sim/testsuite/sim/frv/tinv.cgs | 100 + sim/testsuite/sim/frv/tip.cgs | 100 + sim/testsuite/sim/frv/tira.cgs | 114 + sim/testsuite/sim/frv/tiv.cgs | 100 + sim/testsuite/sim/frv/tle.cgs | 109 + sim/testsuite/sim/frv/tls.cgs | 109 + sim/testsuite/sim/frv/tlt.cgs | 101 + sim/testsuite/sim/frv/tn.cgs | 101 + sim/testsuite/sim/frv/tnc.cgs | 101 + sim/testsuite/sim/frv/tne.cgs | 101 + sim/testsuite/sim/frv/tno.cgs | 54 + sim/testsuite/sim/frv/tnv.cgs | 101 + sim/testsuite/sim/frv/tp.cgs | 101 + sim/testsuite/sim/frv/tra.cgs | 117 + sim/testsuite/sim/frv/tv.cgs | 101 + sim/testsuite/sim/frv/udiv.cgs | 48 + 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100644 sim/testsuite/sim/frv/tno.cgs create mode 100644 sim/testsuite/sim/frv/tnv.cgs create mode 100644 sim/testsuite/sim/frv/tp.cgs create mode 100644 sim/testsuite/sim/frv/tra.cgs create mode 100644 sim/testsuite/sim/frv/tv.cgs create mode 100644 sim/testsuite/sim/frv/udiv.cgs create mode 100644 sim/testsuite/sim/frv/udivi.cgs create mode 100644 sim/testsuite/sim/frv/umul.cgs create mode 100644 sim/testsuite/sim/frv/umulcc.cgs create mode 100644 sim/testsuite/sim/frv/umuli.cgs create mode 100644 sim/testsuite/sim/frv/umulicc.cgs create mode 100644 sim/testsuite/sim/frv/xor.cgs create mode 100644 sim/testsuite/sim/frv/xorcc.cgs create mode 100644 sim/testsuite/sim/frv/xorcr.cgs create mode 100644 sim/testsuite/sim/frv/xori.cgs create mode 100644 sim/testsuite/sim/frv/xoricc.cgs diff --git a/sim/testsuite/frv-elf/ChangeLog b/sim/testsuite/frv-elf/ChangeLog new file mode 100644 index 00000000000..5d6b82c3211 --- /dev/null +++ b/sim/testsuite/frv-elf/ChangeLog @@ -0,0 +1,34 @@ +2000-07-26 Dave Brolley + + * Makefile.in (TESTS): Don't run cache.ok + * cache.s: Use softune syntax for jmpl. + +2000-07-19 Dave Brolley + + * cache.s (pass): Use softune syntax for tira. + * exit47.s (pass): Use softune syntax for tira. + * grloop.s (pass): Use softune syntax for tira. + * hello.s (pass): Use softune syntax for tira. + +Thu Aug 19 18:00:16 1999 Dave Brolley + + * hello.s: Fix sethi, setlo insn usage. + +Mon Jun 21 17:33:37 1999 Dave Brolley + + * Makefile.in (TESTS): Add grloop.ok. + * grloop.s: New testcase. + +Fri Jun 18 17:55:02 1999 Dave Brolley + + * exit47.s: Use proper syscalls interface. + * hello.s: Use proper syscalls interface. + +Mon May 31 12:03:38 1999 Dave Brolley + + * hello.s,loop.s,exit47.s: Convert to frv insn set. + +Thu May 6 16:36:30 1999 Dave Brolley + + * Directory created. + diff --git a/sim/testsuite/frv-elf/Makefile.in b/sim/testsuite/frv-elf/Makefile.in new file mode 100644 index 00000000000..795bdd1aed1 --- /dev/null +++ b/sim/testsuite/frv-elf/Makefile.in @@ -0,0 +1,159 @@ +# Makefile for regression testing the frv simulator. +# Copyright (C) 1998 Free Software Foundation, Inc. + +# This file is part of GDB. + +# GDB is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# GDB is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +VPATH = @srcdir@ +srcdir = @srcdir@ +srcroot = $(srcdir)/../../.. + +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +host_alias = @host_alias@ +target_alias = @target_alias@ +program_transform_name = @program_transform_name@ +build_canonical = @build@ +host_canonical = @host@ +target_canonical = @target@ +target_cpu = @target_cpu@ + + +SHELL = @SHELL@ +SUBDIRS = @subdirs@ +RPATH_ENVVAR = @RPATH_ENVVAR@ + +EXPECT = `if [ -f ../../../expect/expect ] ; then \ + echo ../../../expect/expect ; \ + else echo expect ; fi` + +RUNTEST = $(RUNTEST_FOR_TARGET) + +RUNTESTFLAGS = + +RUNTEST_FOR_TARGET = `\ + if [ -f $${srcroot}/dejagnu/runtest ]; then \ + echo $${srcroot}/dejagnu/runtest; \ + else \ + if [ "$(host_canonical)" = "$(target_canonical)" ]; then \ + echo runtest; \ + else \ + t='$(program_transform_name)'; echo runtest | sed -e '' $$t; \ + fi; \ + fi` + + +AS_FOR_TARGET = `\ + if [ -x ../../../gas/as-new ]; then \ + echo ../../../gas/as-new ; \ + else \ + echo $(target_alias)-as ; \ + fi` + +LD_FOR_TARGET = `\ + if [ -x ../../../ld/ld-new ]; then \ + echo ../../../ld/ld-new ; \ + else \ + echo $(target_alias)-ld ; \ + fi` + +RUN_FOR_TARGET = `\ + if [ -x ../../../sim/${target_cpu}/run ]; then \ + echo ../../../sim/${target_cpu}/run ; \ + else \ + echo $(target_alias)-run ; \ + fi` + +TESTS = \ + exit47.ko \ + grloop.ok \ + hello.ok + + +check: sanity $(TESTS) +sanity: + @eval echo AS_FOR_TARGET = $(AS_FOR_TARGET) + @eval echo LD_FOR_TARGET = $(LD_FOR_TARGET) + @eval echo RUN_FOR_TARGET = $(RUN_FOR_TARGET) + + + +# Rules for running all the tests, put into three types +# exit success, exit fail, print "Hello World" + +.u.log: + uudecode $*.u + $(RUN_FOR_TARGET) $* > $*.log + + +# Rules for running the tests + +.SUFFIXES: .u .ok .run .hi .ko +.run.ok: + rm -f tmp-$* $*.hi + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* + mv tmp-$* $*.ok +.run.hi: + rm -f tmp-$* $*.hi diff-$* + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* + echo "Hello World" | diff - tmp-$* > diff-$* + cat tmp-$* diff-$* > $*.hi +.run.ko: + rm -f tmp-$* $*.ko + set +e ; \ + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* ; \ + if [ $$? -eq 47 ] ; then \ + exit 0 ; \ + else \ + exit 1 ; \ + fi + mv tmp-$* $*.ko + + +# Rules for building all the tests and packing them into +# uuencoded files. + +uuencode: em-pstr.u em-e0.u em-e47.u em-pchr.u + +.SUFFIXES: .u .s .run +.s.u: + rm -f $*.o $*.run + $(AS_FOR_TARGET) $(srcdir)/$*.s -o $*.o + $(LD_FOR_TARGET) -o $* $*.o + uuencode < $* $* > $*.u + rm -f $*.o $* +.s.run: + rm -f $*.o $*.run + $(AS_FOR_TARGET) $(srcdir)/$*.s -o $*.o + $(LD_FOR_TARGET) -o $*.run $*.o + rm -f $*.o $* + + +clean mostlyclean: + rm -f *~ core *.o a.out + rm -f $(TESTS) + +distclean maintainer-clean realclean: clean + rm -f *~ core + rm -f Makefile config.status *-init.exp + rm -fr *.log summary detail *.plog *.sum *.psum site.* + +Makefile : Makefile.in config.status + $(SHELL) config.status + +config.status: configure + $(SHELL) config.status --recheck diff --git a/sim/testsuite/frv-elf/cache.s b/sim/testsuite/frv-elf/cache.s new file mode 100644 index 00000000000..2ed0e1e35a9 --- /dev/null +++ b/sim/testsuite/frv-elf/cache.s @@ -0,0 +1,164 @@ +# run with --memory-region 0xff000000,4 --memory-region 0xfe000000,00404000 +; Exit with return code + .macro exit rc + setlos.p #1,gr7 + setlos \rc,gr8 + tira gr0,#0 + .endm + +; Pass the test case + .macro pass +pass: + setlos.p #5,gr10 + setlos #1,gr8 + setlos #5,gr7 + sethi.p %hi(passmsg),gr9 + setlo %lo(passmsg),gr9 + tira gr0,#0 + exit #0 + .endm + +; Fail the testcase + .macro fail +fail\@: + setlos.p #5,gr10 + setlos #1,gr8 + setlos #5,gr7 + sethi.p %hi(failmsg),gr9 + setlo %lo(failmsg),gr9 + tira gr0,#0 + exit #1 + .endm + + .data +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + + .text + .global _start +_start: + movsg hsr0,gr10 ; enable insn and data caches + sethi.p 0xc800,gr11 ; in copy-back mode + setlo 0x0000,gr11 + or gr10,gr11,gr10 + movgs gr10,hsr0 + + sethi.p 0x7,sp + setlo 0x0000,sp + + ; fill the cache + sethi.p %hi(done1),gr10 + setlo %lo(done1),gr10 + movgs gr10,lr + setlos.p 0x1000,gr10 + setlos 0x0,gr11 + movgs gr10,lcr +write1: st.p gr11,@(sp,gr11) + addi.p gr11,4,gr11 + bctrlr.p 1,0 + bra write1 +done1: + ; read it back + sethi.p %hi(done2),gr10 + setlo %lo(done2),gr10 + movgs gr10,lr + setlos.p 0x1000,gr10 + setlos 0x0,gr11 + movgs gr10,lcr +read1: ld @(sp,gr11),gr12 + cmp gr11,gr12,icc0 + bne icc0,1,fail + addi.p gr11,4,gr11 + bctrlr.p 1,0 + bra read1 +done2: + + ; fill the cache twice + sethi.p %hi(done3),gr10 + setlo %lo(done3),gr10 + movgs gr10,lr + setlos.p 0x2000,gr10 + setlos 0x0,gr11 + movgs gr10,lcr +write3: st.p gr11,@(sp,gr11) + addi.p gr11,4,gr11 + bctrlr.p 1,0 + bra write3 +done3: + ; read it back + sethi.p %hi(done4),gr10 + setlo %lo(done4),gr10 + movgs gr10,lr + setlos.p 0x2000,gr10 + setlos 0x0,gr11 + movgs gr10,lcr +read4: ld @(sp,gr11),gr12 + cmp gr11,gr12,icc0 + bne icc0,1,fail + addi.p gr11,4,gr11 + bctrlr.p 1,0 + bra read4 +done4: + ; read it back in reverse + sethi.p %hi(done5),gr10 + setlo %lo(done5),gr10 + movgs gr10,lr + setlos.p 0x2000,gr10 + setlos 0x7ffc,gr11 + movgs gr10,lcr +read5: ld @(sp,gr11),gr12 + cmp gr11,gr12,icc0 + bne icc0,1,fail + subi.p gr11,4,gr11 + bctrlr.p 1,0 + bra read5 +done5: + + ; access data and insns in non-cache areas + sethi.p 0x8038,gr11 ; bctrlr 0,0 + setlo 0x2000,gr11 + + sethi.p 0xff00,gr10 ; documented area + setlo 0x0000,gr10 + sti gr11,@(gr10,0) + jmpl @(gr10,gr0) + + ; enable RAM mode + movsg hsr0,gr10 + sethi.p 0x0040,gr12 + setlo 0x0000,gr12 + or gr10,gr12,gr10 + movgs gr10,hsr0 + + sethi.p 0xfe00,gr10 ; documented area + setlo 0x0400,gr10 + sti gr11,@(gr10,0) + jmpl @(gr10,gr0) + + sethi.p 0xfe40,gr10 ; documented area + setlo 0x0400,gr10 + sti gr11,@(gr10,0) + dcf @(gr10,gr0) + jmpl @(gr10,gr0) + + sethi.p 0x0007,gr10 ; non RAM area + setlo 0x0000,gr10 + sti gr11,@(gr10,0) + jmpl @(gr10,gr0) + + sethi.p 0xfe00,gr10 ; insn RAM area + setlo 0x0000,gr10 + sti gr11,@(gr10,0) + jmpl @(gr10,gr0) + + sethi.p 0xfe40,gr10 ; data RAM area + setlo 0x0000,gr10 + sti gr11,@(gr10,0) + dcf @(gr10,gr0) + jmpl @(gr10,gr0) + + pass +fail: + fail diff --git a/sim/testsuite/frv-elf/configure b/sim/testsuite/frv-elf/configure new file mode 100755 index 00000000000..25c27936dcb --- /dev/null +++ b/sim/testsuite/frv-elf/configure @@ -0,0 +1,905 @@ +#! /bin/sh + +# Guess values for system-dependent variables and create Makefiles. +# Generated automatically using autoconf version 2.13 +# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. + +# Defaults: +ac_help= +ac_default_prefix=/usr/local +# Any additions from configure.in: + +# Initialize some variables set by options. +# The variables have the same names as the options, with +# dashes changed to underlines. +build=NONE +cache_file=./config.cache +exec_prefix=NONE +host=NONE +no_create= +nonopt=NONE +no_recursion= +prefix=NONE +program_prefix=NONE +program_suffix=NONE +program_transform_name=s,x,x, +silent= +site= +srcdir= +target=NONE +verbose= +x_includes=NONE +x_libraries=NONE +bindir='${exec_prefix}/bin' +sbindir='${exec_prefix}/sbin' +libexecdir='${exec_prefix}/libexec' +datadir='${prefix}/share' +sysconfdir='${prefix}/etc' +sharedstatedir='${prefix}/com' +localstatedir='${prefix}/var' +libdir='${exec_prefix}/lib' +includedir='${prefix}/include' +oldincludedir='/usr/include' +infodir='${prefix}/info' +mandir='${prefix}/man' + +# Initialize some other variables. +subdirs= +MFLAGS= MAKEFLAGS= +SHELL=${CONFIG_SHELL-/bin/sh} +# Maximum number of lines to put in a shell here document. +ac_max_here_lines=12 + +ac_prev= +for ac_option +do + + # If the previous option needs an argument, assign it. + if test -n "$ac_prev"; then + eval "$ac_prev=\$ac_option" + ac_prev= + continue + fi + + case "$ac_option" in + -*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;; + *) ac_optarg= ;; + esac + + # Accept the important Cygnus configure options, so we can diagnose typos. + + case "$ac_option" in + + -bindir | --bindir | --bindi | --bind | --bin | --bi) + ac_prev=bindir ;; + -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*) + bindir="$ac_optarg" ;; + + -build | --build | --buil | --bui | --bu) + ac_prev=build ;; + -build=* | --build=* | --buil=* | --bui=* | --bu=*) + build="$ac_optarg" ;; + + -cache-file | --cache-file | --cache-fil | --cache-fi \ + | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c) + ac_prev=cache_file ;; + -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \ + | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*) + cache_file="$ac_optarg" ;; + + -datadir | --datadir | --datadi | --datad | --data | --dat | --da) + ac_prev=datadir ;; + -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \ + | --da=*) + datadir="$ac_optarg" ;; + + -disable-* | --disable-*) + ac_feature=`echo $ac_option|sed -e 's/-*disable-//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_feature| sed 's/[-a-zA-Z0-9_]//g'`"; then + { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; } + fi + ac_feature=`echo $ac_feature| sed 's/-/_/g'` + eval "enable_${ac_feature}=no" ;; + + -enable-* | --enable-*) + ac_feature=`echo $ac_option|sed -e 's/-*enable-//' -e 's/=.*//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_feature| sed 's/[-_a-zA-Z0-9]//g'`"; then + { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; } + fi + ac_feature=`echo $ac_feature| sed 's/-/_/g'` + case "$ac_option" in + *=*) ;; + *) ac_optarg=yes ;; + esac + eval "enable_${ac_feature}='$ac_optarg'" ;; + + -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \ + | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \ + | --exec | --exe | --ex) + ac_prev=exec_prefix ;; + -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \ + | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \ + | --exec=* | --exe=* | --ex=*) + exec_prefix="$ac_optarg" ;; + + -gas | --gas | --ga | --g) + # Obsolete; use --with-gas. + with_gas=yes ;; + + -help | --help | --hel | --he) + # Omit some internal or obsolete options to make the list less imposing. + # This message is too long to be a string in the A/UX 3.1 sh. + cat << EOF +Usage: configure [options] [host] +Options: [defaults in brackets after descriptions] +Configuration: + --cache-file=FILE cache test results in FILE + --help print this message + --no-create do not create output files + --quiet, --silent do not print \`checking...' messages + --version print the version of autoconf that created configure +Directory and file names: + --prefix=PREFIX install architecture-independent files in PREFIX + [$ac_default_prefix] + --exec-prefix=EPREFIX install architecture-dependent files in EPREFIX + [same as prefix] + --bindir=DIR user executables in DIR [EPREFIX/bin] + --sbindir=DIR system admin executables in DIR [EPREFIX/sbin] + --libexecdir=DIR program executables in DIR [EPREFIX/libexec] + --datadir=DIR read-only architecture-independent data in DIR + [PREFIX/share] + --sysconfdir=DIR read-only single-machine data in DIR [PREFIX/etc] + --sharedstatedir=DIR modifiable architecture-independent data in DIR + [PREFIX/com] + --localstatedir=DIR modifiable single-machine data in DIR [PREFIX/var] + --libdir=DIR object code libraries in DIR [EPREFIX/lib] + --includedir=DIR C header files in DIR [PREFIX/include] + --oldincludedir=DIR C header files for non-gcc in DIR [/usr/include] + --infodir=DIR info documentation in DIR [PREFIX/info] + --mandir=DIR man documentation in DIR [PREFIX/man] + --srcdir=DIR find the sources in DIR [configure dir or ..] + --program-prefix=PREFIX prepend PREFIX to installed program names + --program-suffix=SUFFIX append SUFFIX to installed program names + --program-transform-name=PROGRAM + run sed PROGRAM on installed program names +EOF + cat << EOF +Host type: + --build=BUILD configure for building on BUILD [BUILD=HOST] + --host=HOST configure for HOST [guessed] + --target=TARGET configure for TARGET [TARGET=HOST] +Features and packages: + --disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no) + --enable-FEATURE[=ARG] include FEATURE [ARG=yes] + --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] + --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no) + --x-includes=DIR X include files are in DIR + --x-libraries=DIR X library files are in DIR +EOF + if test -n "$ac_help"; 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then + echo "configure: warning: $ac_option: invalid host type" 1>&2 + fi + if test "x$nonopt" != xNONE; then + { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } + fi + nonopt="$ac_option" + ;; + + esac +done + +if test -n "$ac_prev"; then + { echo "configure: error: missing argument to --`echo $ac_prev | sed 's/_/-/g'`" 1>&2; exit 1; } +fi + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +# File descriptor usage: +# 0 standard input +# 1 file creation +# 2 errors and warnings +# 3 some systems may open it to /dev/tty +# 4 used on the Kubota Titan +# 6 checking for... messages and results +# 5 compiler messages saved in config.log +if test "$silent" = yes; then + exec 6>/dev/null +else + exec 6>&1 +fi +exec 5>./config.log + +echo "\ +This file contains any messages produced by compilers while +running configure, to aid debugging if configure makes a mistake. +" 1>&5 + +# Strip out --no-create and --no-recursion so they do not pile up. +# Also quote any args containing shell metacharacters. +ac_configure_args= +for ac_arg +do + case "$ac_arg" in + -no-create | --no-create | --no-creat | --no-crea | --no-cre \ + | --no-cr | --no-c) ;; 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You are not allowed to specify --host, --target, and nonopt at the +# same time. +# 2. Host defaults to nonopt. +# 3. If nonopt is not specified, then host defaults to the current host, +# as determined by config.guess. +# 4. Target and build default to nonopt. +# 5. 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It is not useful on other systems. +# If it contains results you don't want to keep, you may remove or edit it. +# +# By default, configure uses ./config.cache as the cache file, +# creating it if it does not exist already. You can give configure +# the --cache-file=FILE option to use a different cache file; that is +# what configure does when it calls configure scripts in +# subdirectories, so they share the cache. +# Giving --cache-file=/dev/null disables caching, for debugging configure. +# config.status only pays attention to the cache file if you give it the +# --recheck option to rerun configure. +# +EOF +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, don't put newlines in cache variables' values. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +(set) 2>&1 | + case `(ac_space=' '; set | grep ac_space) 2>&1` in + *ac_space=\ *) + # `set' does not quote correctly, so add quotes (double-quote substitution + # turns \\\\ into \\, and sed turns \\ into \). + sed -n \ + -e "s/'/'\\\\''/g" \ + -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p" + ;; + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p' + ;; + esac >> confcache +if cmp -s $cache_file confcache; then + : +else + if test -w $cache_file; then + echo "updating cache $cache_file" + cat confcache > $cache_file + else + echo "not updating unwritable cache $cache_file" + fi +fi +rm -f confcache + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +# Any assignment to VPATH causes Sun make to only execute +# the first set of double-colon rules, so remove it if not needed. +# If there is a colon in the path, we need to keep it. +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d' +fi + +trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15 + +# Transform confdefs.h into DEFS. +# Protect against shell expansion while executing Makefile rules. +# Protect against Makefile macro expansion. +cat > conftest.defs <<\EOF +s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%-D\1=\2%g +s%[ `~#$^&*(){}\\|;'"<>?]%\\&%g +s%\[%\\&%g +s%\]%\\&%g +s%\$%$$%g +EOF +DEFS=`sed -f conftest.defs confdefs.h | tr '\012' ' '` +rm -f conftest.defs + + +# Without the "./", some shells look in PATH for config.status. +: ${CONFIG_STATUS=./config.status} + +echo creating $CONFIG_STATUS +rm -f $CONFIG_STATUS +cat > $CONFIG_STATUS </dev/null | sed 1q`: +# +# $0 $ac_configure_args +# +# Compiler output produced by configure, useful for debugging +# configure, is in ./config.log if it exists. + +ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]" +for ac_option +do + case "\$ac_option" in + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" + exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; + -version | --version | --versio | --versi | --vers | --ver | --ve | --v) + echo "$CONFIG_STATUS generated by autoconf version 2.13" + exit 0 ;; + -help | --help | --hel | --he | --h) + echo "\$ac_cs_usage"; exit 0 ;; + *) echo "\$ac_cs_usage"; exit 1 ;; + esac +done + +ac_given_srcdir=$srcdir + +trap 'rm -fr `echo "Makefile" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15 +EOF +cat >> $CONFIG_STATUS < conftest.subs <<\\CEOF +$ac_vpsub +$extrasub +s%@SHELL@%$SHELL%g +s%@CFLAGS@%$CFLAGS%g +s%@CPPFLAGS@%$CPPFLAGS%g +s%@CXXFLAGS@%$CXXFLAGS%g +s%@FFLAGS@%$FFLAGS%g +s%@DEFS@%$DEFS%g +s%@LDFLAGS@%$LDFLAGS%g +s%@LIBS@%$LIBS%g +s%@exec_prefix@%$exec_prefix%g +s%@prefix@%$prefix%g +s%@program_transform_name@%$program_transform_name%g +s%@bindir@%$bindir%g +s%@sbindir@%$sbindir%g +s%@libexecdir@%$libexecdir%g +s%@datadir@%$datadir%g +s%@sysconfdir@%$sysconfdir%g +s%@sharedstatedir@%$sharedstatedir%g +s%@localstatedir@%$localstatedir%g +s%@libdir@%$libdir%g +s%@includedir@%$includedir%g +s%@oldincludedir@%$oldincludedir%g +s%@infodir@%$infodir%g +s%@mandir@%$mandir%g +s%@CC@%$CC%g +s%@host@%$host%g +s%@host_alias@%$host_alias%g +s%@host_cpu@%$host_cpu%g +s%@host_vendor@%$host_vendor%g +s%@host_os@%$host_os%g +s%@target@%$target%g +s%@target_alias@%$target_alias%g +s%@target_cpu@%$target_cpu%g +s%@target_vendor@%$target_vendor%g +s%@target_os@%$target_os%g +s%@build@%$build%g +s%@build_alias@%$build_alias%g +s%@build_cpu@%$build_cpu%g +s%@build_vendor@%$build_vendor%g +s%@build_os@%$build_os%g + +CEOF +EOF + +cat >> $CONFIG_STATUS <<\EOF + +# Split the substitutions into bite-sized pieces for seds with +# small command number limits, like on Digital OSF/1 and HP-UX. +ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script. +ac_file=1 # Number of current file. +ac_beg=1 # First line for current file. +ac_end=$ac_max_sed_cmds # Line after last line for current file. +ac_more_lines=: +ac_sed_cmds="" +while $ac_more_lines; do + if test $ac_beg -gt 1; then + sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file + else + sed "${ac_end}q" conftest.subs > conftest.s$ac_file + fi + if test ! -s conftest.s$ac_file; then + ac_more_lines=false + rm -f conftest.s$ac_file + else + if test -z "$ac_sed_cmds"; then + ac_sed_cmds="sed -f conftest.s$ac_file" + else + ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file" + fi + ac_file=`expr $ac_file + 1` + ac_beg=$ac_end + ac_end=`expr $ac_end + $ac_max_sed_cmds` + fi +done +if test -z "$ac_sed_cmds"; then + ac_sed_cmds=cat +fi +EOF + +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories. + + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`" + # A "../" for each directory in $ac_dir_suffix. + ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'` + else + ac_dir_suffix= ac_dots= + fi + + case "$ac_given_srcdir" in + .) srcdir=. + if test -z "$ac_dots"; then top_srcdir=. + else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;; + /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;; + *) # Relative path. + srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix" + top_srcdir="$ac_dots$ac_given_srcdir" ;; + esac + + + echo creating "$ac_file" + rm -f "$ac_file" + configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure." + case "$ac_file" in + *Makefile*) ac_comsub="1i\\ +# $configure_input" ;; + *) ac_comsub= ;; + esac + + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + sed -e "$ac_comsub +s%@configure_input@%$configure_input%g +s%@srcdir@%$srcdir%g +s%@top_srcdir@%$top_srcdir%g +" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file +fi; done +rm -f conftest.s* + +EOF +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF + +exit 0 +EOF +chmod +x $CONFIG_STATUS +rm -fr confdefs* $ac_clean_files +test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1 + diff --git a/sim/testsuite/frv-elf/configure.in b/sim/testsuite/frv-elf/configure.in new file mode 100644 index 00000000000..e74389e551e --- /dev/null +++ b/sim/testsuite/frv-elf/configure.in @@ -0,0 +1,19 @@ +dnl Process this file file with autoconf to produce a configure script. +dnl This file is a shell script fragment that supplies the information +dnl necessary to tailor a template configure script into the configure +dnl script appropriate for this directory. For more information, check +dnl any existing configure script. + +AC_PREREQ(2.5) +dnl FIXME - think of a truly uniq file to this directory +AC_INIT(Makefile.in) + +CC=${CC-cc} +AC_SUBST(CC) +AC_CONFIG_AUX_DIR(`cd $srcdir;pwd`/../../..) +AC_CANONICAL_SYSTEM + +AC_SUBST(target_cpu) + + +AC_OUTPUT(Makefile) diff --git a/sim/testsuite/frv-elf/exit47.s b/sim/testsuite/frv-elf/exit47.s new file mode 100644 index 00000000000..70e56b3c4ab --- /dev/null +++ b/sim/testsuite/frv-elf/exit47.s @@ -0,0 +1,5 @@ + .global _start +_start: + setlos #47,gr8 + setlos #1,gr7 + tira gr0,#0 diff --git a/sim/testsuite/frv-elf/grloop.s b/sim/testsuite/frv-elf/grloop.s new file mode 100644 index 00000000000..844ad1d2941 --- /dev/null +++ b/sim/testsuite/frv-elf/grloop.s @@ -0,0 +1,10 @@ + .global _start +_start: + setlo 0x0400,gr10 +loop: + addicc gr10,-1,gr10,icc0 + bne icc0,0,loop +; exit (0) + setlos #0,gr8 + setlos #1,gr7 + tira gr0,#0 diff --git a/sim/testsuite/frv-elf/hello.s b/sim/testsuite/frv-elf/hello.s new file mode 100644 index 00000000000..0151febc02f --- /dev/null +++ b/sim/testsuite/frv-elf/hello.s @@ -0,0 +1,16 @@ + .global _start +_start: + +; write (hello world) + setlos #14,gr10 + sethi %hi(hello),gr9 + setlo %lo(hello),gr9 + setlos #1,gr8 + setlos #5,gr7 + tira gr0,#0 +; exit (0) + setlos #0,gr8 + setlos #1,gr7 + tira gr0,#0 + +hello: .ascii "Hello World!\r\n" diff --git a/sim/testsuite/frv-elf/loop.s b/sim/testsuite/frv-elf/loop.s new file mode 100644 index 00000000000..8489c13c569 --- /dev/null +++ b/sim/testsuite/frv-elf/loop.s @@ -0,0 +1,2 @@ + .global _start +_start: bra icc0,0,_start diff --git a/sim/testsuite/sim/frv/add.cgs b/sim/testsuite/sim/frv/add.cgs new file mode 100644 index 00000000000..54fdfd5daa4 --- /dev/null +++ b/sim/testsuite/sim/frv/add.cgs @@ -0,0 +1,23 @@ +# frv testcase for add $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + add gr7,gr8,gr8 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + add gr7,gr8,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + + add gr8,gr8,gr8 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/add.pcgs b/sim/testsuite/sim/frv/add.pcgs new file mode 100644 index 00000000000..cf49976d440 --- /dev/null +++ b/sim/testsuite/sim/frv/add.pcgs @@ -0,0 +1,25 @@ +# frv parallel testcase for add $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + add.p gr7,gr8,gr8 + add gr7,gr8,gr9 + add.p gr7,gr8,gr10 + add gr7,gr8,gr11 + add.p gr7,gr8,gr12 + add gr7,gr8,gr13 + test_gr_immed 3,gr8 + test_gr_immed 3,gr9 + test_gr_immed 4,gr10 + test_gr_immed 4,gr11 + test_gr_immed 4,gr12 + test_gr_immed 4,gr13 + + pass diff --git a/sim/testsuite/sim/frv/addcc.cgs b/sim/testsuite/sim/frv/addcc.cgs new file mode 100644 index 00000000000..d2e33d8fa2a --- /dev/null +++ b/sim/testsuite/sim/frv/addcc.cgs @@ -0,0 +1,36 @@ +# frv testcase for addcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addcc +addcc: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + addcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + addcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x08,0 ; Set mask opposite of expected + addcc gr8,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + addcc gr8,gr8,gr8,icc0; test zero, carry and overflow bits + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + + pass diff --git a/sim/testsuite/sim/frv/addi.cgs b/sim/testsuite/sim/frv/addi.cgs new file mode 100644 index 00000000000..3d60c5d9acf --- /dev/null +++ b/sim/testsuite/sim/frv/addi.cgs @@ -0,0 +1,25 @@ +# frv testcase for addi $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global addi +addi: + set_gr_immed 4,gr8 + addi gr8,0,gr8 + test_gr_immed 4,gr8 + addi gr8,1,gr8 + test_gr_immed 5,gr8 + addi gr8,15,gr8 + test_gr_immed 20,gr8 + set_gr_limmed 0x7fff,0xffff,gr8 + addi gr8,1,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + addi gr8,0x7ff,gr8 + test_gr_limmed 0x8000,0x07ff,gr8 + addi gr8,-2048,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + + pass diff --git a/sim/testsuite/sim/frv/addicc.cgs b/sim/testsuite/sim/frv/addicc.cgs new file mode 100644 index 00000000000..6f2a19760c4 --- /dev/null +++ b/sim/testsuite/sim/frv/addicc.cgs @@ -0,0 +1,30 @@ +# frv testcase for addicc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addicc +addicc: + ; Test add $u4Ri + set_gr_immed 4,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + addicc gr8,0,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 4,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + addicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 5,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + addicc gr8,15,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 20,gr8 + set_gr_limmed 0x7fff,0xffff,gr8 ; test neg and overflow bits + set_icc 0x05,0 ; Set mask opposite of expected + addicc gr8,1,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/addx.cgs b/sim/testsuite/sim/frv/addx.cgs new file mode 100644 index 00000000000..259a694062f --- /dev/null +++ b/sim/testsuite/sim/frv/addx.cgs @@ -0,0 +1,49 @@ +# frv testcase for addx $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addx +addx: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry bit is off + addx gr7,gr8,gr8,icc0 + test_icc 1 1 1 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x04,0 ; Make sure carry bit is off + addx gr7,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x08,0 ; Make sure carry bit is off + addx gr8,gr8,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Make sure carry bit is on + addx gr7,gr8,gr8,icc0 + test_icc 1 1 1 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 0,gr8 + set_icc 0x05,0 ; Make sure carry bit is on + addx gr7,gr8,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_icc 0x0b,0 ; Make sure carry bit is on + addx gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/addxcc.cgs b/sim/testsuite/sim/frv/addxcc.cgs new file mode 100644 index 00000000000..230c047d688 --- /dev/null +++ b/sim/testsuite/sim/frv/addxcc.cgs @@ -0,0 +1,49 @@ +# frv testcase for addxcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addxcc +addxcc: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry bit is off + addxcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x04,0 ; Make sure carry bit is off + addxcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x08,0 ; Make sure carry bit is off + addxcc gr8,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Make sure carry bit is on + addxcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 0,gr8 + set_icc 0x05,0 ; Make sure carry bit is on + addxcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_icc 0x0b,0 ; Make sure carry bit is on + addxcc gr7,gr8,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/addxi.cgs b/sim/testsuite/sim/frv/addxi.cgs new file mode 100644 index 00000000000..c36272a14ea --- /dev/null +++ b/sim/testsuite/sim/frv/addxi.cgs @@ -0,0 +1,46 @@ +# frv testcase for addxi $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addxi +addxi: + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry bit is off + addxi gr8,1,gr8,icc0 + test_icc 1 1 1 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x04,0 ; Make sure carry bit is off + addxi gr8,1,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xffff,0xff00,gr8 + set_icc 0x08,0 ; Make sure carry bit is off + addxi gr8,0x100,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Make sure carry bit is on + addxi gr8,1,gr8,icc0 + test_icc 1 1 1 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x05,0 ; Make sure carry bit is on + addxi gr8,0,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xffff,0xfeff,gr8 + set_icc 0x0b,0 ; Make sure carry bit is on + addxi gr8,0x100,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/addxicc.cgs b/sim/testsuite/sim/frv/addxicc.cgs new file mode 100644 index 00000000000..831fec39bdf --- /dev/null +++ b/sim/testsuite/sim/frv/addxicc.cgs @@ -0,0 +1,46 @@ +# frv testcase for addxicc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addxicc +addxicc: + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry bit is off + addxicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x04,0 ; Make sure carry bit is off + addxicc gr8,1,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xffff,0xff00,gr8 + set_icc 0x08,0 ; Make sure carry bit is off + addxicc gr8,0x100,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Make sure carry bit is on + addxicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x05,0 ; Make sure carry bit is on + addxicc gr8,0,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xffff,0xfeff,gr8 + set_icc 0x0b,0 ; Make sure carry bit is on + addxicc gr8,0x100,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/allinsn.exp b/sim/testsuite/sim/frv/allinsn.exp new file mode 100644 index 00000000000..20f72093701 --- /dev/null +++ b/sim/testsuite/sim/frv/allinsn.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "frv fr500 fr400" + set cpu_option -mcpu + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/frv/and.cgs b/sim/testsuite/sim/frv/and.cgs new file mode 100644 index 00000000000..a1773f1e3de --- /dev/null +++ b/sim/testsuite/sim/frv/and.cgs @@ -0,0 +1,29 @@ +# frv testcase for and $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global and +and: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + and gr7,gr8,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + and gr7,gr8,gr8 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + and gr7,gr8,gr8 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x0000,0xaaaa,gr8 + + pass diff --git a/sim/testsuite/sim/frv/andcc.cgs b/sim/testsuite/sim/frv/andcc.cgs new file mode 100644 index 00000000000..a2a04d2c0ca --- /dev/null +++ b/sim/testsuite/sim/frv/andcc.cgs @@ -0,0 +1,29 @@ +# frv testcase for andcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global andcc +andcc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + andcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + andcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + andcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x0000,0xaaaa,gr8 + + pass diff --git a/sim/testsuite/sim/frv/andcr.cgs b/sim/testsuite/sim/frv/andcr.cgs new file mode 100644 index 00000000000..9fbbaffb8b0 --- /dev/null +++ b/sim/testsuite/sim/frv/andcr.cgs @@ -0,0 +1,59 @@ +# frv testcase for andcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global andcr +andcr: + set_spr_immed 0x1b1b,cccr + andcr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc7,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc7,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc6,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc6,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc5,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc5,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc5,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc5,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc4,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc4,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc4,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + andcr cc4,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/andi.cgs b/sim/testsuite/sim/frv/andi.cgs new file mode 100644 index 00000000000..e9fdf75b4d5 --- /dev/null +++ b/sim/testsuite/sim/frv/andi.cgs @@ -0,0 +1,26 @@ +# frv testcase for andi $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global andi +andi: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x0b,0 ; Set mask opposite of expected + andi gr7,0x555,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_icc 0x04,0 ; Set mask opposite of expected + andi gr7,-2048,gr8 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0xaaaa,0xa800,gr8 + + set_icc 0x0d,0 ; Set mask opposite of expected + andi gr7,-1,gr8 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + pass diff --git a/sim/testsuite/sim/frv/andicc.cgs b/sim/testsuite/sim/frv/andicc.cgs new file mode 100644 index 00000000000..650805975ad --- /dev/null +++ b/sim/testsuite/sim/frv/andicc.cgs @@ -0,0 +1,26 @@ +# frv testcase for andicc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global andicc +andicc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x0b,0 ; Set mask opposite of expected + andicc gr7,0x155,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_icc 0x04,0 ; Set mask opposite of expected + andicc gr7,-512,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xaaaa,0xaa00,gr8 + + set_icc 0x05,0 ; Set mask opposite of expected + andicc gr7,-1,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + pass diff --git a/sim/testsuite/sim/frv/andncr.cgs b/sim/testsuite/sim/frv/andncr.cgs new file mode 100644 index 00000000000..31fd1f78d0d --- /dev/null +++ b/sim/testsuite/sim/frv/andncr.cgs @@ -0,0 +1,59 @@ +# frv testcase for andncr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global andncr +andncr: + set_spr_immed 0x1b1b,cccr + andncr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc7,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc7,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc6,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc6,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc5,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc5,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc5,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + andncr cc5,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + andncr cc4,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc4,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc4,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc4,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/bar.cgs b/sim/testsuite/sim/frv/bar.cgs new file mode 100644 index 00000000000..df6a9caf6ec --- /dev/null +++ b/sim/testsuite/sim/frv/bar.cgs @@ -0,0 +1,12 @@ +# frv testcase for bar +# mach: all + + .include "testutils.inc" + + start + + .global bar +bar: + bar + + pass diff --git a/sim/testsuite/sim/frv/bc.cgs b/sim/testsuite/sim/frv/bc.cgs new file mode 100644 index 00000000000..a5c612ccc9a --- /dev/null +++ b/sim/testsuite/sim/frv/bc.cgs @@ -0,0 +1,61 @@ +# frv testcase for bc $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bc +bc: + set_icc 0x0 0 + bc icc0,0,bad + set_icc 0x1 1 + bc icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bc icc2,2,bad + set_icc 0x3 3 + bc icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + bc icc0,0,bad + set_icc 0x5 1 + bc icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + bc icc2,2,bad + set_icc 0x7 3 + bc icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + bc icc0,0,bad + set_icc 0x9 1 + bc icc1,1,oka + fail +oka: + set_icc 0xa 2 + bc icc2,2,bad + set_icc 0xb 3 + bc icc3,3,okc + fail +okc: + set_icc 0xc 0 + bc icc0,0,bad + set_icc 0xd 1 + bc icc1,1,oke + fail +oke: + set_icc 0xe 2 + bc icc2,2,bad + set_icc 0xf 3 + bc icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcclr.cgs b/sim/testsuite/sim/frv/bcclr.cgs new file mode 100644 index 00000000000..248be13491a --- /dev/null +++ b/sim/testsuite/sim/frv/bcclr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bcclr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcclr +bcclr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcclr icc0,0,0 + + set_spr_addr ok2,lr + set_icc 0x1 1 + bcclr icc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bcclr icc2,0,2 + + set_spr_addr ok4,lr + set_icc 0x3 3 + bcclr icc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bcclr icc0,0,0 + + set_spr_addr ok6,lr + set_icc 0x5 1 + bcclr icc1,0,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bcclr icc2,0,2 + + set_spr_addr ok8,lr + set_icc 0x7 3 + bcclr icc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bcclr icc0,0,0 + + set_spr_addr oka,lr + set_icc 0x9 1 + bcclr icc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bcclr icc2,0,2 + + set_spr_addr okc,lr + set_icc 0xb 3 + bcclr icc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bcclr icc0,0,0 + + set_spr_addr oke,lr + set_icc 0xd 1 + bcclr icc1,0,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bcclr icc2,0,2 + + set_spr_addr okg,lr + set_icc 0xf 3 + bcclr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcclr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcclr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bcclr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcclr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcclr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bcclr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcclr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bcclr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bcclr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcclr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bcclr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcclr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcclr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bcclr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcclr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bcclr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcclr icc0,1,0 + + set_icc 0x1 1 + bcclr icc1,1,1 + + set_icc 0x2 2 + bcclr icc2,1,2 + + set_icc 0x3 3 + bcclr icc3,1,3 + + set_icc 0x4 0 + bcclr icc0,1,0 + + set_icc 0x5 1 + bcclr icc1,1,1 + + set_icc 0x6 2 + bcclr icc2,1,2 + + set_icc 0x7 3 + bcclr icc3,1,3 + + set_icc 0x8 0 + bcclr icc0,1,0 + + set_icc 0x9 1 + bcclr icc1,1,1 + + set_icc 0xa 2 + bcclr icc2,1,2 + + set_icc 0xb 3 + bcclr icc3,1,3 + + set_icc 0xc 0 + bcclr icc0,1,0 + + set_icc 0xd 1 + bcclr icc1,1,1 + + set_icc 0xe 2 + bcclr icc2,1,2 + + set_icc 0xf 3 + bcclr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcclr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bceqlr.cgs b/sim/testsuite/sim/frv/bceqlr.cgs new file mode 100644 index 00000000000..bacabf417ec --- /dev/null +++ b/sim/testsuite/sim/frv/bceqlr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bceqlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bceqlr +bceqlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bceqlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bceqlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x2 2 + bceqlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bceqlr icc3,0,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bceqlr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bceqlr icc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bceqlr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bceqlr icc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bceqlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bceqlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xa 2 + bceqlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bceqlr icc3,0,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bceqlr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bceqlr icc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bceqlr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bceqlr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bceqlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bceqlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bceqlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bceqlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bceqlr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bceqlr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bceqlr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bceqlr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bceqlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bceqlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bceqlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bceqlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bceqlr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bceqlr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bceqlr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bceqlr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bceqlr icc0,1,0 + + set_icc 0x1 1 + bceqlr icc1,1,1 + + set_icc 0x2 2 + bceqlr icc2,1,2 + + set_icc 0x3 3 + bceqlr icc3,1,3 + + set_icc 0x4 0 + bceqlr icc0,1,0 + + set_icc 0x5 1 + bceqlr icc1,1,1 + + set_icc 0x6 2 + bceqlr icc2,1,2 + + set_icc 0x7 3 + bceqlr icc3,1,3 + + set_icc 0x8 0 + bceqlr icc0,1,0 + + set_icc 0x9 1 + bceqlr icc1,1,1 + + set_icc 0xa 2 + bceqlr icc2,1,2 + + set_icc 0xb 3 + bceqlr icc3,1,3 + + set_icc 0xc 0 + bceqlr icc0,1,0 + + set_icc 0xd 1 + bceqlr icc1,1,1 + + set_icc 0xe 2 + bceqlr icc2,1,2 + + set_icc 0xf 3 + bceqlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bceqlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bceqlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bceqlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bceqlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bceqlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bceqlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bceqlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bceqlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bceqlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bceqlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bceqlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bceqlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bceqlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bceqlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bceqlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bceqlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcgelr.cgs b/sim/testsuite/sim/frv/bcgelr.cgs new file mode 100644 index 00000000000..72bd37450fd --- /dev/null +++ b/sim/testsuite/sim/frv/bcgelr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bcgelr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcgelr +bcgelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcgelr icc0,0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcgelr icc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bcgelr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bcgelr icc3,0,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bcgelr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bcgelr icc1,0,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bcgelr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bcgelr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0x8 0 + bcgelr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bcgelr icc1,0,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bcgelr icc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcgelr icc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bcgelr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bcgelr icc1,0,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bcgelr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bcgelr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcgelr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcgelr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bcgelr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bcgelr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bcgelr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bcgelr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcgelr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcgelr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bcgelr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bcgelr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcgelr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcgelr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcgelr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcgelr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bcgelr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bcgelr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcgelr icc0,1,0 + + set_icc 0x1 1 + bcgelr icc1,1,1 + + set_icc 0x2 2 + bcgelr icc2,1,2 + + set_icc 0x3 3 + bcgelr icc3,1,3 + + set_icc 0x4 0 + bcgelr icc0,1,0 + + set_icc 0x5 1 + bcgelr icc1,1,1 + + set_icc 0x6 2 + bcgelr icc2,1,2 + + set_icc 0x7 3 + bcgelr icc3,1,3 + + set_icc 0x8 0 + bcgelr icc0,1,0 + + set_icc 0x9 1 + bcgelr icc1,1,1 + + set_icc 0xa 2 + bcgelr icc2,1,2 + + set_icc 0xb 3 + bcgelr icc3,1,3 + + set_icc 0xc 0 + bcgelr icc0,1,0 + + set_icc 0xd 1 + bcgelr icc1,1,1 + + set_icc 0xe 2 + bcgelr icc2,1,2 + + set_icc 0xf 3 + bcgelr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcgelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcgelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcgelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcgelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcgelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcgelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcgelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcgelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcgelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcgelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcgelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcgelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcgelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcgelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcgelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcgelr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcgtlr.cgs b/sim/testsuite/sim/frv/bcgtlr.cgs new file mode 100644 index 00000000000..edffed83327 --- /dev/null +++ b/sim/testsuite/sim/frv/bcgtlr.cgs @@ -0,0 +1,284 @@ +# frv testcase for bcgtlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcgtlr +bcgtlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcgtlr icc0,0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcgtlr icc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bcgtlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bcgtlr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bcgtlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bcgtlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bcgtlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bcgtlr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0x8 0 + bcgtlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bcgtlr icc1,0,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bcgtlr icc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcgtlr icc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bcgtlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bcgtlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bcgtlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bcgtlr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcgtlr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcgtlr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bcgtlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bcgtlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcgtlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcgtlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcgtlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcgtlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bcgtlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bcgtlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcgtlr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcgtlr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcgtlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcgtlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcgtlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcgtlr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcgtlr icc0,1,0 + + set_icc 0x1 1 + bcgtlr icc1,1,1 + + set_icc 0x2 2 + bcgtlr icc2,1,2 + + set_icc 0x3 3 + bcgtlr icc3,1,3 + + set_icc 0x4 0 + bcgtlr icc0,1,0 + + set_icc 0x5 1 + bcgtlr icc1,1,1 + + set_icc 0x6 2 + bcgtlr icc2,1,2 + + set_icc 0x7 3 + bcgtlr icc3,1,3 + + set_icc 0x8 0 + bcgtlr icc0,1,0 + + set_icc 0x9 1 + bcgtlr icc1,1,1 + + set_icc 0xa 2 + bcgtlr icc2,1,2 + + set_icc 0xb 3 + bcgtlr icc3,1,3 + + set_icc 0xc 0 + bcgtlr icc0,1,0 + + set_icc 0xd 1 + bcgtlr icc1,1,1 + + set_icc 0xe 2 + bcgtlr icc2,1,2 + + set_icc 0xf 3 + bcgtlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcgtlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcgtlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcgtlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcgtlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcgtlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcgtlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcgtlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcgtlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcgtlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcgtlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcgtlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcgtlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcgtlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcgtlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcgtlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcgtlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bchilr.cgs b/sim/testsuite/sim/frv/bchilr.cgs new file mode 100644 index 00000000000..ea7e2f4bac5 --- /dev/null +++ b/sim/testsuite/sim/frv/bchilr.cgs @@ -0,0 +1,284 @@ +# frv testcase for bchilr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bchilr +bchilr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bchilr icc0,0,0 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x1 1 + bchilr icc1,0,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bchilr icc2,0,2 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x3 3 + bchilr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bchilr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bchilr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bchilr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bchilr icc3,0,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bchilr icc0,0,0 + fail +ok9: + set_spr_addr bad,lr + set_icc 0x9 1 + bchilr icc1,0,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bchilr icc2,0,2 + fail +okb: + set_spr_addr bad,lr + set_icc 0xb 3 + bchilr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0xc 0 + bchilr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bchilr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bchilr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bchilr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bchilr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bchilr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bchilr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bchilr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bchilr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bchilr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bchilr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bchilr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bchilr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bchilr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bchilr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bchilr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bchilr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bchilr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bchilr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bchilr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bchilr icc0,1,0 + + set_icc 0x1 1 + bchilr icc1,1,1 + + set_icc 0x2 2 + bchilr icc2,1,2 + + set_icc 0x3 3 + bchilr icc3,1,3 + + set_icc 0x4 0 + bchilr icc0,1,0 + + set_icc 0x5 1 + bchilr icc1,1,1 + + set_icc 0x6 2 + bchilr icc2,1,2 + + set_icc 0x7 3 + bchilr icc3,1,3 + + set_icc 0x8 0 + bchilr icc0,1,0 + + set_icc 0x9 1 + bchilr icc1,1,1 + + set_icc 0xa 2 + bchilr icc2,1,2 + + set_icc 0xb 3 + bchilr icc3,1,3 + + set_icc 0xc 0 + bchilr icc0,1,0 + + set_icc 0xd 1 + bchilr icc1,1,1 + + set_icc 0xe 2 + bchilr icc2,1,2 + + set_icc 0xf 3 + bchilr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bchilr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bchilr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bchilr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bchilr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bchilr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bchilr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bchilr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bchilr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bchilr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bchilr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bchilr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bchilr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bchilr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bchilr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bchilr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bchilr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bclelr.cgs b/sim/testsuite/sim/frv/bclelr.cgs new file mode 100644 index 00000000000..6668c77684b --- /dev/null +++ b/sim/testsuite/sim/frv/bclelr.cgs @@ -0,0 +1,301 @@ +# frv testcase for bclelr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bclelr +bclelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclelr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bclelr icc1,0,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bclelr icc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bclelr icc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bclelr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bclelr icc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bclelr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bclelr icc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + bclelr icc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bclelr icc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bclelr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bclelr icc3,0,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bclelr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bclelr icc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bclelr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bclelr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclelr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bclelr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bclelr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bclelr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bclelr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bclelr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bclelr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bclelr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bclelr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bclelr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bclelr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bclelr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bclelr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bclelr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bclelr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bclelr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclelr icc0,1,0 + + set_icc 0x1 1 + bclelr icc1,1,1 + + set_icc 0x2 2 + bclelr icc2,1,2 + + set_icc 0x3 3 + bclelr icc3,1,3 + + set_icc 0x4 0 + bclelr icc0,1,0 + + set_icc 0x5 1 + bclelr icc1,1,1 + + set_icc 0x6 2 + bclelr icc2,1,2 + + set_icc 0x7 3 + bclelr icc3,1,3 + + set_icc 0x8 0 + bclelr icc0,1,0 + + set_icc 0x9 1 + bclelr icc1,1,1 + + set_icc 0xa 2 + bclelr icc2,1,2 + + set_icc 0xb 3 + bclelr icc3,1,3 + + set_icc 0xc 0 + bclelr icc0,1,0 + + set_icc 0xd 1 + bclelr icc1,1,1 + + set_icc 0xe 2 + bclelr icc2,1,2 + + set_icc 0xf 3 + bclelr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bclelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bclelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bclelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bclelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bclelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bclelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bclelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bclelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bclelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bclelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bclelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bclelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bclelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bclelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bclelr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bclr.cgs b/sim/testsuite/sim/frv/bclr.cgs new file mode 100644 index 00000000000..d36563b618d --- /dev/null +++ b/sim/testsuite/sim/frv/bclr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bclr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bclr +bclr: + set_spr_addr bad,lr + set_icc 0x0 0 + bclr icc0,0 + + set_spr_addr ok2,lr + set_icc 0x1 1 + bclr icc1,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bclr icc2,2 + + set_spr_addr ok4,lr + set_icc 0x3 3 + bclr icc3,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bclr icc0,0 + + set_spr_addr ok6,lr + set_icc 0x5 1 + bclr icc1,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bclr icc2,2 + + set_spr_addr ok8,lr + set_icc 0x7 3 + bclr icc3,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bclr icc0,0 + + set_spr_addr oka,lr + set_icc 0x9 1 + bclr icc1,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bclr icc2,2 + + set_spr_addr okc,lr + set_icc 0xb 3 + bclr icc3,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bclr icc0,0 + + set_spr_addr oke,lr + set_icc 0xd 1 + bclr icc1,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bclr icc2,2 + + set_spr_addr okg,lr + set_icc 0xf 3 + bclr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bclslr.cgs b/sim/testsuite/sim/frv/bclslr.cgs new file mode 100644 index 00000000000..37b91bc105d --- /dev/null +++ b/sim/testsuite/sim/frv/bclslr.cgs @@ -0,0 +1,301 @@ +# frv testcase for bclslr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bclslr +bclslr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclslr icc0,0,0 + + set_spr_addr ok2,lr + set_icc 0x1 1 + bclslr icc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bclslr icc2,0,2 + + set_spr_addr ok4,lr + set_icc 0x3 3 + bclslr icc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bclslr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bclslr icc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bclslr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bclslr icc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bclslr icc0,0,0 + + set_spr_addr oka,lr + set_icc 0x9 1 + bclslr icc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bclslr icc2,0,2 + + set_spr_addr okc,lr + set_icc 0xb 3 + bclslr icc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + bclslr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bclslr icc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bclslr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bclslr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclslr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bclslr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bclslr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bclslr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bclslr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bclslr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bclslr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bclslr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bclslr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bclslr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bclslr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bclslr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bclslr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bclslr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bclslr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bclslr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclslr icc0,1,0 + + set_icc 0x1 1 + bclslr icc1,1,1 + + set_icc 0x2 2 + bclslr icc2,1,2 + + set_icc 0x3 3 + bclslr icc3,1,3 + + set_icc 0x4 0 + bclslr icc0,1,0 + + set_icc 0x5 1 + bclslr icc1,1,1 + + set_icc 0x6 2 + bclslr icc2,1,2 + + set_icc 0x7 3 + bclslr icc3,1,3 + + set_icc 0x8 0 + bclslr icc0,1,0 + + set_icc 0x9 1 + bclslr icc1,1,1 + + set_icc 0xa 2 + bclslr icc2,1,2 + + set_icc 0xb 3 + bclslr icc3,1,3 + + set_icc 0xc 0 + bclslr icc0,1,0 + + set_icc 0xd 1 + bclslr icc1,1,1 + + set_icc 0xe 2 + bclslr icc2,1,2 + + set_icc 0xf 3 + bclslr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclslr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bclslr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bclslr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bclslr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bclslr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bclslr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bclslr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bclslr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bclslr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bclslr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bclslr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bclslr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bclslr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bclslr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bclslr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bclslr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcltlr.cgs b/sim/testsuite/sim/frv/bcltlr.cgs new file mode 100644 index 00000000000..0ba6bfa8aaf --- /dev/null +++ b/sim/testsuite/sim/frv/bcltlr.cgs @@ -0,0 +1,292 @@ +# frv testcase for bcltlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcltlr +bcltlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcltlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bcltlr icc1,0,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bcltlr icc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bcltlr icc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bcltlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bcltlr icc1,0,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bcltlr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bcltlr icc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + bcltlr icc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bcltlr icc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bcltlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bcltlr icc3,0,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bcltlr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bcltlr icc1,0,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bcltlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bcltlr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcltlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bcltlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcltlr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcltlr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcltlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcltlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bcltlr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bcltlr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcltlr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcltlr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bcltlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bcltlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bcltlr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bcltlr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcltlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcltlr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcltlr icc0,1,0 + + set_icc 0x1 1 + bcltlr icc1,1,1 + + set_icc 0x2 2 + bcltlr icc2,1,2 + + set_icc 0x3 3 + bcltlr icc3,1,3 + + set_icc 0x4 0 + bcltlr icc0,1,0 + + set_icc 0x5 1 + bcltlr icc1,1,1 + + set_icc 0x6 2 + bcltlr icc2,1,2 + + set_icc 0x7 3 + bcltlr icc3,1,3 + + set_icc 0x8 0 + bcltlr icc0,1,0 + + set_icc 0x9 1 + bcltlr icc1,1,1 + + set_icc 0xa 2 + bcltlr icc2,1,2 + + set_icc 0xb 3 + bcltlr icc3,1,3 + + set_icc 0xc 0 + bcltlr icc0,1,0 + + set_icc 0xd 1 + bcltlr icc1,1,1 + + set_icc 0xe 2 + bcltlr icc2,1,2 + + set_icc 0xf 3 + bcltlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcltlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcltlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcltlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcltlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcltlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcltlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcltlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcltlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcltlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcltlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcltlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcltlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcltlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcltlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcltlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcltlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcnclr.cgs b/sim/testsuite/sim/frv/bcnclr.cgs new file mode 100644 index 00000000000..51824a6295d --- /dev/null +++ b/sim/testsuite/sim/frv/bcnclr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bcnclr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcnclr +bcnclr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcnclr icc0,0,0 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x1 1 + bcnclr icc1,0,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bcnclr icc2,0,2 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x3 3 + bcnclr icc3,0,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bcnclr icc0,0,0 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x5 1 + bcnclr icc1,0,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bcnclr icc2,0,2 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x7 3 + bcnclr icc3,0,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bcnclr icc0,0,0 + fail +ok9: + set_spr_addr bad,lr + set_icc 0x9 1 + bcnclr icc1,0,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bcnclr icc2,0,2 + fail +okb: + set_spr_addr bad,lr + set_icc 0xb 3 + bcnclr icc3,0,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bcnclr icc0,0,0 + fail +okd: + set_spr_addr bad,lr + set_icc 0xd 1 + bcnclr icc1,0,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bcnclr icc2,0,2 + fail +okf: + set_spr_addr bad,lr + set_icc 0xf 3 + bcnclr icc3,0,3 + + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcnclr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bcnclr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcnclr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bcnclr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bcnclr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcnclr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bcnclr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcnclr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcnclr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bcnclr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcnclr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bcnclr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bcnclr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcnclr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bcnclr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcnclr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnclr icc0,1,0 + + set_icc 0x1 1 + bcnclr icc1,1,1 + + set_icc 0x2 2 + bcnclr icc2,1,2 + + set_icc 0x3 3 + bcnclr icc3,1,3 + + set_icc 0x4 0 + bcnclr icc0,1,0 + + set_icc 0x5 1 + bcnclr icc1,1,1 + + set_icc 0x6 2 + bcnclr icc2,1,2 + + set_icc 0x7 3 + bcnclr icc3,1,3 + + set_icc 0x8 0 + bcnclr icc0,1,0 + + set_icc 0x9 1 + bcnclr icc1,1,1 + + set_icc 0xa 2 + bcnclr icc2,1,2 + + set_icc 0xb 3 + bcnclr icc3,1,3 + + set_icc 0xc 0 + bcnclr icc0,1,0 + + set_icc 0xd 1 + bcnclr icc1,1,1 + + set_icc 0xe 2 + bcnclr icc2,1,2 + + set_icc 0xf 3 + bcnclr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnclr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcnelr.cgs b/sim/testsuite/sim/frv/bcnelr.cgs new file mode 100644 index 00000000000..55be2d3c156 --- /dev/null +++ b/sim/testsuite/sim/frv/bcnelr.cgs @@ -0,0 +1,292 @@ +# frv testcase for bcnelr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcnelr +bcnelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcnelr icc0,0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcnelr icc1,0,1 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bcnelr icc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bcnelr icc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bcnelr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bcnelr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bcnelr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bcnelr icc3,0,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bcnelr icc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bcnelr icc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bcnelr icc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcnelr icc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bcnelr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bcnelr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bcnelr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bcnelr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcnelr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcnelr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcnelr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcnelr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcnelr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcnelr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcnelr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcnelr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcnelr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcnelr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcnelr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcnelr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcnelr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcnelr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcnelr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcnelr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnelr icc0,1,0 + + set_icc 0x1 1 + bcnelr icc1,1,1 + + set_icc 0x2 2 + bcnelr icc2,1,2 + + set_icc 0x3 3 + bcnelr icc3,1,3 + + set_icc 0x4 0 + bcnelr icc0,1,0 + + set_icc 0x5 1 + bcnelr icc1,1,1 + + set_icc 0x6 2 + bcnelr icc2,1,2 + + set_icc 0x7 3 + bcnelr icc3,1,3 + + set_icc 0x8 0 + bcnelr icc0,1,0 + + set_icc 0x9 1 + bcnelr icc1,1,1 + + set_icc 0xa 2 + bcnelr icc2,1,2 + + set_icc 0xb 3 + bcnelr icc3,1,3 + + set_icc 0xc 0 + bcnelr icc0,1,0 + + set_icc 0xd 1 + bcnelr icc1,1,1 + + set_icc 0xe 2 + bcnelr icc2,1,2 + + set_icc 0xf 3 + bcnelr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnelr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcnlr.cgs b/sim/testsuite/sim/frv/bcnlr.cgs new file mode 100644 index 00000000000..8ddfcaa33d0 --- /dev/null +++ b/sim/testsuite/sim/frv/bcnlr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bcnlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcnlr +bcnlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bcnlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x2 2 + bcnlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bcnlr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bcnlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bcnlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bcnlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bcnlr icc3,0,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bcnlr icc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bcnlr icc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bcnlr icc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcnlr icc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + bcnlr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bcnlr icc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bcnlr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bcnlr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bcnlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bcnlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bcnlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcnlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcnlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcnlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcnlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcnlr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcnlr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcnlr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcnlr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bcnlr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bcnlr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bcnlr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bcnlr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnlr icc0,1,0 + + set_icc 0x1 1 + bcnlr icc1,1,1 + + set_icc 0x2 2 + bcnlr icc2,1,2 + + set_icc 0x3 3 + bcnlr icc3,1,3 + + set_icc 0x4 0 + bcnlr icc0,1,0 + + set_icc 0x5 1 + bcnlr icc1,1,1 + + set_icc 0x6 2 + bcnlr icc2,1,2 + + set_icc 0x7 3 + bcnlr icc3,1,3 + + set_icc 0x8 0 + bcnlr icc0,1,0 + + set_icc 0x9 1 + bcnlr icc1,1,1 + + set_icc 0xa 2 + bcnlr icc2,1,2 + + set_icc 0xb 3 + bcnlr icc3,1,3 + + set_icc 0xc 0 + bcnlr icc0,1,0 + + set_icc 0xd 1 + bcnlr icc1,1,1 + + set_icc 0xe 2 + bcnlr icc2,1,2 + + set_icc 0xf 3 + bcnlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcnolr.cgs b/sim/testsuite/sim/frv/bcnolr.cgs new file mode 100644 index 00000000000..04f0b8dbd84 --- /dev/null +++ b/sim/testsuite/sim/frv/bcnolr.cgs @@ -0,0 +1,246 @@ +# frv testcase for bcnolr +# mach: all + + .include "testutils.inc" + + start + + .global bcnolr +bcnolr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnolr + + set_icc 0x1 1 + bcnolr + + set_icc 0x2 2 + bcnolr + + set_icc 0x3 3 + bcnolr + + set_icc 0x4 0 + bcnolr + + set_icc 0x5 1 + bcnolr + + set_icc 0x6 2 + bcnolr + + set_icc 0x7 3 + bcnolr + + set_icc 0x8 0 + bcnolr + + set_icc 0x9 1 + bcnolr + + set_icc 0xa 2 + bcnolr + + set_icc 0xb 3 + bcnolr + + set_icc 0xc 0 + bcnolr + + set_icc 0xd 1 + bcnolr + + set_icc 0xe 2 + bcnolr + + set_icc 0xf 3 + bcnolr + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnolr + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnolr + + set_icc 0x1 1 + bcnolr + + set_icc 0x2 2 + bcnolr + + set_icc 0x3 3 + bcnolr + + set_icc 0x4 0 + bcnolr + + set_icc 0x5 1 + bcnolr + + set_icc 0x6 2 + bcnolr + + set_icc 0x7 3 + bcnolr + + set_icc 0x8 0 + bcnolr + + set_icc 0x9 1 + bcnolr + + set_icc 0xa 2 + bcnolr + + set_icc 0xb 3 + bcnolr + + set_icc 0xc 0 + bcnolr + + set_icc 0xd 1 + bcnolr + + set_icc 0xe 2 + bcnolr + + set_icc 0xf 3 + bcnolr + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnolr + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcnvlr.cgs b/sim/testsuite/sim/frv/bcnvlr.cgs new file mode 100644 index 00000000000..24515575ee5 --- /dev/null +++ b/sim/testsuite/sim/frv/bcnvlr.cgs @@ -0,0 +1,292 @@ +# frv testcase for bcnvlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcnvlr +bcnvlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcnvlr icc0,0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcnvlr icc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bcnvlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bcnvlr icc3,0,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bcnvlr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bcnvlr icc1,0,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bcnvlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bcnvlr icc3,0,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bcnvlr icc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bcnvlr icc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bcnvlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bcnvlr icc3,0,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bcnvlr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bcnvlr icc1,0,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bcnvlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bcnvlr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcnvlr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcnvlr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bcnvlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bcnvlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bcnvlr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bcnvlr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcnvlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcnvlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcnvlr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcnvlr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bcnvlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bcnvlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bcnvlr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bcnvlr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcnvlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcnvlr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnvlr icc0,1,0 + + set_icc 0x1 1 + bcnvlr icc1,1,1 + + set_icc 0x2 2 + bcnvlr icc2,1,2 + + set_icc 0x3 3 + bcnvlr icc3,1,3 + + set_icc 0x4 0 + bcnvlr icc0,1,0 + + set_icc 0x5 1 + bcnvlr icc1,1,1 + + set_icc 0x6 2 + bcnvlr icc2,1,2 + + set_icc 0x7 3 + bcnvlr icc3,1,3 + + set_icc 0x8 0 + bcnvlr icc0,1,0 + + set_icc 0x9 1 + bcnvlr icc1,1,1 + + set_icc 0xa 2 + bcnvlr icc2,1,2 + + set_icc 0xb 3 + bcnvlr icc3,1,3 + + set_icc 0xc 0 + bcnvlr icc0,1,0 + + set_icc 0xd 1 + bcnvlr icc1,1,1 + + set_icc 0xe 2 + bcnvlr icc2,1,2 + + set_icc 0xf 3 + bcnvlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnvlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcplr.cgs b/sim/testsuite/sim/frv/bcplr.cgs new file mode 100644 index 00000000000..fef3ccbadbe --- /dev/null +++ b/sim/testsuite/sim/frv/bcplr.cgs @@ -0,0 +1,292 @@ +# frv testcase for bcplr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcplr +bcplr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcplr icc0,0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcplr icc1,0,1 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bcplr icc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bcplr icc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bcplr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bcplr icc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bcplr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bcplr icc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bcplr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bcplr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xa 2 + bcplr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bcplr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0xc 0 + bcplr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bcplr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bcplr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bcplr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcplr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcplr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcplr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcplr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bcplr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bcplr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bcplr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bcplr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bcplr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bcplr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bcplr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bcplr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcplr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcplr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcplr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcplr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcplr icc0,1,0 + + set_icc 0x1 1 + bcplr icc1,1,1 + + set_icc 0x2 2 + bcplr icc2,1,2 + + set_icc 0x3 3 + bcplr icc3,1,3 + + set_icc 0x4 0 + bcplr icc0,1,0 + + set_icc 0x5 1 + bcplr icc1,1,1 + + set_icc 0x6 2 + bcplr icc2,1,2 + + set_icc 0x7 3 + bcplr icc3,1,3 + + set_icc 0x8 0 + bcplr icc0,1,0 + + set_icc 0x9 1 + bcplr icc1,1,1 + + set_icc 0xa 2 + bcplr icc2,1,2 + + set_icc 0xb 3 + bcplr icc3,1,3 + + set_icc 0xc 0 + bcplr icc0,1,0 + + set_icc 0xd 1 + bcplr icc1,1,1 + + set_icc 0xe 2 + bcplr icc2,1,2 + + set_icc 0xf 3 + bcplr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcplr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcplr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcplr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcplr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcplr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcplr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcplr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcplr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcplr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcplr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcplr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcplr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcplr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcplr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcplr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcplr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcralr.cgs b/sim/testsuite/sim/frv/bcralr.cgs new file mode 100644 index 00000000000..612363d62a7 --- /dev/null +++ b/sim/testsuite/sim/frv/bcralr.cgs @@ -0,0 +1,309 @@ +# frv testcase for bcralr $ccond +# mach: all + + .include "testutils.inc" + + start + + .global bcralr +bcralr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcralr 0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcralr 0 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bcralr 0 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bcralr 0 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bcralr 0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bcralr 0 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bcralr 0 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bcralr 0 + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + bcralr 0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bcralr 0 + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bcralr 0 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcralr 0 + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + bcralr 0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bcralr 0 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bcralr 0 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bcralr 0 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcralr 1 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcralr 1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcralr 1 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcralr 1 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bcralr 1 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bcralr 1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bcralr 1 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bcralr 1 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcralr 1 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcralr 1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcralr 1 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcralr 1 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bcralr 1 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bcralr 1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bcralr 1 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bcralr 1 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcralr 1 + + set_icc 0x1 1 + bcralr 1 + + set_icc 0x2 2 + bcralr 1 + + set_icc 0x3 3 + bcralr 1 + + set_icc 0x4 0 + bcralr 1 + + set_icc 0x5 1 + bcralr 1 + + set_icc 0x6 2 + bcralr 1 + + set_icc 0x7 3 + bcralr 1 + + set_icc 0x8 0 + bcralr 1 + + set_icc 0x9 1 + bcralr 1 + + set_icc 0xa 2 + bcralr 1 + + set_icc 0xb 3 + bcralr 1 + + set_icc 0xc 0 + bcralr 1 + + set_icc 0xd 1 + bcralr 1 + + set_icc 0xe 2 + bcralr 1 + + set_icc 0xf 3 + bcralr 1 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcralr 0 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bctrlr.cgs b/sim/testsuite/sim/frv/bctrlr.cgs new file mode 100644 index 00000000000..b00cb97aaf8 --- /dev/null +++ b/sim/testsuite/sim/frv/bctrlr.cgs @@ -0,0 +1,29 @@ +# frv testcase for bctrlr $ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bctrlr +bctrlr: + set_spr_addr bad,lr + set_spr_immed 1,lcr + bctrlr 0,0 + + set_spr_addr ok1,lr + set_spr_immed 2,lcr + bctrlr 0,0 + fail +ok1: + set_spr_addr bad,lr + set_spr_immed 2,lcr + bctrlr 1,0 + + set_spr_addr ok2,lr + bctrlr 1,0 + fail +ok2: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcvlr.cgs b/sim/testsuite/sim/frv/bcvlr.cgs new file mode 100644 index 00000000000..b25d646092d --- /dev/null +++ b/sim/testsuite/sim/frv/bcvlr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bcvlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcvlr +bcvlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcvlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bcvlr icc1,0,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bcvlr icc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bcvlr icc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bcvlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bcvlr icc1,0,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bcvlr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bcvlr icc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bcvlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bcvlr icc1,0,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bcvlr icc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcvlr icc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bcvlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bcvlr icc1,0,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bcvlr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bcvlr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcvlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bcvlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcvlr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcvlr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcvlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcvlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bcvlr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bcvlr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bcvlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bcvlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcvlr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcvlr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcvlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcvlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bcvlr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bcvlr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcvlr icc0,1,0 + + set_icc 0x1 1 + bcvlr icc1,1,1 + + set_icc 0x2 2 + bcvlr icc2,1,2 + + set_icc 0x3 3 + bcvlr icc3,1,3 + + set_icc 0x4 0 + bcvlr icc0,1,0 + + set_icc 0x5 1 + bcvlr icc1,1,1 + + set_icc 0x6 2 + bcvlr icc2,1,2 + + set_icc 0x7 3 + bcvlr icc3,1,3 + + set_icc 0x8 0 + bcvlr icc0,1,0 + + set_icc 0x9 1 + bcvlr icc1,1,1 + + set_icc 0xa 2 + bcvlr icc2,1,2 + + set_icc 0xb 3 + bcvlr icc3,1,3 + + set_icc 0xc 0 + bcvlr icc0,1,0 + + set_icc 0xd 1 + bcvlr icc1,1,1 + + set_icc 0xe 2 + bcvlr icc2,1,2 + + set_icc 0xf 3 + bcvlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcvlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/beq.cgs b/sim/testsuite/sim/frv/beq.cgs new file mode 100644 index 00000000000..b3706dc09e0 --- /dev/null +++ b/sim/testsuite/sim/frv/beq.cgs @@ -0,0 +1,61 @@ +# frv testcase for beq $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global beq +beq: + set_icc 0x0 0 + beq icc0,0,bad + set_icc 0x1 1 + beq icc1,1,bad + set_icc 0x2 2 + beq icc2,2,bad + set_icc 0x3 3 + beq icc3,3,bad + set_icc 0x4 0 + beq icc0,0,ok1 + fail +ok1: + set_icc 0x5 1 + beq icc1,1,ok2 + fail +ok2: + set_icc 0x6 2 + beq icc2,2,ok3 + fail +ok3: + set_icc 0x7 3 + beq icc3,3,ok4 + fail +ok4: + set_icc 0x8 0 + beq icc0,0,bad + set_icc 0x9 1 + beq icc1,1,bad + set_icc 0xa 2 + beq icc2,2,bad + set_icc 0xb 3 + beq icc3,3,bad + set_icc 0xc 0 + beq icc0,0,ok5 + fail +ok5: + set_icc 0xd 1 + beq icc1,1,ok6 + fail +ok6: + set_icc 0xe 2 + beq icc2,2,ok7 + fail +ok7: + set_icc 0xf 3 + beq icc3,3,ok8 + fail +ok8: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/beqlr.cgs b/sim/testsuite/sim/frv/beqlr.cgs new file mode 100644 index 00000000000..772b9faf197 --- /dev/null +++ b/sim/testsuite/sim/frv/beqlr.cgs @@ -0,0 +1,71 @@ +# frv testcase for beqlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global beqlr +beqlr: + set_spr_addr bad,lr + set_icc 0x0 0 + beqlr icc0,0 + set_icc 0x1 1 + beqlr icc1,1 + set_icc 0x2 2 + beqlr icc2,2 + set_icc 0x3 3 + beqlr icc3,3 + set_spr_addr ok1,lr + set_icc 0x4 0 + beqlr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x5 1 + beqlr icc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x6 2 + beqlr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x7 3 + beqlr icc3,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x8 0 + beqlr icc0,0 + set_icc 0x9 1 + beqlr icc1,1 + set_icc 0xa 2 + beqlr icc2,2 + set_icc 0xb 3 + beqlr icc3,3 + set_spr_addr ok5,lr + set_icc 0xc 0 + beqlr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0xd 1 + beqlr icc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0xe 2 + beqlr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0xf 3 + beqlr icc3,3 + fail +ok8: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bge.cgs b/sim/testsuite/sim/frv/bge.cgs new file mode 100644 index 00000000000..7ebead7e5ee --- /dev/null +++ b/sim/testsuite/sim/frv/bge.cgs @@ -0,0 +1,61 @@ +# frv testcase for bge $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bge +bge: + set_icc 0x0 0 + bge icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bge icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bge icc2,2,bad + set_icc 0x3 3 + bge icc3,3,bad + set_icc 0x4 0 + bge icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + bge icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + bge icc2,2,bad + set_icc 0x7 3 + bge icc3,3,bad + set_icc 0x8 0 + bge icc0,0,bad + set_icc 0x9 1 + bge icc1,1,bad + set_icc 0xa 2 + bge icc2,2,okb + fail +okb: + set_icc 0xb 3 + bge icc3,3,okc + fail +okc: + set_icc 0xc 0 + bge icc0,0,bad + set_icc 0xd 1 + bge icc1,1,bad + set_icc 0xe 2 + bge icc2,2,okf + fail +okf: + set_icc 0xf 3 + bge icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bgelr.cgs b/sim/testsuite/sim/frv/bgelr.cgs new file mode 100644 index 00000000000..806770a2c27 --- /dev/null +++ b/sim/testsuite/sim/frv/bgelr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bgelr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bgelr +bgelr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bgelr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bgelr icc1,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bgelr icc2,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bgelr icc3,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bgelr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bgelr icc1,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bgelr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bgelr icc3,3 + + set_spr_addr bad,lr + set_icc 0x8 0 + bgelr icc0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bgelr icc1,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bgelr icc2,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bgelr icc3,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bgelr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bgelr icc1,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bgelr icc2,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bgelr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bgt.cgs b/sim/testsuite/sim/frv/bgt.cgs new file mode 100644 index 00000000000..98b1b17fadb --- /dev/null +++ b/sim/testsuite/sim/frv/bgt.cgs @@ -0,0 +1,53 @@ +# frv testcase for bgt $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bgt +bgt: + set_icc 0x0 0 + bgt icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bgt icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bgt icc2,2,bad + set_icc 0x3 3 + bgt icc3,3,bad + set_icc 0x4 0 + bgt icc0,0,bad + set_icc 0x5 1 + bgt icc1,1,bad + set_icc 0x6 2 + bgt icc2,2,bad + set_icc 0x7 3 + bgt icc3,3,bad + set_icc 0x8 0 + bgt icc0,0,bad + set_icc 0x9 1 + bgt icc1,1,bad + set_icc 0xa 2 + bgt icc2,2,okb + fail +okb: + set_icc 0xb 3 + bgt icc3,3,okc + fail +okc: + set_icc 0xc 0 + bgt icc0,0,bad + set_icc 0xd 1 + bgt icc1,1,bad + set_icc 0xe 2 + bgt icc2,2,bad + set_icc 0xf 3 + bgt icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bgtlr.cgs b/sim/testsuite/sim/frv/bgtlr.cgs new file mode 100644 index 00000000000..ad44a2ce2b1 --- /dev/null +++ b/sim/testsuite/sim/frv/bgtlr.cgs @@ -0,0 +1,80 @@ +# frv testcase for bgtlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bgtlr +bgtlr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bgtlr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bgtlr icc1,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bgtlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bgtlr icc3,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bgtlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bgtlr icc1,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bgtlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bgtlr icc3,3 + + set_spr_addr bad,lr + set_icc 0x8 0 + bgtlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bgtlr icc1,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bgtlr icc2,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bgtlr icc3,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bgtlr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bgtlr icc1,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bgtlr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bgtlr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bhi.cgs b/sim/testsuite/sim/frv/bhi.cgs new file mode 100644 index 00000000000..a92c0c0b307 --- /dev/null +++ b/sim/testsuite/sim/frv/bhi.cgs @@ -0,0 +1,53 @@ +# frv testcase for bhi $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bhi +bhi: + set_icc 0x0 0 + bhi icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bhi icc1,1,bad + set_icc 0x2 2 + bhi icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + bhi icc3,3,bad + set_icc 0x4 0 + bhi icc0,0,bad + set_icc 0x5 1 + bhi icc1,1,bad + set_icc 0x6 2 + bhi icc2,2,bad + set_icc 0x7 3 + bhi icc3,3,bad + set_icc 0x8 0 + bhi icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + bhi icc1,1,bad + set_icc 0xa 2 + bhi icc2,2,okb + fail +okb: + set_icc 0xb 3 + bhi icc3,3,bad + set_icc 0xc 0 + bhi icc0,0,bad + set_icc 0xd 1 + bhi icc1,1,bad + set_icc 0xe 2 + bhi icc2,2,bad + set_icc 0xf 3 + bhi icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bhilr.cgs b/sim/testsuite/sim/frv/bhilr.cgs new file mode 100644 index 00000000000..927643b2170 --- /dev/null +++ b/sim/testsuite/sim/frv/bhilr.cgs @@ -0,0 +1,80 @@ +# frv testcase for bhilr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bhilr +bhilr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bhilr icc0,0 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x1 1 + bhilr icc1,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bhilr icc2,2 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x3 3 + bhilr icc3,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bhilr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bhilr icc1,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bhilr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bhilr icc3,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bhilr icc0,0 + fail +ok9: + set_spr_addr bad,lr + set_icc 0x9 1 + bhilr icc1,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bhilr icc2,2 + fail +okb: + set_spr_addr bad,lr + set_icc 0xb 3 + bhilr icc3,3 + + set_spr_addr bad,lr + set_icc 0xc 0 + bhilr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bhilr icc1,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bhilr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bhilr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ble.cgs b/sim/testsuite/sim/frv/ble.cgs new file mode 100644 index 00000000000..c3587663606 --- /dev/null +++ b/sim/testsuite/sim/frv/ble.cgs @@ -0,0 +1,69 @@ +# frv testcase for ble $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global ble +ble: + set_icc 0x0 0 + ble icc0,0,bad + set_icc 0x1 1 + ble icc1,1,bad + set_icc 0x2 2 + ble icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + ble icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + ble icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + ble icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + ble icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + ble icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + ble icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + ble icc1,1,oka + fail +oka: + set_icc 0xa 2 + ble icc2,2,bad + set_icc 0xb 3 + ble icc3,3,bad + set_icc 0xc 0 + ble icc0,0,okd + fail +okd: + set_icc 0xd 1 + ble icc1,1,oke + fail +oke: + set_icc 0xe 2 + ble icc2,2,okf + fail +okf: + set_icc 0xf 3 + ble icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/blelr.cgs b/sim/testsuite/sim/frv/blelr.cgs new file mode 100644 index 00000000000..dbb8e84539a --- /dev/null +++ b/sim/testsuite/sim/frv/blelr.cgs @@ -0,0 +1,88 @@ +# frv testcase for blelr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global blelr +blelr: + set_spr_addr bad,lr + set_icc 0x0 0 + blelr icc0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + blelr icc1,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + blelr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + blelr icc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + blelr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + blelr icc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + blelr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + blelr icc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + blelr icc0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + blelr icc1,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + blelr icc2,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + blelr icc3,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + blelr icc0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + blelr icc1,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + blelr icc2,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + blelr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bls.cgs b/sim/testsuite/sim/frv/bls.cgs new file mode 100644 index 00000000000..e868de62af3 --- /dev/null +++ b/sim/testsuite/sim/frv/bls.cgs @@ -0,0 +1,69 @@ +# frv testcase for bls $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bls +bls: + set_icc 0x0 0 + bls icc0,0,bad + set_icc 0x1 1 + bls icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bls icc2,2,bad + set_icc 0x3 3 + bls icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + bls icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + bls icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + bls icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + bls icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + bls icc0,0,bad + set_icc 0x9 1 + bls icc1,1,oka + fail +oka: + set_icc 0xa 2 + bls icc2,2,bad + set_icc 0xb 3 + bls icc3,3,okc + fail +okc: + set_icc 0xc 0 + bls icc0,0,okd + fail +okd: + set_icc 0xd 1 + bls icc1,1,oke + fail +oke: + set_icc 0xe 2 + bls icc2,2,okf + fail +okf: + set_icc 0xf 3 + bls icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/blslr.cgs b/sim/testsuite/sim/frv/blslr.cgs new file mode 100644 index 00000000000..5166c52a54c --- /dev/null +++ b/sim/testsuite/sim/frv/blslr.cgs @@ -0,0 +1,88 @@ +# frv testcase for blslr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global blslr +blslr: + set_spr_addr bad,lr + set_icc 0x0 0 + blslr icc0,0 + + set_spr_addr ok2,lr + set_icc 0x1 1 + blslr icc1,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + blslr icc2,2 + + set_spr_addr ok4,lr + set_icc 0x3 3 + blslr icc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + blslr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + blslr icc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + blslr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + blslr icc3,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + blslr icc0,0 + + set_spr_addr oka,lr + set_icc 0x9 1 + blslr icc1,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + blslr icc2,2 + + set_spr_addr okc,lr + set_icc 0xb 3 + blslr icc3,3 + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + blslr icc0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + blslr icc1,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + blslr icc2,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + blslr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/blt.cgs b/sim/testsuite/sim/frv/blt.cgs new file mode 100644 index 00000000000..639f9710a43 --- /dev/null +++ b/sim/testsuite/sim/frv/blt.cgs @@ -0,0 +1,61 @@ +# frv testcase for blt $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global blt +blt: + set_icc 0x0 0 + blt icc0,0,bad + set_icc 0x1 1 + blt icc1,1,bad + set_icc 0x2 2 + blt icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + blt icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + blt icc0,0,bad + set_icc 0x5 1 + blt icc1,1,bad + set_icc 0x6 2 + blt icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + blt icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + blt icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + blt icc1,1,oka + fail +oka: + set_icc 0xa 2 + blt icc2,2,bad + set_icc 0xb 3 + blt icc3,3,bad + set_icc 0xc 0 + blt icc0,0,okd + fail +okd: + set_icc 0xd 1 + blt icc1,1,oke + fail +oke: + set_icc 0xe 2 + blt icc2,2,bad + set_icc 0xf 3 + blt icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bltlr.cgs b/sim/testsuite/sim/frv/bltlr.cgs new file mode 100644 index 00000000000..fcf04b5db7a --- /dev/null +++ b/sim/testsuite/sim/frv/bltlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bltlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bltlr +bltlr: + set_spr_addr bad,lr + set_icc 0x0 0 + bltlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bltlr icc1,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bltlr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bltlr icc3,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bltlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bltlr icc1,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bltlr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bltlr icc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + bltlr icc0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bltlr icc1,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bltlr icc2,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bltlr icc3,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bltlr icc0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bltlr icc1,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bltlr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bltlr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bn.cgs b/sim/testsuite/sim/frv/bn.cgs new file mode 100644 index 00000000000..e5ff3977bb4 --- /dev/null +++ b/sim/testsuite/sim/frv/bn.cgs @@ -0,0 +1,61 @@ +# frv testcase for bn $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bn +bn: + set_icc 0x0 0 + bn icc0,0,bad + set_icc 0x1 1 + bn icc1,1,bad + set_icc 0x2 2 + bn icc2,2,bad + set_icc 0x3 3 + bn icc3,3,bad + set_icc 0x4 0 + bn icc0,0,bad + set_icc 0x5 1 + bn icc1,1,bad + set_icc 0x6 2 + bn icc2,2,bad + set_icc 0x7 3 + bn icc3,3,bad + set_icc 0x8 0 + bn icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + bn icc1,1,oka + fail +oka: + set_icc 0xa 2 + bn icc2,2,okb + fail +okb: + set_icc 0xb 3 + bn icc3,3,okc + fail +okc: + set_icc 0xc 0 + bn icc0,0,okd + fail +okd: + set_icc 0xd 1 + bn icc1,1,oke + fail +oke: + set_icc 0xe 2 + bn icc2,2,okf + fail +okf: + set_icc 0xf 3 + bn icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bnc.cgs b/sim/testsuite/sim/frv/bnc.cgs new file mode 100644 index 00000000000..6f14e6cd550 --- /dev/null +++ b/sim/testsuite/sim/frv/bnc.cgs @@ -0,0 +1,61 @@ +# frv testcase for bnc $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bnc +bnc: + set_icc 0x0 0 + bnc icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bnc icc1,1,bad + set_icc 0x2 2 + bnc icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + bnc icc3,3,bad + set_icc 0x4 0 + bnc icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + bnc icc1,1,bad + set_icc 0x6 2 + bnc icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + bnc icc3,3,bad + set_icc 0x8 0 + bnc icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + bnc icc1,1,bad + set_icc 0xa 2 + bnc icc2,2,okb + fail +okb: + set_icc 0xb 3 + bnc icc3,3,bad + set_icc 0xc 0 + bnc icc0,0,okd + fail +okd: + set_icc 0xd 1 + bnc icc1,1,bad + set_icc 0xe 2 + bnc icc2,2,okf + fail +okf: + set_icc 0xf 3 + bnc icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bnclr.cgs b/sim/testsuite/sim/frv/bnclr.cgs new file mode 100644 index 00000000000..d24f8eb5463 --- /dev/null +++ b/sim/testsuite/sim/frv/bnclr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bnclr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bnclr +bnclr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bnclr icc0,0 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x1 1 + bnclr icc1,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bnclr icc2,2 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x3 3 + bnclr icc3,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bnclr icc0,0 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x5 1 + bnclr icc1,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bnclr icc2,2 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x7 3 + bnclr icc3,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bnclr icc0,0 + fail +ok9: + set_spr_addr bad,lr + set_icc 0x9 1 + bnclr icc1,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bnclr icc2,2 + fail +okb: + set_spr_addr bad,lr + set_icc 0xb 3 + bnclr icc3,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bnclr icc0,0 + fail +okd: + set_spr_addr bad,lr + set_icc 0xd 1 + bnclr icc1,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bnclr icc2,2 + fail +okf: + set_spr_addr bad,lr + set_icc 0xf 3 + bnclr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bne.cgs b/sim/testsuite/sim/frv/bne.cgs new file mode 100644 index 00000000000..f0f08945358 --- /dev/null +++ b/sim/testsuite/sim/frv/bne.cgs @@ -0,0 +1,61 @@ +# frv testcase for bne $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bne +bne: + set_icc 0x0 0 + bne icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bne icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bne icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + bne icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + bne icc0,0,bad + set_icc 0x5 1 + bne icc1,1,bad + set_icc 0x6 2 + bne icc2,2,bad + set_icc 0x7 3 + bne icc3,3,bad + set_icc 0x8 0 + bne icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + bne icc1,1,oka + fail +oka: + set_icc 0xa 2 + bne icc2,2,okb + fail +okb: + set_icc 0xb 3 + bne icc3,3,okc + fail +okc: + set_icc 0xc 0 + bne icc0,0,bad + set_icc 0xd 1 + bne icc1,1,bad + set_icc 0xe 2 + bne icc2,2,bad + set_icc 0xf 3 + bne icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bnelr.cgs b/sim/testsuite/sim/frv/bnelr.cgs new file mode 100644 index 00000000000..7a477b844e6 --- /dev/null +++ b/sim/testsuite/sim/frv/bnelr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bnelr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bnelr +bnelr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bnelr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bnelr icc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bnelr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bnelr icc3,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bnelr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bnelr icc1,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bnelr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bnelr icc3,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bnelr icc0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bnelr icc1,1 + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bnelr icc2,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bnelr icc3,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bnelr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bnelr icc1,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bnelr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bnelr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bnlr.cgs b/sim/testsuite/sim/frv/bnlr.cgs new file mode 100644 index 00000000000..de32b051694 --- /dev/null +++ b/sim/testsuite/sim/frv/bnlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bnlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bnlr +bnlr: + set_spr_addr bad,lr + set_icc 0x0 0 + bnlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bnlr icc1,1 + + set_spr_addr bad,lr + set_icc 0x2 2 + bnlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bnlr icc3,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bnlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bnlr icc1,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bnlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bnlr icc3,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bnlr icc0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bnlr icc1,1 + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bnlr icc2,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bnlr icc3,3 + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + bnlr icc0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bnlr icc1,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bnlr icc2,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bnlr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bno.cgs b/sim/testsuite/sim/frv/bno.cgs new file mode 100644 index 00000000000..005e4224437 --- /dev/null +++ b/sim/testsuite/sim/frv/bno.cgs @@ -0,0 +1,45 @@ +# frv testcase for bno $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bno +bno: + set_icc 0x0 0 + bno + set_icc 0x1 1 + bno + set_icc 0x2 2 + bno + set_icc 0x3 3 + bno + set_icc 0x4 0 + bno + set_icc 0x5 1 + bno + set_icc 0x6 2 + bno + set_icc 0x7 3 + bno + set_icc 0x8 0 + bno + set_icc 0x9 1 + bno + set_icc 0xa 2 + bno + set_icc 0xb 3 + bno + set_icc 0xc 0 + bno + set_icc 0xd 1 + bno + set_icc 0xe 2 + bno + set_icc 0xf 3 + bno + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bnolr.cgs b/sim/testsuite/sim/frv/bnolr.cgs new file mode 100644 index 00000000000..ae69f6fa495 --- /dev/null +++ b/sim/testsuite/sim/frv/bnolr.cgs @@ -0,0 +1,61 @@ +# frv testcase for bnolr +# mach: all + + .include "testutils.inc" + + start + + .global bnolr +bnolr: + set_spr_addr bad,lr + set_icc 0x0 0 + bnolr + + set_icc 0x1 1 + bnolr + + set_icc 0x2 2 + bnolr + + set_icc 0x3 3 + bnolr + + set_icc 0x4 0 + bnolr + + set_icc 0x5 1 + bnolr + + set_icc 0x6 2 + bnolr + + set_icc 0x7 3 + bnolr + + set_icc 0x8 0 + bnolr + + set_icc 0x9 1 + bnolr + + set_icc 0xa 2 + bnolr + + set_icc 0xb 3 + bnolr + + set_icc 0xc 0 + bnolr + + set_icc 0xd 1 + bnolr + + set_icc 0xe 2 + bnolr + + set_icc 0xf 3 + bnolr + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bnv.cgs b/sim/testsuite/sim/frv/bnv.cgs new file mode 100644 index 00000000000..29ec57a1ded --- /dev/null +++ b/sim/testsuite/sim/frv/bnv.cgs @@ -0,0 +1,61 @@ +# frv testcase for bnv $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bnv +bnv: + set_icc 0x0 0 + bnv icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bnv icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bnv icc2,2,bad + set_icc 0x3 3 + bnv icc3,3,bad + set_icc 0x4 0 + bnv icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + bnv icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + bnv icc2,2,bad + set_icc 0x7 3 + bnv icc3,3,bad + set_icc 0x8 0 + bnv icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + bnv icc1,1,oka + fail +oka: + set_icc 0xa 2 + bnv icc2,2,bad + set_icc 0xb 3 + bnv icc3,3,bad + set_icc 0xc 0 + bnv icc0,0,okd + fail +okd: + set_icc 0xd 1 + bnv icc1,1,oke + fail +oke: + set_icc 0xe 2 + bnv icc2,2,bad + set_icc 0xf 3 + bnv icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bnvlr.cgs b/sim/testsuite/sim/frv/bnvlr.cgs new file mode 100644 index 00000000000..de40f9cf5fb --- /dev/null +++ b/sim/testsuite/sim/frv/bnvlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bnvlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bnvlr +bnvlr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bnvlr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bnvlr icc1,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bnvlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bnvlr icc3,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bnvlr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bnvlr icc1,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bnvlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bnvlr icc3,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bnvlr icc0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bnvlr icc1,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bnvlr icc2,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bnvlr icc3,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bnvlr icc0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bnvlr icc1,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bnvlr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bnvlr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bp.cgs b/sim/testsuite/sim/frv/bp.cgs new file mode 100644 index 00000000000..0bc1e7fb8b9 --- /dev/null +++ b/sim/testsuite/sim/frv/bp.cgs @@ -0,0 +1,61 @@ +# frv testcase for bp $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bp +bp: + set_icc 0x0 0 + bp icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bp icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bp icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + bp icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + bp icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + bp icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + bp icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + bp icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + bp icc0,0,bad + set_icc 0x9 1 + bp icc1,1,bad + set_icc 0xa 2 + bp icc2,2,bad + set_icc 0xb 3 + bp icc3,3,bad + set_icc 0xc 0 + bp icc0,0,bad + set_icc 0xd 1 + bp icc1,1,bad + set_icc 0xe 2 + bp icc2,2,bad + set_icc 0xf 3 + bp icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bplr.cgs b/sim/testsuite/sim/frv/bplr.cgs new file mode 100644 index 00000000000..2bd9bb6ec67 --- /dev/null +++ b/sim/testsuite/sim/frv/bplr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bplr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bplr +bplr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bplr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bplr icc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bplr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bplr icc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bplr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bplr icc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bplr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bplr icc3,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bplr icc0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bplr icc1,1 + + set_spr_addr bad,lr + set_icc 0xa 2 + bplr icc2,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bplr icc3,3 + + set_spr_addr bad,lr + set_icc 0xc 0 + bplr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bplr icc1,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bplr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bplr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bra.cgs b/sim/testsuite/sim/frv/bra.cgs new file mode 100644 index 00000000000..e6b312b1372 --- /dev/null +++ b/sim/testsuite/sim/frv/bra.cgs @@ -0,0 +1,75 @@ +# frv testcase for bra $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bra +bra: + set_icc 0x0 0 + bra ok1 + fail +ok1: + set_icc 0x1 1 + bra ok2 + fail +ok2: + set_icc 0x2 2 + bra ok3 + fail +ok3: + set_icc 0x3 3 + bra ok4 + fail +ok4: + set_icc 0x4 0 + bra ok5 + fail +ok5: + set_icc 0x5 1 + bra ok6 + fail +ok6: + set_icc 0x6 2 + bra ok7 + fail +ok7: + set_icc 0x7 3 + bra ok8 + fail +ok8: + set_icc 0x8 0 + bra ok9 + fail +ok9: + set_icc 0x9 1 + bra oka + fail +oka: + set_icc 0xa 2 + bra okb + fail +okb: + set_icc 0xb 3 + bra okc + fail +okc: + set_icc 0xc 0 + bra okd + fail +okd: + set_icc 0xd 1 + bra oke + fail +oke: + set_icc 0xe 2 + bra okf + fail +okf: + set_icc 0xf 3 + bra okg + fail +okg: + + pass diff --git a/sim/testsuite/sim/frv/bralr.cgs b/sim/testsuite/sim/frv/bralr.cgs new file mode 100644 index 00000000000..39282099947 --- /dev/null +++ b/sim/testsuite/sim/frv/bralr.cgs @@ -0,0 +1,91 @@ +# frv testcase for bralr +# mach: all + + .include "testutils.inc" + + start + + .global bralr +bralr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bralr + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bralr + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bralr + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bralr + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bralr + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bralr + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bralr + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bralr + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + bralr + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bralr + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bralr + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bralr + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + bralr + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bralr + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bralr + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bralr + fail +okg: + + pass diff --git a/sim/testsuite/sim/frv/branch.pcgs b/sim/testsuite/sim/frv/branch.pcgs new file mode 100644 index 00000000000..42b49e7f8a1 --- /dev/null +++ b/sim/testsuite/sim/frv/branch.pcgs @@ -0,0 +1,63 @@ +# frv parallel testcase for branching +# mach: fr500 frv + + .include "testutils.inc" + + start + + .global branch +branch: ; All insns in VLIW execute + setlos.p 1,gr1 + setlos 0,gr2 + setlos.p 0,gr3 + bra ok1 + setlos.p 2,gr2 + setlos 3,gr3 + fail +ok1: + test_gr_immed 1,gr1 + test_gr_immed 0,gr2 + test_gr_immed 0,gr3 + + ; 1st branch is taken + bra.p ok5 + bra ok4 + bra.p ok3 + bra ok2 + fail +ok2: + fail +ok3: + fail +ok4: + fail +ok5: + ; 1st true branch is taken + set_icc 0x4 1 + bne.p icc1,1,ok6 + blt icc1,1,ok7 + beq.p icc1,1,ok9 + ble icc1,1,ok8 + fail +ok6: + fail +ok7: + fail +ok8: + fail +ok9: + ; combination of the above + set_icc 0x4 1 + setlos.p 4,gr4 + setlos.p 0,gr5 + bne.p icc1,1,oka + beq icc1,1,okb + setlos 5,gr5 + fail +oka: + fail +okb: + test_gr_immed 4,gr4 + test_gr_immed 0,gr5 + + pass diff --git a/sim/testsuite/sim/frv/break.cgs b/sim/testsuite/sim/frv/break.cgs new file mode 100644 index 00000000000..b2a61a05be0 --- /dev/null +++ b/sim/testsuite/sim/frv/break.cgs @@ -0,0 +1,58 @@ +# FRV testcase for break +# mach: all + + .include "testutils.inc" + + start + + .global tra +tra: + ; Can't test break anymore in the user environment because it is the + ; debugger's breakpoint insn. Just pass this test for now. + pass + + + + + + set_gr_spr tbr,gr7 + and_gr_immed -4081,gr7 ; clear tbr.tt + inc_gr_immed 0xff0,gr7 ; break handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + + test_spr_bits 0x4,2,0x1,psr ; psr.s is set + test_spr_bits 0x1,0,0x0,psr ; psr.et is clear + set_spr_addr ok1,lr + break +ret: + or_spr_immed 0x00000001,psr ; turn on psr.et + and_spr_immed 0xfffffffb,psr ; turn off psr.s + test_spr_bits 0x4,2,0x0,psr ; psr.s is clear + test_spr_bits 0x1,0,0x1,psr ; psr.et is set + set_spr_addr ok0,lr + break +ret1: + test_spr_bits 0x4,2,0x0,psr ; psr.s is clear + test_spr_bits 0x1,0,0x1,psr ; psr.et is set + pass + + ; check interrupt for second break +ok0: test_spr_addr ret1,bpcsr + test_spr_bits 0x1000,12,0x0,bpsr ; bpsr.bs is clear + test_spr_bits 0x0001,0,0x1,bpsr ; bpsr.et is set + test_spr_bits 0x4,2,0x1,psr ; psr.s is set + test_spr_bits 0x1,0,0x0,psr ; psr.et is clear + rett 0 ; nop + rett 1 + + ; check interrupt for first break +ok1: test_spr_addr ret,bpcsr + test_spr_bits 0x1000,12,0x1,bpsr ; bpsr.bs is set + test_spr_bits 0x0001,0,0x0,bpsr ; bpsr.et is clear + test_spr_bits 0x4,2,0x1,psr ; psr.s is set + test_spr_bits 0x1,0,0x0,psr ; psr.et is clear + rett 0 ; nop + rett 1 + + diff --git a/sim/testsuite/sim/frv/bv.cgs b/sim/testsuite/sim/frv/bv.cgs new file mode 100644 index 00000000000..e2f8174063f --- /dev/null +++ b/sim/testsuite/sim/frv/bv.cgs @@ -0,0 +1,61 @@ +# frv testcase for bv $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bv +bv: + set_icc 0x0 0 + bv icc0,0,bad + set_icc 0x1 1 + bv icc1,1,bad + set_icc 0x2 2 + bv icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + bv icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + bv icc0,0,bad + set_icc 0x5 1 + bv icc1,1,bad + set_icc 0x6 2 + bv icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + bv icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + bv icc0,0,bad + set_icc 0x9 1 + bv icc1,1,bad + set_icc 0xa 2 + bv icc2,2,okb + fail +okb: + set_icc 0xb 3 + bv icc3,3,okc + fail +okc: + set_icc 0xc 0 + bv icc0,0,bad + set_icc 0xd 1 + bv icc1,1,bad + set_icc 0xe 2 + bv icc2,2,okf + fail +okf: + set_icc 0xf 3 + bv icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bvlr.cgs b/sim/testsuite/sim/frv/bvlr.cgs new file mode 100644 index 00000000000..b7ba9d88ac5 --- /dev/null +++ b/sim/testsuite/sim/frv/bvlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bvlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bvlr +bvlr: + set_spr_addr bad,lr + set_icc 0x0 0 + bvlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bvlr icc1,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bvlr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bvlr icc3,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bvlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bvlr icc1,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bvlr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bvlr icc3,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bvlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bvlr icc1,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bvlr icc2,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bvlr icc3,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bvlr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bvlr icc1,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bvlr icc2,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bvlr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/cadd.cgs b/sim/testsuite/sim/frv/cadd.cgs new file mode 100644 index 00000000000..291b8fb6675 --- /dev/null +++ b/sim/testsuite/sim/frv/cadd.cgs @@ -0,0 +1,90 @@ +# frv testcase for cadd $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cadd +cadd: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc4,1 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc4,1 + test_gr_limmed 0x8000,0x0000,gr8 + + cadd gr8,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc4,0 + test_gr_immed 1,gr8 + + cadd gr8,gr8,gr8,cc4,0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc5,0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc5,0 + test_gr_limmed 0x8000,0x0000,gr8 + + cadd gr8,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc5,1 + test_gr_immed 1,gr8 + + cadd gr8,gr8,gr8,cc5,1 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc6,1 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc6,0 + test_gr_immed 1,gr8 + + cadd gr8,gr8,gr8,cc6,1 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc7,0 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc7,1 + test_gr_immed 1,gr8 + + cadd gr8,gr8,gr8,cc7,0 + test_gr_immed 1,gr8 + + pass diff --git a/sim/testsuite/sim/frv/caddcc.cgs b/sim/testsuite/sim/frv/caddcc.cgs new file mode 100644 index 00000000000..ddfd41e359b --- /dev/null +++ b/sim/testsuite/sim/frv/caddcc.cgs @@ -0,0 +1,163 @@ +# frv testcase for caddcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global caddcc +caddcc: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x08,0 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc4,1; test zero, carry and overflow bits + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_immed 1,gr8 + + set_icc 0x08,0 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc4,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc4,0; test zero, carry and overflow bits + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x08,1 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc5,0; test zero, carry and overflow bits + test_icc 0 1 1 1 icc1 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_immed 1,gr8 + + set_icc 0x08,1 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc5,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc5,1; test zero, carry and overflow bits + test_icc 1 0 0 0 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_immed 1,gr8 + + set_icc 0x08,2 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc6,1 + test_icc 1 0 0 0 icc2 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc6,1; test zero, carry and overflow bits + test_icc 1 0 0 0 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_immed 1,gr8 + + set_icc 0x08,3 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc7,1 + test_icc 1 0 0 0 icc3 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc7,1; test zero, carry and overflow bits + test_icc 1 0 0 0 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + + pass diff --git a/sim/testsuite/sim/frv/call.cgs b/sim/testsuite/sim/frv/call.cgs new file mode 100644 index 00000000000..5f0d7677bcc --- /dev/null +++ b/sim/testsuite/sim/frv/call.cgs @@ -0,0 +1,17 @@ +# frv testcase for call $label24 +# mach: all + + .include "testutils.inc" + + start + + .global call +call: + set_spr_immed 0,lr + call ok1 +bad1: + fail +ok1: + test_spr_addr bad1,lr + + pass diff --git a/sim/testsuite/sim/frv/call.pcgs b/sim/testsuite/sim/frv/call.pcgs new file mode 100644 index 00000000000..16792fa8c79 --- /dev/null +++ b/sim/testsuite/sim/frv/call.pcgs @@ -0,0 +1,30 @@ +# frv parallel testcase for call $label24 +# mach: fr500 frv + + .include "testutils.inc" + + start + + .global call +call: + set_spr_immed 0,lr + call ok1 +bad1: + fail +ok1: + test_spr_addr bad1,lr + + set_spr_immed 0,lr + setlos.p 0,gr5 + call.p ok2 + bra bad3 +bad2: + setlos 5,gr5 + fail +bad3: + fail +ok2: + test_spr_addr bad2,lr + test_gr_immed 0,gr5 + + pass diff --git a/sim/testsuite/sim/frv/callil.cgs b/sim/testsuite/sim/frv/callil.cgs new file mode 100644 index 00000000000..eac63e86a49 --- /dev/null +++ b/sim/testsuite/sim/frv/callil.cgs @@ -0,0 +1,26 @@ +# frv testcase for callil @($GRi,$d12),$LI +# mach: all + + .include "testutils.inc" + + start + + .global callil +callil: + set_gr_addr ok2,gr8 + inc_gr_immed -2047,gr8 + callil @(gr8,0x7ff) +bad2: + fail +ok2: + test_spr_addr bad2,lr + + set_gr_addr ok3,gr8 + inc_gr_immed 2048,gr8 + callil @(gr8,-2048) +bad3: + fail +ok3: + test_spr_addr bad3,lr + + pass diff --git a/sim/testsuite/sim/frv/calll.cgs b/sim/testsuite/sim/frv/calll.cgs new file mode 100644 index 00000000000..eee73bc2a97 --- /dev/null +++ b/sim/testsuite/sim/frv/calll.cgs @@ -0,0 +1,28 @@ +# frv testcase for calll @($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global calll +calll: + set_gr_addr ok2,gr8 + inc_gr_immed -4,gr8 + inc_gr_immed 4,gr9 + calll @(gr8,gr9) +bad2: + fail +ok2: + test_spr_addr bad2,lr + + set_gr_addr ok3,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + calll @(gr8,gr9) +bad3: + fail +ok3: + test_spr_addr bad3,lr + + pass diff --git a/sim/testsuite/sim/frv/cand.cgs b/sim/testsuite/sim/frv/cand.cgs new file mode 100644 index 00000000000..6113593c24f --- /dev/null +++ b/sim/testsuite/sim/frv/cand.cgs @@ -0,0 +1,126 @@ +# frv testcase for cand $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global cand +cand: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc0,1 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc0,1 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc4,1 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x0000,0xaaaa,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc0,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc4,0 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc1,0 + test_icc 1 0 1 1 icc1 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc1,0 + test_icc 0 1 0 0 icc1 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc5,0 + test_icc 1 1 0 1 icc1 + test_gr_limmed 0x0000,0xaaaa,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc1,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 0 icc1 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc5,1 + test_icc 1 1 0 1 icc1 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,2 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc2,0 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,2 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc2,0 + test_icc 0 1 0 0 icc2 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc6,1 + test_icc 1 1 0 1 icc2 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,3 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc3,0 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,3 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc3,0 + test_icc 0 1 0 0 icc3 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc7,1 + test_icc 1 1 0 1 icc3 + test_gr_limmed 0x0000,0xffff,gr8 + + pass diff --git a/sim/testsuite/sim/frv/candcc.cgs b/sim/testsuite/sim/frv/candcc.cgs new file mode 100644 index 00000000000..c16df73ec29 --- /dev/null +++ b/sim/testsuite/sim/frv/candcc.cgs @@ -0,0 +1,126 @@ +# frv testcase for candcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global candcc +candcc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc0,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x0000,0xaaaa,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc4,0 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc1,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 0 1 icc1 + test_gr_limmed 0x0000,0xaaaa,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 0 icc1 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc5,1 + test_icc 1 1 0 1 icc1 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,2 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc2,0 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,2 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 0 0 icc2 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc6,1 + test_icc 1 1 0 1 icc2 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,3 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc3,0 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,3 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 0 0 icc3 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc7,1 + test_icc 1 1 0 1 icc3 + test_gr_limmed 0x0000,0xffff,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ccalll.cgs b/sim/testsuite/sim/frv/ccalll.cgs new file mode 100644 index 00000000000..dcfd300079c --- /dev/null +++ b/sim/testsuite/sim/frv/ccalll.cgs @@ -0,0 +1,101 @@ +# frv testcase for ccalll @($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global ccalll +ccalll: + set_spr_immed 0x1b1b,cccr + + set_gr_addr ok2,gr8 + inc_gr_immed -4,gr8 + inc_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc0,1 +bad2: + fail +ok2: + test_spr_addr bad2,lr + + set_gr_addr ok3,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc4,1 +bad3: + fail +ok3: + test_spr_addr bad3,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc0,0 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc4,0 + test_spr_addr 0,lr + + set_gr_addr ok5,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc1,0 +bad5: + fail +ok5: + test_spr_addr bad5,lr + + set_gr_addr ok6,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc5,0 +bad6: + fail +ok6: + test_spr_addr bad6,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc1,1 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc5,1 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc2,1 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc6,0 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc3,0 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc7,1 + test_spr_addr 0,lr + + pass +bad: + fail + diff --git a/sim/testsuite/sim/frv/cckc.cgs b/sim/testsuite/sim/frv/cckc.cgs new file mode 100644 index 00000000000..70eabee5ce9 --- /dev/null +++ b/sim/testsuite/sim/frv/cckc.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckc $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckc +cckc: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckeq.cgs b/sim/testsuite/sim/frv/cckeq.cgs new file mode 100644 index 00000000000..2c86f1858d5 --- /dev/null +++ b/sim/testsuite/sim/frv/cckeq.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckeq $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckeq +cckeq: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckge.cgs b/sim/testsuite/sim/frv/cckge.cgs new file mode 100644 index 00000000000..6938f1e8e67 --- /dev/null +++ b/sim/testsuite/sim/frv/cckge.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckge $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckge +cckge: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckgt.cgs b/sim/testsuite/sim/frv/cckgt.cgs new file mode 100644 index 00000000000..e0745dd4433 --- /dev/null +++ b/sim/testsuite/sim/frv/cckgt.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckgt $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckgt +cckgt: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckhi.cgs b/sim/testsuite/sim/frv/cckhi.cgs new file mode 100644 index 00000000000..4741f5ac3a4 --- /dev/null +++ b/sim/testsuite/sim/frv/cckhi.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckhi $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckhi +cckhi: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckle.cgs b/sim/testsuite/sim/frv/cckle.cgs new file mode 100644 index 00000000000..9d8821414f7 --- /dev/null +++ b/sim/testsuite/sim/frv/cckle.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckle $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckle +cckle: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckls.cgs b/sim/testsuite/sim/frv/cckls.cgs new file mode 100644 index 00000000000..a78b7799add --- /dev/null +++ b/sim/testsuite/sim/frv/cckls.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckls $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckls +cckls: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ccklt.cgs b/sim/testsuite/sim/frv/ccklt.cgs new file mode 100644 index 00000000000..c14c6328694 --- /dev/null +++ b/sim/testsuite/sim/frv/ccklt.cgs @@ -0,0 +1,490 @@ +# frv testcase for ccklt $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global ccklt +ccklt: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckn.cgs b/sim/testsuite/sim/frv/cckn.cgs new file mode 100644 index 00000000000..d4231246d8d --- /dev/null +++ b/sim/testsuite/sim/frv/cckn.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckn $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckn +cckn: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ccknc.cgs b/sim/testsuite/sim/frv/ccknc.cgs new file mode 100644 index 00000000000..0478f271ec5 --- /dev/null +++ b/sim/testsuite/sim/frv/ccknc.cgs @@ -0,0 +1,490 @@ +# frv testcase for ccknc $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global ccknc +ccknc: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckne.cgs b/sim/testsuite/sim/frv/cckne.cgs new file mode 100644 index 00000000000..d8af1e34cf6 --- /dev/null +++ b/sim/testsuite/sim/frv/cckne.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckne $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckne +cckne: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckno.cgs b/sim/testsuite/sim/frv/cckno.cgs new file mode 100644 index 00000000000..8c3c9274183 --- /dev/null +++ b/sim/testsuite/sim/frv/cckno.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckno $CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckno +cckno: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ccknv.cgs b/sim/testsuite/sim/frv/ccknv.cgs new file mode 100644 index 00000000000..333edca9d83 --- /dev/null +++ b/sim/testsuite/sim/frv/ccknv.cgs @@ -0,0 +1,490 @@ +# frv testcase for ccknv $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global ccknv +ccknv: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckp.cgs b/sim/testsuite/sim/frv/cckp.cgs new file mode 100644 index 00000000000..53570d98905 --- /dev/null +++ b/sim/testsuite/sim/frv/cckp.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckp $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckp +cckp: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckra.cgs b/sim/testsuite/sim/frv/cckra.cgs new file mode 100644 index 00000000000..c0b27fca15b --- /dev/null +++ b/sim/testsuite/sim/frv/cckra.cgs @@ -0,0 +1,480 @@ +# frv testcase for cckra $CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckra +cckra: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckv.cgs b/sim/testsuite/sim/frv/cckv.cgs new file mode 100644 index 00000000000..9ebb6e353a4 --- /dev/null +++ b/sim/testsuite/sim/frv/cckv.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckv $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckv +cckv: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ccmp.cgs b/sim/testsuite/sim/frv/ccmp.cgs new file mode 100644 index 00000000000..52d5310499e --- /dev/null +++ b/sim/testsuite/sim/frv/ccmp.cgs @@ -0,0 +1,134 @@ +# frv testcase for ccmp $GRi,$GRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global ccmp +ccmp: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc0,1 + test_icc 0 0 0 0 icc0 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc0,1 + test_icc 0 0 1 0 icc0 + + set_icc 0x0b,0 ; Set mask opposite of expected + ccmp gr8,gr8,cc4,1 + test_icc 0 1 0 0 icc0 + + set_gr_immed 0,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc4,1 + test_icc 1 0 0 1 icc0 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc0,0 + test_icc 1 1 1 1 icc0 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc0,0 + test_icc 1 1 0 1 icc0 + + set_icc 0x0b,0 ; Set mask opposite of expected + ccmp gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + + set_icc 0x06,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc4,0 + test_icc 0 1 1 0 icc0 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc1,0 + test_icc 0 0 0 0 icc1 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc1,0 + test_icc 0 0 1 0 icc1 + + set_icc 0x0b,1 ; Set mask opposite of expected + ccmp gr8,gr8,cc5,0 + test_icc 0 1 0 0 icc1 + + set_gr_immed 0,gr8 + set_icc 0x06,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc5,0 + test_icc 1 0 0 1 icc1 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc1,1 + test_icc 1 1 1 1 icc1 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc1,1 + test_icc 1 1 0 1 icc1 + + set_icc 0x0b,1 ; Set mask opposite of expected + ccmp gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + + set_icc 0x06,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc5,1 + test_icc 0 1 1 0 icc1 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + ccmp gr8,gr7,cc2,0 + test_icc 1 1 1 1 icc2 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + ccmp gr8,gr7,cc2,0 + test_icc 1 1 0 1 icc2 + + set_icc 0x0b,2 ; Set mask opposite of expected + ccmp gr8,gr8,cc6,1 + test_icc 1 0 1 1 icc2 + + set_icc 0x06,2 ; Set mask opposite of expected + ccmp gr8,gr7,cc6,1 + test_icc 0 1 1 0 icc2 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + ccmp gr8,gr7,cc3,0 + test_icc 1 1 1 1 icc3 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + ccmp gr8,gr7,cc3,0 + test_icc 1 1 0 1 icc3 + + set_icc 0x0b,3 ; Set mask opposite of expected + ccmp gr8,gr8,cc7,1 + test_icc 1 0 1 1 icc3 + + set_icc 0x06,3 ; Set mask opposite of expected + ccmp gr8,gr7,cc7,1 + test_icc 0 1 1 0 icc3 + + pass diff --git a/sim/testsuite/sim/frv/cfabss.cgs b/sim/testsuite/sim/frv/cfabss.cgs new file mode 100644 index 00000000000..894b331008b --- /dev/null +++ b/sim/testsuite/sim/frv/cfabss.cgs @@ -0,0 +1,96 @@ +# frv testcase for cfabss $FRj,$FRk,$CCi,$cond +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfabss +cfabss: + set_spr_immed 0x1b1b,cccr + + cfabss fr0,fr1,cc0,1 + test_fr_fr fr1,fr52 + cfabss fr8,fr1,cc0,1 + test_fr_fr fr1,fr28 + cfabss fr12,fr1,cc0,1 + test_fr_fr fr1,fr24 + cfabss fr24,fr1,cc4,1 + test_fr_fr fr1,fr24 + cfabss fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + cfabss fr52,fr1,cc4,1 + test_fr_fr fr1,fr52 + + cfabss fr0,fr1,cc1,0 + test_fr_fr fr1,fr52 + cfabss fr8,fr1,cc1,0 + test_fr_fr fr1,fr28 + cfabss fr12,fr1,cc1,0 + test_fr_fr fr1,fr24 + cfabss fr24,fr1,cc5,0 + test_fr_fr fr1,fr24 + cfabss fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + cfabss fr52,fr1,cc5,0 + test_fr_fr fr1,fr52 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfabss fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfabss fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfabss fr0,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr8,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr12,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr24,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr28,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr52,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfabss fr0,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr24,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr28,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr52,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/cfadds.cgs b/sim/testsuite/sim/frv/cfadds.cgs new file mode 100644 index 00000000000..248c3266cba --- /dev/null +++ b/sim/testsuite/sim/frv/cfadds.cgs @@ -0,0 +1,456 @@ +# frv testcase for cfadds $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfadds +cfadds: + set_spr_immed 0x1b1b,cccr + + cfadds fr16,fr0,fr1,cc0,1 + test_fr_fr fr1,fr0 + cfadds fr16,fr4,fr1,cc0,1 + test_fr_fr fr1,fr4 + cfadds fr16,fr8,fr1,cc0,1 + test_fr_fr fr1,fr8 + cfadds fr16,fr12,fr1,cc0,1 + test_fr_fr fr1,fr12 + cfadds fr16,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr16,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr16,fr24,fr1,cc0,1 + test_fr_fr fr1,fr24 + cfadds fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr28 + cfadds fr16,fr32,fr1,cc0,1 + test_fr_fr fr1,fr32 + cfadds fr16,fr36,fr1,cc0,1 + test_fr_fr fr1,fr36 + cfadds fr16,fr40,fr1,cc0,1 + test_fr_fr fr1,fr40 + cfadds fr16,fr44,fr1,cc0,1 + test_fr_fr fr1,fr44 + cfadds fr16,fr48,fr1,cc0,1 + test_fr_fr fr1,fr48 + cfadds fr16,fr52,fr1,cc0,1 + test_fr_fr fr1,fr52 + + cfadds fr20,fr0,fr1,cc0,1 + test_fr_fr fr1,fr0 + cfadds fr20,fr4,fr1,cc0,1 + test_fr_fr fr1,fr4 + cfadds fr20,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfadds fr20,fr12,fr1,cc4,1 + test_fr_fr fr1,fr12 + cfadds fr20,fr16,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr20,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr20,fr24,fr1,cc4,1 + test_fr_fr fr1,fr24 + cfadds fr20,fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + cfadds fr20,fr32,fr1,cc4,1 + test_fr_fr fr1,fr32 + cfadds fr20,fr36,fr1,cc4,1 + test_fr_fr fr1,fr36 + cfadds fr20,fr40,fr1,cc4,1 + test_fr_fr fr1,fr40 + cfadds fr20,fr44,fr1,cc4,1 + test_fr_fr fr1,fr44 + cfadds fr20,fr48,fr1,cc4,1 + test_fr_fr fr1,fr48 + cfadds fr20,fr52,fr1,cc4,1 + test_fr_fr fr1,fr52 + + cfadds fr8,fr28,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr12,fr24,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr24,fr12,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfadds fr36,fr40,fr1,cc4,1 + test_fr_fr fr1,fr44 + + cfadds fr16,fr0,fr1,cc1,0 + test_fr_fr fr1,fr0 + cfadds fr16,fr4,fr1,cc1,0 + test_fr_fr fr1,fr4 + cfadds fr16,fr8,fr1,cc1,0 + test_fr_fr fr1,fr8 + cfadds fr16,fr12,fr1,cc1,0 + test_fr_fr fr1,fr12 + cfadds fr16,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr16,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr16,fr24,fr1,cc1,0 + test_fr_fr fr1,fr24 + cfadds fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr28 + cfadds fr16,fr32,fr1,cc1,0 + test_fr_fr fr1,fr32 + cfadds fr16,fr36,fr1,cc1,0 + test_fr_fr fr1,fr36 + cfadds fr16,fr40,fr1,cc1,0 + test_fr_fr fr1,fr40 + cfadds fr16,fr44,fr1,cc1,0 + test_fr_fr fr1,fr44 + cfadds fr16,fr48,fr1,cc1,0 + test_fr_fr fr1,fr48 + cfadds fr16,fr52,fr1,cc1,0 + test_fr_fr fr1,fr52 + + cfadds fr20,fr0,fr1,cc1,0 + test_fr_fr fr1,fr0 + cfadds fr20,fr4,fr1,cc1,0 + test_fr_fr fr1,fr4 + cfadds fr20,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfadds fr20,fr12,fr1,cc5,0 + test_fr_fr fr1,fr12 + cfadds fr20,fr16,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr20,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr20,fr24,fr1,cc5,0 + test_fr_fr fr1,fr24 + cfadds fr20,fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + cfadds fr20,fr32,fr1,cc5,0 + test_fr_fr fr1,fr32 + cfadds fr20,fr36,fr1,cc5,0 + test_fr_fr fr1,fr36 + cfadds fr20,fr40,fr1,cc5,0 + test_fr_fr fr1,fr40 + cfadds fr20,fr44,fr1,cc5,0 + test_fr_fr fr1,fr44 + cfadds fr20,fr48,fr1,cc5,0 + test_fr_fr fr1,fr48 + cfadds fr20,fr52,fr1,cc5,0 + test_fr_fr fr1,fr52 + + cfadds fr8,fr28,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr12,fr24,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr24,fr12,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfadds fr36,fr40,fr1,cc5,0 + test_fr_fr fr1,fr44 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfadds fr16,fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr24,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr32,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr36,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr40,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr44,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr48,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr52,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr20,fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr12,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr16,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr8,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr12,fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr24,fr12,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr28,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr36,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfadds fr16,fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr24,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr32,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr36,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr40,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr44,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr48,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr52,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr20,fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr12,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr16,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr8,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr12,fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr24,fr12,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr28,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr36,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfadds fr16,fr0,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr4,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr8,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr12,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr20,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr24,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr32,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr36,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr40,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr44,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr48,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr52,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr20,fr0,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr4,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr8,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr12,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr16,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr24,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr28,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr32,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr36,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr40,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr44,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr48,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr52,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr8,fr28,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr12,fr24,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr24,fr12,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr28,fr8,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr36,fr40,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfadds fr16,fr0,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr4,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr20,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr24,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr32,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr36,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr40,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr44,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr48,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr52,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr20,fr0,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr4,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr8,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr12,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr16,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr24,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr28,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr32,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr36,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr40,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr44,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr48,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr52,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr8,fr28,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr12,fr24,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr24,fr12,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr28,fr8,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr36,fr40,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass + + diff --git a/sim/testsuite/sim/frv/cfckeq.cgs b/sim/testsuite/sim/frv/cfckeq.cgs new file mode 100644 index 00000000000..467568af55e --- /dev/null +++ b/sim/testsuite/sim/frv/cfckeq.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckeq $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckeq +cfckeq: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckge.cgs b/sim/testsuite/sim/frv/cfckge.cgs new file mode 100644 index 00000000000..ba2de9510e7 --- /dev/null +++ b/sim/testsuite/sim/frv/cfckge.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckge $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckge +cfckge: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckgt.cgs b/sim/testsuite/sim/frv/cfckgt.cgs new file mode 100644 index 00000000000..7858c1772a6 --- /dev/null +++ b/sim/testsuite/sim/frv/cfckgt.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckgt $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckgt +cfckgt: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckle.cgs b/sim/testsuite/sim/frv/cfckle.cgs new file mode 100644 index 00000000000..fb2b1b85e13 --- /dev/null +++ b/sim/testsuite/sim/frv/cfckle.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckle $FCCi,$CCj_float$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckle +cfckle: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfcklg.cgs b/sim/testsuite/sim/frv/cfcklg.cgs new file mode 100644 index 00000000000..22deb52f38d --- /dev/null +++ b/sim/testsuite/sim/frv/cfcklg.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfcklg $FCCi,$CCj_float$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfcklg +cfcklg: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfcklt.cgs b/sim/testsuite/sim/frv/cfcklt.cgs new file mode 100644 index 00000000000..ffabcd2628b --- /dev/null +++ b/sim/testsuite/sim/frv/cfcklt.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfcklt $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfcklt +cfcklt: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckne.cgs b/sim/testsuite/sim/frv/cfckne.cgs new file mode 100644 index 00000000000..da6846fa30e --- /dev/null +++ b/sim/testsuite/sim/frv/cfckne.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckne $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckne +cfckne: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckno.cgs b/sim/testsuite/sim/frv/cfckno.cgs new file mode 100644 index 00000000000..56819604070 --- /dev/null +++ b/sim/testsuite/sim/frv/cfckno.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckno $CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckno +cfckno: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfcko.cgs b/sim/testsuite/sim/frv/cfcko.cgs new file mode 100644 index 00000000000..ac55fc3e7ac --- /dev/null +++ b/sim/testsuite/sim/frv/cfcko.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfcko $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfcko +cfcko: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckra.cgs b/sim/testsuite/sim/frv/cfckra.cgs new file mode 100644 index 00000000000..0cabd8f47c1 --- /dev/null +++ b/sim/testsuite/sim/frv/cfckra.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckra $CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckra +cfckra: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfcku.cgs b/sim/testsuite/sim/frv/cfcku.cgs new file mode 100644 index 00000000000..0f56e7e74c6 --- /dev/null +++ b/sim/testsuite/sim/frv/cfcku.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfcku $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfcku +cfcku: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckue.cgs b/sim/testsuite/sim/frv/cfckue.cgs new file mode 100644 index 00000000000..447c2bac3ed --- /dev/null +++ b/sim/testsuite/sim/frv/cfckue.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckue $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckue +cfckue: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckug.cgs b/sim/testsuite/sim/frv/cfckug.cgs new file mode 100644 index 00000000000..7442f84a457 --- /dev/null +++ b/sim/testsuite/sim/frv/cfckug.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckug $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckug +cfckug: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckuge.cgs b/sim/testsuite/sim/frv/cfckuge.cgs new file mode 100644 index 00000000000..8eaf92fd406 --- /dev/null +++ b/sim/testsuite/sim/frv/cfckuge.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckuge $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckuge +cfckuge: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckul.cgs b/sim/testsuite/sim/frv/cfckul.cgs new file mode 100644 index 00000000000..5945a8a7ce0 --- /dev/null +++ b/sim/testsuite/sim/frv/cfckul.cgs @@ -0,0 +1,410 @@ +# frv testcase for cfckul $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckul +cfckul: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckule.cgs b/sim/testsuite/sim/frv/cfckule.cgs new file mode 100644 index 00000000000..aaf655e8430 --- /dev/null +++ b/sim/testsuite/sim/frv/cfckule.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckule $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckule +cfckule: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfcmps.cgs b/sim/testsuite/sim/frv/cfcmps.cgs new file mode 100644 index 00000000000..aba22a5d27a --- /dev/null +++ b/sim/testsuite/sim/frv/cfcmps.cgs @@ -0,0 +1,3542 @@ +# frv testcase for cfcmps $FRi,$FRj,$FCCi,$CCi,$cond_2 +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfcmps +cfcmps: + set_spr_immed 0x1b1b,cccr + + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc4,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc4,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc4,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc4,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc4,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc4,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc4,1 + test_fcc 0x8,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc4,1 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc4,1 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc4,1 + test_fcc 0x1,0 +; + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc5,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc5,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc5,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc5,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc5,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc5,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc5,0 + test_fcc 0x8,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc5,0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc5,0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc5,0 + test_fcc 0x1,0 +; + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc4,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc4,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc4,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc4,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc4,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc4,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc4,0 + test_fcc 0x7,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc4,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc4,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc4,0 + test_fcc 0xe,0 +; + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc5,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc5,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc5,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc5,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc5,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc5,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc5,1 + test_fcc 0x7,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc5,1 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc5,1 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc5,1 + test_fcc 0xe,0 +; + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc2,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc2,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc2,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc2,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc2,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc2,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc2,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc2,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc6,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc6,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc6,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc6,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc6,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc6,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc6,0 + test_fcc 0x7,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc6,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc6,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc6,1 + test_fcc 0xe,0 + + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc3,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc3,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc3,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc3,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc3,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc3,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc3,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc3,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc7,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc7,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc7,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc7,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc7,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc7,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc7,0 + test_fcc 0x7,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc7,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc7,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc7,1 + test_fcc 0xe,0 + + pass diff --git a/sim/testsuite/sim/frv/cfdivs.cgs b/sim/testsuite/sim/frv/cfdivs.cgs new file mode 100644 index 00000000000..301a946bbc8 --- /dev/null +++ b/sim/testsuite/sim/frv/cfdivs.cgs @@ -0,0 +1,696 @@ +# frv testcase for cfdivs $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfdivs +cfdivs: + set_spr_immed 0x1b1b,cccr + + cfdivs fr0,fr28,fr1,cc0,1 + test_fr_fr fr1,fr0 + cfdivs fr4,fr28,fr1,cc0,1 + test_fr_fr fr1,fr4 + cfdivs fr8,fr28,fr1,cc0,1 + test_fr_fr fr1,fr8 + cfdivs fr12,fr28,fr1,cc0,1 + test_fr_fr fr1,fr12 + cfdivs fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr24,fr28,fr1,cc0,1 + test_fr_fr fr1,fr24 + cfdivs fr28,fr28,fr1,cc0,1 + test_fr_fr fr1,fr28 + cfdivs fr32,fr28,fr1,cc0,1 + test_fr_fr fr1,fr32 + cfdivs fr36,fr28,fr1,cc0,1 + test_fr_fr fr1,fr36 + cfdivs fr40,fr28,fr1,cc0,1 + test_fr_fr fr1,fr40 + cfdivs fr44,fr28,fr1,cc0,1 + test_fr_fr fr1,fr44 + cfdivs fr48,fr28,fr1,cc0,1 + test_fr_fr fr1,fr48 + cfdivs fr52,fr28,fr1,cc0,1 + test_fr_fr fr1,fr52 + + cfdivs fr16,fr0,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr32,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr36,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr40,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr44,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr48,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr52,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfdivs fr20,fr0,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr4,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr8,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr12,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr24,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr28,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr32,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr36,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr40,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr44,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr48,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr52,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfdivs fr8,fr28,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfdivs fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + + cfdivs fr40,fr32,fr1,cc4,1 + test_fr_fr fr1,fr36 +; + cfdivs fr0,fr28,fr1,cc1,0 + test_fr_fr fr1,fr0 + cfdivs fr4,fr28,fr1,cc1,0 + test_fr_fr fr1,fr4 + cfdivs fr8,fr28,fr1,cc1,0 + test_fr_fr fr1,fr8 + cfdivs fr12,fr28,fr1,cc1,0 + test_fr_fr fr1,fr12 + cfdivs fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr24,fr28,fr1,cc1,0 + test_fr_fr fr1,fr24 + cfdivs fr28,fr28,fr1,cc1,0 + test_fr_fr fr1,fr28 + cfdivs fr32,fr28,fr1,cc1,0 + test_fr_fr fr1,fr32 + cfdivs fr36,fr28,fr1,cc1,0 + test_fr_fr fr1,fr36 + cfdivs fr40,fr28,fr1,cc1,0 + test_fr_fr fr1,fr40 + cfdivs fr44,fr28,fr1,cc1,0 + test_fr_fr fr1,fr44 + cfdivs fr48,fr28,fr1,cc1,0 + test_fr_fr fr1,fr48 + cfdivs fr52,fr28,fr1,cc1,0 + test_fr_fr fr1,fr52 + + cfdivs fr16,fr0,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr32,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr36,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr40,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr44,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr48,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr52,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfdivs fr20,fr0,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr4,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr8,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr12,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr24,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr28,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr32,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr36,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr40,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr44,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr48,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr52,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfdivs fr8,fr28,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfdivs fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + + cfdivs fr40,fr32,fr1,cc5,0 + test_fr_fr fr1,fr36 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfdivs fr0,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr4,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr8,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr12,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr24,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr32,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr36,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr40,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr44,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr48,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr52,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr16,fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr24,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr20,fr0,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr4,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr12,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr8,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr40,fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfdivs fr0,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr4,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr8,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr12,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr24,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr32,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr36,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr40,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr44,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr48,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr52,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr16,fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr24,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr20,fr0,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr4,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr12,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr8,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr40,fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfdivs fr0,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr4,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr8,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr12,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr24,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr32,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr36,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr40,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr44,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr48,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr52,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr16,fr0,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr4,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr8,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr12,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr24,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr32,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr36,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr40,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr44,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr48,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr52,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr20,fr0,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr4,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr8,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr12,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr24,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr32,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr36,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr40,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr44,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr48,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr52,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr8,fr28,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr8,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr40,fr32,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfdivs fr0,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr4,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr8,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr12,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr24,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr32,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr36,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr40,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr44,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr48,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr52,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr16,fr0,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr4,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr24,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr32,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr36,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr40,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr44,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr48,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr52,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr20,fr0,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr4,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr8,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr12,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr24,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr32,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr36,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr40,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr44,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr48,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr52,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr8,fr28,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr8,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr40,fr32,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/cfitos.cgs b/sim/testsuite/sim/frv/cfitos.cgs new file mode 100644 index 00000000000..33be4dbb66e --- /dev/null +++ b/sim/testsuite/sim/frv/cfitos.cgs @@ -0,0 +1,88 @@ +# frv testcase for cfitos $FRj,$FRk,$CCi,$cond +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfitos +cfitos: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc0,1 + test_fr_fr fr1,fr32 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc4,1 + test_fr_iimmed 0xce054904,fr1 + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc1,0 + test_fr_fr fr1,fr32 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc5,0 + test_fr_iimmed 0xce054904,fr1 + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc0,0 + test_fr_iimmed 0,fr1 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc0,0 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc1,1 + test_fr_iimmed 0,fr1 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc1,1 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc2,1 + test_fr_iimmed 0,fr1 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc2,0 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc3,0 + test_fr_iimmed 0,fr1 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc3,1 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/cfmadds.cgs b/sim/testsuite/sim/frv/cfmadds.cgs new file mode 100644 index 00000000000..a30f7bfd87d --- /dev/null +++ b/sim/testsuite/sim/frv/cfmadds.cgs @@ -0,0 +1,627 @@ +# frv testcase for cfmadds $GRi,$GRj,$GRk,$CCi,$cond +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfmadds +cfmadds: + set_spr_immed 0x1b1b,cccr + + set_fr_fr fr16,fr1 + cfmadds fr16,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr36,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr40,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr44,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr48,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmadds fr20,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr36,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr40,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr44,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr48,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + cfmadds fr28,fr0,fr1,cc4,1 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + cfmadds fr28,fr4,fr1,cc4,1 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + cfmadds fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + cfmadds fr28,fr12,fr1,cc4,1 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + cfmadds fr28,fr16,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmadds fr28,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmadds fr28,fr24,fr1,cc4,1 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + cfmadds fr28,fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + cfmadds fr28,fr32,fr1,cc4,1 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + cfmadds fr28,fr36,fr1,cc4,1 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + cfmadds fr28,fr40,fr1,cc4,1 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + cfmadds fr28,fr44,fr1,cc4,1 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + cfmadds fr28,fr48,fr1,cc4,1 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + cfmadds fr28,fr52,fr1,cc4,1 + test_fr_fr fr1,fr52 + + set_fr_fr fr36,fr1 + cfmadds fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr32 + cfmadds fr8,fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + + set_fr_fr fr36,fr1 + cfmadds fr32,fr36,fr1,cc4,1 + test_fr_fr fr1,fr44 +; + set_fr_fr fr16,fr1 + cfmadds fr16,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr36,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr40,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr44,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr48,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmadds fr20,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr36,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr40,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr44,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr48,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + cfmadds fr28,fr0,fr1,cc5,0 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + cfmadds fr28,fr4,fr1,cc5,0 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + cfmadds fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + cfmadds fr28,fr12,fr1,cc5,0 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + cfmadds fr28,fr16,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmadds fr28,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmadds fr28,fr24,fr1,cc5,0 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + cfmadds fr28,fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + cfmadds fr28,fr32,fr1,cc5,0 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + cfmadds fr28,fr36,fr1,cc5,0 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + cfmadds fr28,fr40,fr1,cc5,0 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + cfmadds fr28,fr44,fr1,cc5,0 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + cfmadds fr28,fr48,fr1,cc5,0 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + cfmadds fr28,fr52,fr1,cc5,0 + test_fr_fr fr1,fr52 + + set_fr_fr fr36,fr1 + cfmadds fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr32 + cfmadds fr8,fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + + set_fr_fr fr36,fr1 + cfmadds fr32,fr36,fr1,cc5,0 + test_fr_fr fr1,fr44 +; + set_fr_fr fr48,fr1 + cfmadds fr16,fr4,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr8,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr12,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr16,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr20,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr24,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr28,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr32,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr36,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr40,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr44,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr48,fr1,cc0,0 + test_fr_fr fr1,fr48 + + cfmadds fr20,fr4,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr8,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr12,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr16,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr20,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr24,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr28,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr32,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr36,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr40,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr44,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr48,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr0,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr4,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr8,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr12,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr16,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr20,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr24,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr28,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr32,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr36,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr40,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr44,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr48,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr52,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr8,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr8,fr28,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmadds fr32,fr36,fr1,cc4,0 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmadds fr16,fr4,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr8,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr12,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr16,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr20,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr24,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr28,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr32,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr36,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr40,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr44,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr48,fr1,cc1,1 + test_fr_fr fr1,fr48 + + cfmadds fr20,fr4,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr8,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr12,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr16,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr20,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr24,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr28,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr32,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr36,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr40,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr44,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr48,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr0,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr4,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr8,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr12,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr16,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr20,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr24,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr28,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr32,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr36,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr40,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr44,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr48,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr52,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr8,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr8,fr28,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmadds fr32,fr36,fr1,cc5,1 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmadds fr16,fr4,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr8,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr12,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr16,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr20,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr24,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr28,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr32,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr36,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr40,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr44,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr48,fr1,cc2,0 + test_fr_fr fr1,fr48 + + cfmadds fr20,fr4,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr8,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr12,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr16,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr20,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr24,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr28,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr32,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr36,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr40,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr44,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr48,fr1,cc6,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr0,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr4,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr8,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr12,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr16,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr20,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr24,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr28,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr32,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr36,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr40,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr44,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr48,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr52,fr1,cc6,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr8,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr8,fr28,fr1,cc6,0 + test_fr_fr fr1,fr48 + + cfmadds fr32,fr36,fr1,cc6,1 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmadds fr16,fr4,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr8,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr12,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr16,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr20,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr24,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr28,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr32,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr36,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr40,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr44,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr48,fr1,cc3,0 + test_fr_fr fr1,fr48 + + cfmadds fr20,fr4,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr8,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr12,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr16,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr20,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr24,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr28,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr32,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr36,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr40,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr44,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr48,fr1,cc7,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr0,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr4,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr8,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr12,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr16,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr20,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr24,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr28,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr32,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr36,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr40,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr44,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr48,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr52,fr1,cc7,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr8,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr8,fr28,fr1,cc7,0 + test_fr_fr fr1,fr48 + + cfmadds fr32,fr36,fr1,cc7,1 + test_fr_fr fr1,fr48 +; + pass diff --git a/sim/testsuite/sim/frv/cfmas.cgs b/sim/testsuite/sim/frv/cfmas.cgs new file mode 100644 index 00000000000..22a7edbafa2 --- /dev/null +++ b/sim/testsuite/sim/frv/cfmas.cgs @@ -0,0 +1,775 @@ +# frv testcase for cfmas $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global cfmas +cfmas: + set_spr_immed 0x1b1b,cccr + + cfmas fr16,fr4,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + cfmas fr16,fr8,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmas fr16,fr12,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + cfmas fr16,fr16,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr16,fr20,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr16,fr24,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + cfmas fr16,fr28,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmas fr16,fr32,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + cfmas fr16,fr36,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + cfmas fr16,fr40,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + cfmas fr16,fr44,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + cfmas fr16,fr48,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + cfmas fr20,fr4,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + cfmas fr20,fr8,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmas fr20,fr12,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + cfmas fr20,fr16,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr20,fr20,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr20,fr24,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + cfmas fr20,fr28,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmas fr20,fr32,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + cfmas fr20,fr36,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + cfmas fr20,fr40,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + cfmas fr20,fr44,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + cfmas fr20,fr48,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + cfmas fr28,fr0,fr2,cc4,1 + test_fr_fr fr2,fr0 + cfmas fr28,fr4,fr2,cc4,1 + test_fr_fr fr2,fr4 + cfmas fr28,fr8,fr2,cc4,1 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr28,fr12,fr2,cc4,1 + test_fr_fr fr2,fr12 + cfmas fr28,fr16,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmas fr28,fr20,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmas fr28,fr24,fr2,cc4,1 + test_fr_fr fr2,fr24 + cfmas fr28,fr28,fr2,cc4,1 + test_fr_fr fr2,fr28 + cfmas fr28,fr32,fr2,cc4,1 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr36 + cfmas fr28,fr36,fr2,cc4,1 + test_fr_fr fr2,fr36 + cfmas fr28,fr40,fr2,cc4,1 + test_fr_fr fr2,fr40 + cfmas fr28,fr44,fr2,cc4,1 + test_fr_fr fr2,fr44 + cfmas fr28,fr48,fr2,cc4,1 + test_fr_fr fr2,fr48 + cfmas fr28,fr52,fr2,cc4,1 + test_fr_fr fr2,fr52 + + cfmas fr28,fr8,fr2,cc4,1 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr8,fr28,fr2,cc4,1 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + cfmas fr32,fr36,fr2,cc4,1 + test_fr_fr fr2,fr40 +; + cfmas fr16,fr4,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + cfmas fr16,fr8,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmas fr16,fr12,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + cfmas fr16,fr16,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr16,fr20,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr16,fr24,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + cfmas fr16,fr28,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmas fr16,fr32,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + cfmas fr16,fr36,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + cfmas fr16,fr40,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + cfmas fr16,fr44,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + cfmas fr16,fr48,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + cfmas fr20,fr4,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + cfmas fr20,fr8,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmas fr20,fr12,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + cfmas fr20,fr16,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr20,fr20,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr20,fr24,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + cfmas fr20,fr28,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmas fr20,fr32,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + cfmas fr20,fr36,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + cfmas fr20,fr40,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + cfmas fr20,fr44,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + cfmas fr20,fr48,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + cfmas fr28,fr0,fr2,cc5,0 + test_fr_fr fr2,fr0 + cfmas fr28,fr4,fr2,cc5,0 + test_fr_fr fr2,fr4 + cfmas fr28,fr8,fr2,cc5,0 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr28,fr12,fr2,cc5,0 + test_fr_fr fr2,fr12 + cfmas fr28,fr16,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmas fr28,fr20,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmas fr28,fr24,fr2,cc5,0 + test_fr_fr fr2,fr24 + cfmas fr28,fr28,fr2,cc5,0 + test_fr_fr fr2,fr28 + cfmas fr28,fr32,fr2,cc5,0 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr36 + cfmas fr28,fr36,fr2,cc5,0 + test_fr_fr fr2,fr36 + cfmas fr28,fr40,fr2,cc5,0 + test_fr_fr fr2,fr40 + cfmas fr28,fr44,fr2,cc5,0 + test_fr_fr fr2,fr44 + cfmas fr28,fr48,fr2,cc5,0 + test_fr_fr fr2,fr48 + cfmas fr28,fr52,fr2,cc5,0 + test_fr_fr fr2,fr52 + + cfmas fr28,fr8,fr2,cc5,0 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr8,fr28,fr2,cc5,0 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + cfmas fr32,fr36,fr2,cc5,0 + test_fr_fr fr2,fr40 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmas fr16,fr4,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr8,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr12,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr16,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr20,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr24,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr28,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr32,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr36,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr40,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr44,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr48,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr20,fr4,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr8,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr12,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr16,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr20,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr24,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr20,fr28,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr32,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr40,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr44,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr48,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr28,fr0,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr4,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr8,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr12,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr16,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr20,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr24,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr28,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr32,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr40,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr44,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr48,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr52,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + + cfmas fr28,fr8,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr8,fr28,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr32,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmas fr16,fr4,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr8,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr12,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr16,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr20,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr24,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr28,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr32,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr36,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr40,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr44,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr48,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr20,fr4,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr8,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr12,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr16,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr20,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr24,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr20,fr28,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr32,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr40,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr44,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr48,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr28,fr0,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr4,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr8,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr12,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr16,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr20,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr24,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr28,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr32,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr40,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr44,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr48,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr52,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + + cfmas fr28,fr8,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr8,fr28,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr32,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmas fr16,fr4,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr8,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr12,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr16,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr20,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr24,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr28,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr32,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr36,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr40,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr44,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr48,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr20,fr4,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr8,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr12,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr16,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr20,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr24,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr20,fr28,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr32,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr36,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr40,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr44,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr48,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr28,fr0,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr4,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr8,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr12,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr16,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr20,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr24,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr28,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr32,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr36,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr40,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr44,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr48,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr52,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + + cfmas fr28,fr8,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr8,fr28,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr32,fr36,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmas fr16,fr4,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr8,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr12,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr16,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr20,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr24,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr28,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr32,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr36,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr40,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr44,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr48,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr20,fr4,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr8,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr12,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr16,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr20,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr24,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr20,fr28,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr32,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr36,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr40,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr44,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr48,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr28,fr0,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr4,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr8,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr12,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr16,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr20,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr24,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr28,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr32,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr36,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr40,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr44,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr48,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr52,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + + cfmas fr28,fr8,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr8,fr28,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr32,fr36,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + + pass diff --git a/sim/testsuite/sim/frv/cfmovs.cgs b/sim/testsuite/sim/frv/cfmovs.cgs new file mode 100644 index 00000000000..e90fcba4770 --- /dev/null +++ b/sim/testsuite/sim/frv/cfmovs.cgs @@ -0,0 +1,216 @@ +# frv testcase for cfmovs $FRj,$FRk,$CCi,$cond +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfmovs +cfmovs: + set_spr_immed 0x1b1b,cccr + + cfmovs fr0,fr1,cc0,1 + test_fr_fr fr0,fr1 + cfmovs fr4,fr1,cc0,1 + test_fr_fr fr4,fr1 + cfmovs fr8,fr1,cc0,1 + test_fr_fr fr8,fr1 + cfmovs fr12,fr1,cc0,1 + test_fr_fr fr12,fr1 + cfmovs fr16,fr1,cc0,1 + test_fr_fr fr16,fr1 + cfmovs fr20,fr1,cc0,1 + test_fr_fr fr20,fr1 + cfmovs fr24,fr1,cc0,1 + test_fr_fr fr24,fr1 + cfmovs fr28,fr1,cc0,1 + test_fr_fr fr28,fr1 + cfmovs fr32,fr1,cc4,1 + test_fr_fr fr32,fr1 + cfmovs fr36,fr1,cc4,1 + test_fr_fr fr36,fr1 + cfmovs fr40,fr1,cc4,1 + test_fr_fr fr40,fr1 + cfmovs fr44,fr1,cc4,1 + test_fr_fr fr44,fr1 + cfmovs fr48,fr1,cc4,1 + test_fr_fr fr48,fr1 + cfmovs fr52,fr1,cc4,1 + test_fr_fr fr52,fr1 + cfmovs fr56,fr1,cc4,1 + test_fr_iimmed 0x7fc00000,fr1 + cfmovs fr60,fr1,cc4,1 + test_fr_iimmed 0x7f800001,fr1 + + cfmovs fr0,fr1,cc1,0 + test_fr_fr fr0,fr1 + cfmovs fr4,fr1,cc1,0 + test_fr_fr fr4,fr1 + cfmovs fr8,fr1,cc1,0 + test_fr_fr fr8,fr1 + cfmovs fr12,fr1,cc1,0 + test_fr_fr fr12,fr1 + cfmovs fr16,fr1,cc1,0 + test_fr_fr fr16,fr1 + cfmovs fr20,fr1,cc1,0 + test_fr_fr fr20,fr1 + cfmovs fr24,fr1,cc1,0 + test_fr_fr fr24,fr1 + cfmovs fr28,fr1,cc1,0 + test_fr_fr fr28,fr1 + cfmovs fr32,fr1,cc5,0 + test_fr_fr fr32,fr1 + cfmovs fr36,fr1,cc5,0 + test_fr_fr fr36,fr1 + cfmovs fr40,fr1,cc5,0 + test_fr_fr fr40,fr1 + cfmovs fr44,fr1,cc5,0 + test_fr_fr fr44,fr1 + cfmovs fr48,fr1,cc5,0 + test_fr_fr fr48,fr1 + cfmovs fr52,fr1,cc5,0 + test_fr_fr fr52,fr1 + cfmovs fr56,fr1,cc5,0 + test_fr_iimmed 0x7fc00000,fr1 + cfmovs fr60,fr1,cc5,0 + test_fr_iimmed 0x7f800001,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmovs fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr24,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr56,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr60,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmovs fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr24,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr56,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr60,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmovs fr0,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr4,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr8,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr12,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr20,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr24,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr32,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr36,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr40,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr44,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr48,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr52,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr56,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr60,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmovs fr0,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr4,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr8,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr12,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr20,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr24,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr32,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr36,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr40,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr44,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr48,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr52,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr56,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr60,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/cfmss.cgs b/sim/testsuite/sim/frv/cfmss.cgs new file mode 100644 index 00000000000..28f8392924f --- /dev/null +++ b/sim/testsuite/sim/frv/cfmss.cgs @@ -0,0 +1,697 @@ +# frv testcase for cfmss $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global cfmss +cfmss: + set_spr_immed 0x1b1b,cccr + + cfmss fr16,fr4,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr8,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr16,fr12,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr16,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr16,fr20,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr16,fr24,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr28,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmss fr16,fr32,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr36,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr40,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr44,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr48,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + cfmss fr20,fr4,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr8,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr20,fr12,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr16,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr20,fr20,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr20,fr24,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr28,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmss fr20,fr32,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr36,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr40,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr44,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr48,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + cfmss fr28,fr0,fr2,cc4,1 + test_fr_fr fr2,fr0 + cfmss fr28,fr4,fr2,cc4,1 + test_fr_fr fr2,fr4 + cfmss fr28,fr8,fr2,cc4,1 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + cfmss fr28,fr12,fr2,cc4,1 + test_fr_fr fr2,fr12 + cfmss fr28,fr16,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr28,fr20,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr28,fr24,fr2,cc4,1 + test_fr_fr fr2,fr24 + cfmss fr28,fr28,fr2,cc4,1 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + cfmss fr28,fr32,fr2,cc4,1 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr8 + cfmss fr28,fr36,fr2,cc4,1 + test_fr_fr fr2,fr36 + cfmss fr28,fr40,fr2,cc4,1 + test_fr_fr fr2,fr40 + cfmss fr28,fr44,fr2,cc4,1 + test_fr_fr fr2,fr44 + cfmss fr28,fr48,fr2,cc4,1 + test_fr_fr fr2,fr48 + cfmss fr28,fr52,fr2,cc4,1 + test_fr_fr fr2,fr52 + + cfmss fr28,fr8,fr2,cc4,1 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + cfmss fr8,fr28,fr2,cc4,1 + test_fr_fr fr2,fr8 + + cfmss fr32,fr36,fr2,cc4,1 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr8 +; + cfmss fr16,fr4,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr8,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr16,fr12,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr16,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr16,fr20,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr16,fr24,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr28,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmss fr16,fr32,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr36,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr40,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr44,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr48,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + cfmss fr20,fr4,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr8,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr20,fr12,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr16,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr20,fr20,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr20,fr24,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr28,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmss fr20,fr32,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr36,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr40,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr44,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr48,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + cfmss fr28,fr0,fr2,cc5,0 + test_fr_fr fr2,fr0 + cfmss fr28,fr4,fr2,cc5,0 + test_fr_fr fr2,fr4 + cfmss fr28,fr8,fr2,cc5,0 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + cfmss fr28,fr12,fr2,cc5,0 + test_fr_fr fr2,fr12 + cfmss fr28,fr16,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr28,fr20,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr28,fr24,fr2,cc5,0 + test_fr_fr fr2,fr24 + cfmss fr28,fr28,fr2,cc5,0 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + cfmss fr28,fr32,fr2,cc5,0 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr8 + cfmss fr28,fr36,fr2,cc5,0 + test_fr_fr fr2,fr36 + cfmss fr28,fr40,fr2,cc5,0 + test_fr_fr fr2,fr40 + cfmss fr28,fr44,fr2,cc5,0 + test_fr_fr fr2,fr44 + cfmss fr28,fr48,fr2,cc5,0 + test_fr_fr fr2,fr48 + cfmss fr28,fr52,fr2,cc5,0 + test_fr_fr fr2,fr52 + + cfmss fr28,fr8,fr2,cc5,0 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + cfmss fr8,fr28,fr2,cc5,0 + test_fr_fr fr2,fr8 + + cfmss fr32,fr36,fr2,cc5,0 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr8 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmss fr16,fr4,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr8,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr12,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr16,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr20,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr24,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr28,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr32,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr36,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr40,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr44,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr48,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr20,fr4,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr8,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr12,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr16,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr20,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr24,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr28,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr32,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr40,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr44,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr48,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr0,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr4,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr8,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr12,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr16,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr20,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr24,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr28,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr32,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr40,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr44,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr48,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr52,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr8,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr8,fr28,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr32,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmss fr16,fr4,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr8,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr12,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr16,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr20,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr24,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr28,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr32,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr36,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr40,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr44,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr48,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr20,fr4,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr8,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr12,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr16,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr20,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr24,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr28,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr32,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr40,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr44,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr48,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr0,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr4,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr8,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr12,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr16,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr20,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr24,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr28,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr32,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr40,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr44,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr48,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr52,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr8,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr8,fr28,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr32,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmss fr16,fr4,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr8,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr12,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr16,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr20,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr24,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr28,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr32,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr36,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr40,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr44,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr48,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr20,fr4,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr8,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr12,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr16,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr20,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr24,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr28,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr32,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr36,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr40,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr44,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr48,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr0,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr4,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr8,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr12,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr16,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr20,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr24,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr28,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr32,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr36,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr40,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr44,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr48,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr52,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr8,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr8,fr28,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr32,fr36,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmss fr16,fr4,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr8,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr12,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr16,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr20,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr24,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr28,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr32,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr36,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr40,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr44,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr48,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr20,fr4,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr8,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr12,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr16,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr20,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr24,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr28,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr32,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr36,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr40,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr44,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr48,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr0,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr4,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr8,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr12,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr16,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr20,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr24,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr28,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr32,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr36,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr40,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr44,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr48,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr52,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr8,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr8,fr28,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr32,fr36,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + pass diff --git a/sim/testsuite/sim/frv/cfmsubs.cgs b/sim/testsuite/sim/frv/cfmsubs.cgs new file mode 100644 index 00000000000..bc74da41b03 --- /dev/null +++ b/sim/testsuite/sim/frv/cfmsubs.cgs @@ -0,0 +1,629 @@ +# frv testcase for cfmsubs $GRi,$GRj,$GRk,$CCi,$cond +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfmsubs +cfmsubs: + set_spr_immed 0x1b1b,cccr + + set_fr_fr fr16,fr1 + cfmsubs fr16,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr36,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr40,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr44,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr48,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmsubs fr20,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr36,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr40,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr44,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr48,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + cfmsubs fr28,fr0,fr1,cc4,1 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr4,fr1,cc4,1 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr12,fr1,cc4,1 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr16,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr24,fr1,cc4,1 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr32,fr1,cc4,1 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr36,fr1,cc4,1 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr40,fr1,cc4,1 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr44,fr1,cc4,1 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr48,fr1,cc4,1 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr52,fr1,cc4,1 + test_fr_fr fr1,fr52 + + set_fr_fr fr32,fr1 + cfmsubs fr8,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + set_fr_fr fr36,fr1 + cfmsubs fr36,fr36,fr1,cc4,1 + test_fr_fr fr1,fr40 + + cfmsubs fr32,fr36,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 +; + set_fr_fr fr16,fr1 + cfmsubs fr16,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr36,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr40,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr44,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr48,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmsubs fr20,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr36,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr40,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr44,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr48,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + cfmsubs fr28,fr0,fr1,cc5,0 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr4,fr1,cc5,0 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr12,fr1,cc5,0 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr16,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr24,fr1,cc5,0 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr32,fr1,cc5,0 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr36,fr1,cc5,0 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr40,fr1,cc5,0 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr44,fr1,cc5,0 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr48,fr1,cc5,0 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr52,fr1,cc5,0 + test_fr_fr fr1,fr52 + + set_fr_fr fr32,fr1 + cfmsubs fr8,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + set_fr_fr fr36,fr1 + cfmsubs fr36,fr36,fr1,cc5,0 + test_fr_fr fr1,fr40 + + cfmsubs fr32,fr36,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 +; + set_fr_fr fr48,fr1 + cfmsubs fr16,fr4,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr8,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr12,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr16,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr20,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr24,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr28,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr32,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr36,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr40,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr44,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr48,fr1,cc0,0 + test_fr_fr fr1,fr48 + + cfmsubs fr20,fr4,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr8,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr12,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr16,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr20,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr24,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr28,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr32,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr36,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr40,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr44,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr48,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmsubs fr28,fr0,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr4,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr8,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr12,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr16,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr20,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr24,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr28,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr32,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr36,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr40,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr44,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr48,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr52,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmsubs fr8,fr8,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr36,fr36,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmsubs fr32,fr36,fr1,cc4,0 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmsubs fr16,fr4,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr8,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr12,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr16,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr20,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr24,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr28,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr32,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr36,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr40,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr44,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr48,fr1,cc1,1 + test_fr_fr fr1,fr48 + + cfmsubs fr20,fr4,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr8,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr12,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr16,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr20,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr24,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr28,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr32,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr36,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr40,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr44,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr48,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmsubs fr28,fr0,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr4,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr8,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr12,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr16,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr20,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr24,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr28,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr32,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr36,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr40,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr44,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr48,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr52,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmsubs fr8,fr8,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr36,fr36,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmsubs fr32,fr36,fr1,cc5,1 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmsubs fr16,fr4,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr8,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr12,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr16,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr20,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr24,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr28,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr32,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr36,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr40,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr44,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr48,fr1,cc2,1 + test_fr_fr fr1,fr48 + + cfmsubs fr20,fr4,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr8,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr12,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr16,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr20,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr24,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr28,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr32,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr36,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr40,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr44,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr48,fr1,cc6,1 + test_fr_fr fr1,fr48 + + cfmsubs fr28,fr0,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr4,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr8,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr12,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr16,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr20,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr24,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr28,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr32,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr36,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr40,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr44,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr48,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr52,fr1,cc6,1 + test_fr_fr fr1,fr48 + + cfmsubs fr8,fr8,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr36,fr36,fr1,cc6,1 + test_fr_fr fr1,fr48 + + cfmsubs fr32,fr36,fr1,cc6,0 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmsubs fr16,fr4,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr8,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr12,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr16,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr20,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr24,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr28,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr32,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr36,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr40,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr44,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr48,fr1,cc3,1 + test_fr_fr fr1,fr48 + + cfmsubs fr20,fr4,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr8,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr12,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr16,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr20,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr24,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr28,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr32,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr36,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr40,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr44,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr48,fr1,cc7,1 + test_fr_fr fr1,fr48 + + cfmsubs fr28,fr0,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr4,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr8,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr12,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr16,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr20,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr24,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr28,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr32,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr36,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr40,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr44,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr48,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr52,fr1,cc7,1 + test_fr_fr fr1,fr48 + + cfmsubs fr8,fr8,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr36,fr36,fr1,cc7,1 + test_fr_fr fr1,fr48 + + cfmsubs fr32,fr36,fr1,cc7,0 + test_fr_fr fr1,fr48 +; + pass diff --git a/sim/testsuite/sim/frv/cfmuls.cgs b/sim/testsuite/sim/frv/cfmuls.cgs new file mode 100644 index 00000000000..a549b5c3b77 --- /dev/null +++ b/sim/testsuite/sim/frv/cfmuls.cgs @@ -0,0 +1,696 @@ +# frv testcase for cfmuls $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfmuls +cfmuls: + set_spr_immed 0x1b1b,cccr + + cfmuls fr16,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr36,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr40,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr44,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr48,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmuls fr20,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr36,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr40,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr44,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr48,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmuls fr28,fr0,fr1,cc4,1 + test_fr_fr fr1,fr0 + cfmuls fr28,fr4,fr1,cc4,1 + test_fr_fr fr1,fr4 + cfmuls fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfmuls fr28,fr12,fr1,cc4,1 + test_fr_fr fr1,fr12 + cfmuls fr28,fr16,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr28,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr28,fr24,fr1,cc4,1 + test_fr_fr fr1,fr24 + cfmuls fr28,fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + cfmuls fr28,fr32,fr1,cc4,1 + test_fr_fr fr1,fr32 + cfmuls fr28,fr36,fr1,cc4,1 + test_fr_fr fr1,fr36 + cfmuls fr28,fr40,fr1,cc4,1 + test_fr_fr fr1,fr40 + cfmuls fr28,fr44,fr1,cc4,1 + test_fr_fr fr1,fr44 + cfmuls fr28,fr48,fr1,cc4,1 + test_fr_fr fr1,fr48 + cfmuls fr28,fr52,fr1,cc4,1 + test_fr_fr fr1,fr52 + + cfmuls fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfmuls fr8,fr28,fr1,cc4,1 + test_fr_fr fr1,fr8 + + cfmuls fr32,fr36,fr1,cc4,1 + test_fr_fr fr1,fr40 +; + cfmuls fr16,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr36,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr40,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr44,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr48,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmuls fr20,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr36,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr40,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr44,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr48,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmuls fr28,fr0,fr1,cc5,0 + test_fr_fr fr1,fr0 + cfmuls fr28,fr4,fr1,cc5,0 + test_fr_fr fr1,fr4 + cfmuls fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfmuls fr28,fr12,fr1,cc5,0 + test_fr_fr fr1,fr12 + cfmuls fr28,fr16,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr28,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr28,fr24,fr1,cc5,0 + test_fr_fr fr1,fr24 + cfmuls fr28,fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + cfmuls fr28,fr32,fr1,cc5,0 + test_fr_fr fr1,fr32 + cfmuls fr28,fr36,fr1,cc5,0 + test_fr_fr fr1,fr36 + cfmuls fr28,fr40,fr1,cc5,0 + test_fr_fr fr1,fr40 + cfmuls fr28,fr44,fr1,cc5,0 + test_fr_fr fr1,fr44 + cfmuls fr28,fr48,fr1,cc5,0 + test_fr_fr fr1,fr48 + cfmuls fr28,fr52,fr1,cc5,0 + test_fr_fr fr1,fr52 + + cfmuls fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfmuls fr8,fr28,fr1,cc5,0 + test_fr_fr fr1,fr8 + + cfmuls fr32,fr36,fr1,cc5,0 + test_fr_fr fr1,fr40 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmuls fr16,fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr24,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr32,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr36,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr40,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr44,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr48,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr20,fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr24,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr32,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr0,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr4,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr12,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr16,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr8,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr32,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmuls fr16,fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr24,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr32,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr36,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr40,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr44,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr48,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr20,fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr24,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr32,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr0,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr4,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr12,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr16,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr8,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr32,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmuls fr16,fr4,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr8,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr12,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr20,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr24,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr32,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr36,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr40,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr44,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr48,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr20,fr4,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr8,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr12,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr20,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr24,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr32,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr36,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr40,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr44,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr48,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr0,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr4,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr8,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr12,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr16,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr24,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr28,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr32,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr36,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr40,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr44,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr48,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr52,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr8,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr8,fr28,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr32,fr36,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmuls fr16,fr4,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr20,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr24,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr32,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr36,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr40,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr44,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr48,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr20,fr4,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr20,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr24,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr32,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr36,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr40,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr44,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr48,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr0,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr4,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr8,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr12,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr16,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr24,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr28,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr32,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr36,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr40,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr44,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr48,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr52,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr8,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr8,fr28,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr32,fr36,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/cfnegs.cgs b/sim/testsuite/sim/frv/cfnegs.cgs new file mode 100644 index 00000000000..728f5f02640 --- /dev/null +++ b/sim/testsuite/sim/frv/cfnegs.cgs @@ -0,0 +1,96 @@ +# frv testcase for cfnegs $FRj,$FRk,$CCi,$cond +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfnegs +cfnegs: + set_spr_immed 0x1b1b,cccr + + cfnegs fr0,fr1,cc0,1 + test_fr_fr fr1,fr52 + cfnegs fr8,fr1,cc0,1 + test_fr_fr fr1,fr28 + cfnegs fr12,fr1,cc0,1 + test_fr_fr fr1,fr24 + cfnegs fr24,fr1,cc4,1 + test_fr_fr fr1,fr12 + cfnegs fr28,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfnegs fr52,fr1,cc4,1 + test_fr_fr fr1,fr0 + + cfnegs fr0,fr1,cc1,0 + test_fr_fr fr1,fr52 + cfnegs fr8,fr1,cc1,0 + test_fr_fr fr1,fr28 + cfnegs fr12,fr1,cc1,0 + test_fr_fr fr1,fr24 + cfnegs fr24,fr1,cc5,0 + test_fr_fr fr1,fr12 + cfnegs fr28,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfnegs fr52,fr1,cc5,0 + test_fr_fr fr1,fr0 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfnegs fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfnegs fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfnegs fr0,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr8,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr12,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr24,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr28,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr52,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfnegs fr0,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr24,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr28,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr52,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/cfsqrts.cgs b/sim/testsuite/sim/frv/cfsqrts.cgs new file mode 100644 index 00000000000..32ff541d53b --- /dev/null +++ b/sim/testsuite/sim/frv/cfsqrts.cgs @@ -0,0 +1,60 @@ +# frv testcase for cfsqrts $FRj,$FRk,$CCi,$cond +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfsqrts +cfsqrts: + set_spr_immed 0x1b1b,cccr + + cfsqrts fr44,fr1,cc0,1 ; 9.0 + test_fr_fr fr1,fr36 ; 3.0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc4,1 + test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 + + cfsqrts fr44,fr1,cc1,0 ; 9.0 + test_fr_fr fr1,fr36 ; 3.0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc5,0 + test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 + + set_fr_fr fr0,fr1 + cfsqrts fr44,fr1,cc0,0 ; 9.0 + test_fr_fr fr1,fr0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc4,0 + test_fr_iimmed 0x40490fdb,fr10 + + set_fr_fr fr0,fr1 + cfsqrts fr44,fr1,cc1,1 ; 9.0 + test_fr_fr fr1,fr0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc5,1 + test_fr_iimmed 0x40490fdb,fr10 + + set_fr_fr fr0,fr1 + cfsqrts fr44,fr1,cc2,0 ; 9.0 + test_fr_fr fr1,fr0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc6,1 + test_fr_iimmed 0x40490fdb,fr10 + + set_fr_fr fr0,fr1 + cfsqrts fr44,fr1,cc3,1 ; 9.0 + test_fr_fr fr1,fr0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc7,0 + test_fr_iimmed 0x40490fdb,fr10 + + pass diff --git a/sim/testsuite/sim/frv/cfstoi.cgs b/sim/testsuite/sim/frv/cfstoi.cgs new file mode 100644 index 00000000000..42e5555acca --- /dev/null +++ b/sim/testsuite/sim/frv/cfstoi.cgs @@ -0,0 +1,83 @@ +# frv testcase for cfstoi $FRj,$FRk,$CCi,$cond +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfstoi +cfstoi: + set_spr_immed 0x1b1b,cccr + + cfstoi fr16,fr1,cc0,1 + test_fr_iimmed 0,fr1 + cfstoi fr20,fr1,cc0,1 + test_fr_iimmed 0,fr1 + + cfstoi fr32,fr1,cc4,1 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xce05,0x4904,fr1 + cfstoi fr1,fr1,cc4,1 + test_fr_iimmed 0xdeadbf00,fr1 + + cfstoi fr16,fr1,cc1,0 + test_fr_iimmed 0,fr1 + cfstoi fr20,fr1,cc1,0 + test_fr_iimmed 0,fr1 + + cfstoi fr32,fr1,cc5,0 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xce05,0x4904,fr1 + cfstoi fr1,fr1,cc5,0 + test_fr_iimmed 0xdeadbf00,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfstoi fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfstoi fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr1,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfstoi fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr1,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfstoi fr20,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr32,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr1,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfstoi fr20,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr32,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr1,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/cfsubs.cgs b/sim/testsuite/sim/frv/cfsubs.cgs new file mode 100644 index 00000000000..5f1adc46995 --- /dev/null +++ b/sim/testsuite/sim/frv/cfsubs.cgs @@ -0,0 +1,412 @@ +# frv testcase for cfsubs $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfsubs +cfsubs: + set_spr_immed 0x1b1b,cccr + + cfsubs fr0,fr16,fr1,cc0,1 + test_fr_fr fr1,fr0 + cfsubs fr4,fr16,fr1,cc0,1 + test_fr_fr fr1,fr4 + cfsubs fr8,fr16,fr1,cc0,1 + test_fr_fr fr1,fr8 + cfsubs fr12,fr16,fr1,cc0,1 + test_fr_fr fr1,fr12 + cfsubs fr16,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr20,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr24,fr16,fr1,cc0,1 + test_fr_fr fr1,fr24 + cfsubs fr28,fr16,fr1,cc0,1 + test_fr_fr fr1,fr28 + cfsubs fr32,fr16,fr1,cc0,1 + test_fr_fr fr1,fr32 + cfsubs fr36,fr16,fr1,cc0,1 + test_fr_fr fr1,fr36 + cfsubs fr40,fr16,fr1,cc0,1 + test_fr_fr fr1,fr40 + cfsubs fr44,fr16,fr1,cc0,1 + test_fr_fr fr1,fr44 + cfsubs fr48,fr16,fr1,cc0,1 + test_fr_fr fr1,fr48 + cfsubs fr52,fr16,fr1,cc0,1 + test_fr_fr fr1,fr52 + + cfsubs fr0,fr20,fr1,cc0,1 + test_fr_fr fr1,fr0 + cfsubs fr4,fr20,fr1,cc4,1 + test_fr_fr fr1,fr4 + cfsubs fr8,fr20,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfsubs fr12,fr20,fr1,cc4,1 + test_fr_fr fr1,fr12 + cfsubs fr16,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr20,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr24,fr20,fr1,cc4,1 + test_fr_fr fr1,fr24 + cfsubs fr28,fr20,fr1,cc4,1 + test_fr_fr fr1,fr28 + cfsubs fr32,fr20,fr1,cc4,1 + test_fr_fr fr1,fr32 + cfsubs fr36,fr20,fr1,cc4,1 + test_fr_fr fr1,fr36 + cfsubs fr40,fr20,fr1,cc4,1 + test_fr_fr fr1,fr40 + cfsubs fr44,fr20,fr1,cc4,1 + test_fr_fr fr1,fr44 + cfsubs fr48,fr20,fr1,cc4,1 + test_fr_fr fr1,fr48 + cfsubs fr52,fr20,fr1,cc4,1 + test_fr_fr fr1,fr52 + + cfsubs fr32,fr36,fr1,cc4,1 + test_fr_fr fr1,fr8 + + cfsubs fr44,fr40,fr1,cc4,1 + test_fr_fr fr1,fr36 +; + cfsubs fr0,fr16,fr1,cc1,0 + test_fr_fr fr1,fr0 + cfsubs fr4,fr16,fr1,cc1,0 + test_fr_fr fr1,fr4 + cfsubs fr8,fr16,fr1,cc1,0 + test_fr_fr fr1,fr8 + cfsubs fr12,fr16,fr1,cc1,0 + test_fr_fr fr1,fr12 + cfsubs fr16,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr20,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr24,fr16,fr1,cc1,0 + test_fr_fr fr1,fr24 + cfsubs fr28,fr16,fr1,cc1,0 + test_fr_fr fr1,fr28 + cfsubs fr32,fr16,fr1,cc1,0 + test_fr_fr fr1,fr32 + cfsubs fr36,fr16,fr1,cc1,0 + test_fr_fr fr1,fr36 + cfsubs fr40,fr16,fr1,cc1,0 + test_fr_fr fr1,fr40 + cfsubs fr44,fr16,fr1,cc1,0 + test_fr_fr fr1,fr44 + cfsubs fr48,fr16,fr1,cc1,0 + test_fr_fr fr1,fr48 + cfsubs fr52,fr16,fr1,cc1,0 + test_fr_fr fr1,fr52 + + cfsubs fr0,fr20,fr1,cc1,0 + test_fr_fr fr1,fr0 + cfsubs fr4,fr20,fr1,cc5,0 + test_fr_fr fr1,fr4 + cfsubs fr8,fr20,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfsubs fr12,fr20,fr1,cc5,0 + test_fr_fr fr1,fr12 + cfsubs fr16,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr20,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr24,fr20,fr1,cc5,0 + test_fr_fr fr1,fr24 + cfsubs fr28,fr20,fr1,cc5,0 + test_fr_fr fr1,fr28 + cfsubs fr32,fr20,fr1,cc5,0 + test_fr_fr fr1,fr32 + cfsubs fr36,fr20,fr1,cc5,0 + test_fr_fr fr1,fr36 + cfsubs fr40,fr20,fr1,cc5,0 + test_fr_fr fr1,fr40 + cfsubs fr44,fr20,fr1,cc5,0 + test_fr_fr fr1,fr44 + cfsubs fr48,fr20,fr1,cc5,0 + test_fr_fr fr1,fr48 + cfsubs fr52,fr20,fr1,cc5,0 + test_fr_fr fr1,fr52 + + cfsubs fr32,fr36,fr1,cc5,0 + test_fr_fr fr1,fr8 + + cfsubs fr44,fr40,fr1,cc5,0 + test_fr_fr fr1,fr36 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfsubs fr0,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr0,fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr32,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr44,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfsubs fr0,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr0,fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr32,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr44,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfsubs fr0,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr0,fr20,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr32,fr36,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr44,fr40,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfsubs fr0,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr0,fr20,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr32,fr36,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr44,fr40,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + pass + + diff --git a/sim/testsuite/sim/frv/cjmpl.cgs b/sim/testsuite/sim/frv/cjmpl.cgs new file mode 100644 index 00000000000..df7be86ac14 --- /dev/null +++ b/sim/testsuite/sim/frv/cjmpl.cgs @@ -0,0 +1,55 @@ +# frv testcase for cjmpl @($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cjmpl +cjmpl: + set_spr_immed 0x1b1b,cccr + + set_spr_immed 0,lr + set_gr_addr ok1,gr8 + set_gr_immed 0,gr9 + cjmpl @(gr8,gr9),cc0,1 + fail +ok1: + test_spr_immed 0,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + set_gr_immed 0,gr9 + cjmpl @(gr8,gr9),cc0,0 + test_spr_immed 0,lr + + set_spr_immed 0,lr + set_gr_addr ok4,gr8 + set_gr_immed 3,gr9 ; target gets aligned down + cjmpl @(gr8,gr9),cc1,0 + fail +ok4: + test_spr_immed 0,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + set_gr_immed 0,gr9 + cjmpl @(gr8,gr9),cc1,1 + test_spr_immed 0,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + set_gr_immed 0,gr9 + cjmpl @(gr8,gr9),cc2,0 + test_spr_immed 0,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + set_gr_immed 0,gr9 + cjmpl @(gr8,gr9),cc3,1 + test_spr_immed 0,lr + + pass +bad: + fail + diff --git a/sim/testsuite/sim/frv/ckc.cgs b/sim/testsuite/sim/frv/ckc.cgs new file mode 100644 index 00000000000..a849dd48376 --- /dev/null +++ b/sim/testsuite/sim/frv/ckc.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckc $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckc +ckc: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckeq.cgs b/sim/testsuite/sim/frv/ckeq.cgs new file mode 100644 index 00000000000..241dc9d0c3c --- /dev/null +++ b/sim/testsuite/sim/frv/ckeq.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckeq $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckeq +ckeq: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckge.cgs b/sim/testsuite/sim/frv/ckge.cgs new file mode 100644 index 00000000000..58eefd33845 --- /dev/null +++ b/sim/testsuite/sim/frv/ckge.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckge $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckge +ckge: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckgt.cgs b/sim/testsuite/sim/frv/ckgt.cgs new file mode 100644 index 00000000000..7d4b6a88e19 --- /dev/null +++ b/sim/testsuite/sim/frv/ckgt.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckgt $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckgt +ckgt: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckgt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckgt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckgt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckgt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckhi.cgs b/sim/testsuite/sim/frv/ckhi.cgs new file mode 100644 index 00000000000..5c55937f6ab --- /dev/null +++ b/sim/testsuite/sim/frv/ckhi.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckhi $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckhi +ckhi: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckhi icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckhi icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckhi icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckhi icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckle.cgs b/sim/testsuite/sim/frv/ckle.cgs new file mode 100644 index 00000000000..8a6f445beaa --- /dev/null +++ b/sim/testsuite/sim/frv/ckle.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckle $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckle +ckle: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckle icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckle icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckle icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckle icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckls.cgs b/sim/testsuite/sim/frv/ckls.cgs new file mode 100644 index 00000000000..ca5822f283f --- /dev/null +++ b/sim/testsuite/sim/frv/ckls.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckls $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckls +ckls: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckls icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckls icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckls icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckls icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cklt.cgs b/sim/testsuite/sim/frv/cklt.cgs new file mode 100644 index 00000000000..f5848af490d --- /dev/null +++ b/sim/testsuite/sim/frv/cklt.cgs @@ -0,0 +1,90 @@ +# frv testcase for cklt $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global cklt +cklt: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckn.cgs b/sim/testsuite/sim/frv/ckn.cgs new file mode 100644 index 00000000000..073a2f1137d --- /dev/null +++ b/sim/testsuite/sim/frv/ckn.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckn $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckn +ckn: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cknc.cgs b/sim/testsuite/sim/frv/cknc.cgs new file mode 100644 index 00000000000..a1359a983ad --- /dev/null +++ b/sim/testsuite/sim/frv/cknc.cgs @@ -0,0 +1,90 @@ +# frv testcase for cknc $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global cknc +cknc: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckne.cgs b/sim/testsuite/sim/frv/ckne.cgs new file mode 100644 index 00000000000..b9c293519b7 --- /dev/null +++ b/sim/testsuite/sim/frv/ckne.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckne $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckne +ckne: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckno.cgs b/sim/testsuite/sim/frv/ckno.cgs new file mode 100644 index 00000000000..e387b46beac --- /dev/null +++ b/sim/testsuite/sim/frv/ckno.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckno $CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckno +ckno: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cknv.cgs b/sim/testsuite/sim/frv/cknv.cgs new file mode 100644 index 00000000000..039eb7d8dbf --- /dev/null +++ b/sim/testsuite/sim/frv/cknv.cgs @@ -0,0 +1,90 @@ +# frv testcase for cknv $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global cknv +cknv: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckp.cgs b/sim/testsuite/sim/frv/ckp.cgs new file mode 100644 index 00000000000..49129ec9bb9 --- /dev/null +++ b/sim/testsuite/sim/frv/ckp.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckp $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckp +ckp: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckra.cgs b/sim/testsuite/sim/frv/ckra.cgs new file mode 100644 index 00000000000..b542b10b9ed --- /dev/null +++ b/sim/testsuite/sim/frv/ckra.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckra $CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckra +ckra: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckv.cgs b/sim/testsuite/sim/frv/ckv.cgs new file mode 100644 index 00000000000..338c2861ed8 --- /dev/null +++ b/sim/testsuite/sim/frv/ckv.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckv $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckv +ckv: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cld.cgs b/sim/testsuite/sim/frv/cld.cgs new file mode 100644 index 00000000000..62e1324a22b --- /dev/null +++ b/sim/testsuite/sim/frv/cld.cgs @@ -0,0 +1,126 @@ +# frv testcase for cld @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cld +cld: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc6,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cldbf.cgs b/sim/testsuite/sim/frv/cldbf.cgs new file mode 100644 index 00000000000..46d65ea6939 --- /dev/null +++ b/sim/testsuite/sim/frv/cldbf.cgs @@ -0,0 +1,114 @@ +# frv testcase for cldbf @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldbf +cldbf: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0x00de,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0x00ad,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0x0000,0x0000,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0x00de,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0x00ad,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0x0000,0x0000,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + pass diff --git a/sim/testsuite/sim/frv/cldbfu.cgs b/sim/testsuite/sim/frv/cldbfu.cgs new file mode 100644 index 00000000000..bde4ff16db6 --- /dev/null +++ b/sim/testsuite/sim/frv/cldbfu.cgs @@ -0,0 +1,154 @@ +# frv testcase for cldbfu @($GRi,$GRj),$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldbfu +cldbfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0x00de,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0x00ad,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0x00de,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0x00ad,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cldd.cgs b/sim/testsuite/sim/frv/cldd.cgs new file mode 100644 index 00000000000..709eba19ae7 --- /dev/null +++ b/sim/testsuite/sim/frv/cldd.cgs @@ -0,0 +1,168 @@ +# frv testcase for cldd @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldd +cldd: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + pass diff --git a/sim/testsuite/sim/frv/clddf.cgs b/sim/testsuite/sim/frv/clddf.cgs new file mode 100644 index 00000000000..c5416ed4c37 --- /dev/null +++ b/sim/testsuite/sim/frv/clddf.cgs @@ -0,0 +1,174 @@ +# frv testcase for clddf @($GRi,$GRj),$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global clddf +clddf: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + pass diff --git a/sim/testsuite/sim/frv/clddfu.cgs b/sim/testsuite/sim/frv/clddfu.cgs new file mode 100644 index 00000000000..ab981aa1389 --- /dev/null +++ b/sim/testsuite/sim/frv/clddfu.cgs @@ -0,0 +1,212 @@ +# frv testcase for clddfu @($GRi,$GRj),$FRk,$CCi,$ccond +# mach: all + + .include "testutils.inc" + + start + + .global clddfu +clddfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/clddu.cgs b/sim/testsuite/sim/frv/clddu.cgs new file mode 100644 index 00000000000..91df6d8f43e --- /dev/null +++ b/sim/testsuite/sim/frv/clddu.cgs @@ -0,0 +1,219 @@ +# frv testcase for clddu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global clddu +clddu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,gr8 + inc_gr_immed -12,gr8 + set_gr_immed 8,gr7 + clddu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + pass diff --git a/sim/testsuite/sim/frv/cldf.cgs b/sim/testsuite/sim/frv/cldf.cgs new file mode 100644 index 00000000000..011a02a3e85 --- /dev/null +++ b/sim/testsuite/sim/frv/cldf.cgs @@ -0,0 +1,126 @@ +# frv testcase for cldf @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldf +cldf: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + pass diff --git a/sim/testsuite/sim/frv/cldfu.cgs b/sim/testsuite/sim/frv/cldfu.cgs new file mode 100644 index 00000000000..d4abef00c96 --- /dev/null +++ b/sim/testsuite/sim/frv/cldfu.cgs @@ -0,0 +1,164 @@ +# frv testcase for cldfu @($GRi,$GRj),$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldfu +cldfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,gr20 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,gr20 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,gr20 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,gr20 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cldhf.cgs b/sim/testsuite/sim/frv/cldhf.cgs new file mode 100644 index 00000000000..26972ed000d --- /dev/null +++ b/sim/testsuite/sim/frv/cldhf.cgs @@ -0,0 +1,114 @@ +# frv testcase for cldhf @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldhf +cldhf: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0xbeef,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0x0000,0x0000,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0xbeef,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0x0000,0x0000,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + pass diff --git a/sim/testsuite/sim/frv/cldhfu.cgs b/sim/testsuite/sim/frv/cldhfu.cgs new file mode 100644 index 00000000000..062e3984a92 --- /dev/null +++ b/sim/testsuite/sim/frv/cldhfu.cgs @@ -0,0 +1,152 @@ +# frv testcase for cldhfu @($GRi,$GRj),$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldhfu +cldhfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0xbeef,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0xbeef,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cldq.cgs b/sim/testsuite/sim/frv/cldq.cgs new file mode 100644 index 00000000000..bfb433b5e31 --- /dev/null +++ b/sim/testsuite/sim/frv/cldq.cgs @@ -0,0 +1,276 @@ +# frv testcase for cldq @($GRi,$GRj),$GRk,$CCi,$cond +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global cldq +cldq: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + pass diff --git a/sim/testsuite/sim/frv/cldqu.cgs b/sim/testsuite/sim/frv/cldqu.cgs new file mode 100644 index 00000000000..fa0949a876e --- /dev/null +++ b/sim/testsuite/sim/frv/cldqu.cgs @@ -0,0 +1,318 @@ +# frv testcase for cldqu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global cldqu +cldqu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,gr20 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,gr20 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,gr20 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,gr20 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,gr20 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,gr20 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,gr20 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,gr20 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,gr8 + inc_gr_immed -28,gr8 + set_gr_immed 16,gr7 + cldqu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + pass diff --git a/sim/testsuite/sim/frv/cldsb.cgs b/sim/testsuite/sim/frv/cldsb.cgs new file mode 100644 index 00000000000..ea8dd943ba3 --- /dev/null +++ b/sim/testsuite/sim/frv/cldsb.cgs @@ -0,0 +1,114 @@ +# frv testcase for cldsb @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldsb +cldsb: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xffde,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xffad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc4,1 + test_gr_immed 0,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xffde,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xffad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc5,0 + test_gr_immed 0,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc6,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cldsbu.cgs b/sim/testsuite/sim/frv/cldsbu.cgs new file mode 100644 index 00000000000..a4057f15696 --- /dev/null +++ b/sim/testsuite/sim/frv/cldsbu.cgs @@ -0,0 +1,162 @@ +# frv testcase for cldsbu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldsbu +cldsbu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xffde,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xffad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + inc_gr_immed 4,gr9 + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xffde,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xffad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + inc_gr_immed 4,gr9 + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + inc_gr_immed 4,gr9 + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + inc_gr_immed 4,gr9 + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr8 + set_gr_immed 1,gr7 + cldsbu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xffad,gr8 + + pass + diff --git a/sim/testsuite/sim/frv/cldsh.cgs b/sim/testsuite/sim/frv/cldsh.cgs new file mode 100644 index 00000000000..091d72036af --- /dev/null +++ b/sim/testsuite/sim/frv/cldsh.cgs @@ -0,0 +1,114 @@ +# frv testcase for cldsh @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global cldsh +cldsh: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc4,1 + test_gr_immed 0,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc5,0 + test_gr_immed 0,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc6,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cldshu.cgs b/sim/testsuite/sim/frv/cldshu.cgs new file mode 100644 index 00000000000..491352eb58b --- /dev/null +++ b/sim/testsuite/sim/frv/cldshu.cgs @@ -0,0 +1,159 @@ +# frv testcase for cldshu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldshu +cldshu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr8 + set_gr_immed 2,gr7 + cldshu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cldu.cgs b/sim/testsuite/sim/frv/cldu.cgs new file mode 100644 index 00000000000..61cf606132a --- /dev/null +++ b/sim/testsuite/sim/frv/cldu.cgs @@ -0,0 +1,172 @@ +# frv testcase for cldu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldu +cldu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,gr9 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,gr9 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,gr9 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,gr9 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,gr9 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,gr9 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,gr9 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,gr9 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr7 + cldu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cldub.cgs b/sim/testsuite/sim/frv/cldub.cgs new file mode 100644 index 00000000000..b1f07766ddd --- /dev/null +++ b/sim/testsuite/sim/frv/cldub.cgs @@ -0,0 +1,114 @@ +# frv testcase for cldub @($GRi,$GRj),$GRk,$cci,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldub +cldub: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0x00de,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0x00ad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x0000,0x0000,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0x00de,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0x00ad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x0000,0x0000,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc6,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cldubu.cgs b/sim/testsuite/sim/frv/cldubu.cgs new file mode 100644 index 00000000000..c9f9579da9d --- /dev/null +++ b/sim/testsuite/sim/frv/cldubu.cgs @@ -0,0 +1,155 @@ +# frv testcase for cldubu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldubu +cldubu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0x00de,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0x00ad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x0000,0x0000,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0x00de,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0x00ad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x0000,0x0000,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr8 + set_gr_immed 1,gr7 + cldubu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0x00ad,gr8 + + pass diff --git a/sim/testsuite/sim/frv/clduh.cgs b/sim/testsuite/sim/frv/clduh.cgs new file mode 100644 index 00000000000..a9e505c0727 --- /dev/null +++ b/sim/testsuite/sim/frv/clduh.cgs @@ -0,0 +1,114 @@ +# frv testcase for clduh @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global clduh +clduh: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x0000,0x0000,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x0000,0x0000,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc6,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/sim/frv/clduhu.cgs b/sim/testsuite/sim/frv/clduhu.cgs new file mode 100644 index 00000000000..80eb381c384 --- /dev/null +++ b/sim/testsuite/sim/frv/clduhu.cgs @@ -0,0 +1,159 @@ +# frv testcase for clduhu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global clduhu +clduhu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x0000,0x0000,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x0000,0x0000,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr8 + set_gr_immed 2,gr7 + clduhu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/clrfa.cgs b/sim/testsuite/sim/frv/clrfa.cgs new file mode 100644 index 00000000000..8bba605e8df --- /dev/null +++ b/sim/testsuite/sim/frv/clrfa.cgs @@ -0,0 +1,27 @@ +# frv testcase for clrfa +# mach: frv + + .include "testutils.inc" + + start + + .global clrfa +clrfa: + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + or_spr_immed 0x00100000,fner1 + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + or_spr_immed 0x00200000,fner1 + nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 + or_spr_immed 0x00100000,fner0 + + clrfa + test_spr_immed 0x00000000,fner1 + test_spr_immed 0x00000000,fner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0,nesr2 + test_spr_immed 0,neear2 + + pass diff --git a/sim/testsuite/sim/frv/clrfr.cgs b/sim/testsuite/sim/frv/clrfr.cgs new file mode 100644 index 00000000000..9112815236b --- /dev/null +++ b/sim/testsuite/sim/frv/clrfr.cgs @@ -0,0 +1,27 @@ +# frv testcase for clrfr $FRk +# mach: frv + + .include "testutils.inc" + + start + + .global clrfr +clrfr: + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + or_spr_immed 0x00100000,fner1 + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + or_spr_immed 0x00200000,fner1 + nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 + or_spr_immed 0x00100000,fner0 + + clrfr fr20 + test_spr_immed 0x00200000,fner1 + test_spr_immed 0x00100000,fner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xf4800801,nesr2 + test_spr_gr neear2,sp + + pass diff --git a/sim/testsuite/sim/frv/clrga.cgs b/sim/testsuite/sim/frv/clrga.cgs new file mode 100644 index 00000000000..9e9a9a9f1c8 --- /dev/null +++ b/sim/testsuite/sim/frv/clrga.cgs @@ -0,0 +1,27 @@ +# frv testcase for clrga +# mach: frv + + .include "testutils.inc" + + start + + .global clrga +clrga: + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + or_spr_immed 0x00100000,gner1 + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + or_spr_immed 0x00200000,gner1 + nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 + or_spr_immed 0x00100000,gner0 + + clrga + test_spr_immed 0x00000000,gner1 + test_spr_immed 0x00000000,gner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0,nesr2 + test_spr_immed 0,neear2 + + pass diff --git a/sim/testsuite/sim/frv/clrgr.cgs b/sim/testsuite/sim/frv/clrgr.cgs new file mode 100644 index 00000000000..049b9e371e7 --- /dev/null +++ b/sim/testsuite/sim/frv/clrgr.cgs @@ -0,0 +1,27 @@ +# frv testcase for clrgr $GRk +# mach: frv + + .include "testutils.inc" + + start + + .global clrgr +clrgr: + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + or_spr_immed 0x00100000,gner1 + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + or_spr_immed 0x00200000,gner1 + nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 + or_spr_immed 0x00100000,gner0 + + clrgr gr20 + test_spr_immed 0x00200000,gner1 + test_spr_immed 0x00100000,gner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xb4800801,nesr2 + test_spr_gr neear2,sp + + pass diff --git a/sim/testsuite/sim/frv/cmaddhss.cgs b/sim/testsuite/sim/frv/cmaddhss.cgs new file mode 100644 index 00000000000..e730827625d --- /dev/null +++ b/sim/testsuite/sim/frv/cmaddhss.cgs @@ -0,0 +1,562 @@ +# frv testcase for cmaddhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global maddhss +maddhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x1233,0x5677,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,1 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc4,1 + cmaddhss fr11,fr11,fr13,cc4,1 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x1233,0x5677,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc5,0 + cmaddhss fr11,fr11,fr13,cc5,0 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc4,0 + cmaddhss fr11,fr11,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc5,1 + cmaddhss fr11,fr11,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc6,1 + cmaddhss fr11,fr11,fr13,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set +; + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc7,1 + cmaddhss fr11,fr11,fr13,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/sim/frv/cmaddhus.cgs b/sim/testsuite/sim/frv/cmaddhus.cgs new file mode 100644 index 00000000000..4c5600df85c --- /dev/null +++ b/sim/testsuite/sim/frv/cmaddhus.cgs @@ -0,0 +1,496 @@ +# frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmaddhus +cmaddhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x7fff,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc4,1 + cmaddhus fr11,fr11,fr13,cc4,1 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0xffff,0xffff,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x7fff,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc5,0 + cmaddhus fr11,fr11,fr13,cc5,0 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0xffff,0xffff,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc4,0 + cmaddhus fr11,fr11,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc5,1 + cmaddhus fr11,fr11,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc6,0 + cmaddhus fr11,fr11,fr13,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc7,0 + cmaddhus fr11,fr11,fr13,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/sim/frv/cmand.cgs b/sim/testsuite/sim/frv/cmand.cgs new file mode 100644 index 00000000000..7ed9e4da33e --- /dev/null +++ b/sim/testsuite/sim/frv/cmand.cgs @@ -0,0 +1,89 @@ +# frv testcase for cmand $FRinti,$FRintj,$FRintk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmand +cmand: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0xaaaa0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc4,1 + test_fr_iimmed 0x0000aaaa,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0xaaaa0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc5,0 + test_fr_iimmed 0x0000aaaa,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0xffff0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc4,0 + test_fr_iimmed 0x0000ffff,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0xffff0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc5,1 + test_fr_iimmed 0x0000ffff,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc2,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc2,1 + test_fr_iimmed 0xffff0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc6,0 + test_fr_iimmed 0x0000ffff,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc3,1 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc3,0 + test_fr_iimmed 0xffff0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc7,1 + test_fr_iimmed 0x0000ffff,fr8 + pass diff --git a/sim/testsuite/sim/frv/cmbtoh.cgs b/sim/testsuite/sim/frv/cmbtoh.cgs new file mode 100644 index 00000000000..5e7c91ae669 --- /dev/null +++ b/sim/testsuite/sim/frv/cmbtoh.cgs @@ -0,0 +1,74 @@ +# frv testcase for cmbtoh $FRj,$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmbtoh +cmbtoh: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc0,1 + test_fr_limmed 0x00de,0x00ad,fr12 + test_fr_limmed 0x00be,0x00ef,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc4,1 + test_fr_limmed 0x0012,0x0034,fr12 + test_fr_limmed 0x0056,0x0078,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc1,0 + test_fr_limmed 0x00de,0x00ad,fr12 + test_fr_limmed 0x00be,0x00ef,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc5,0 + test_fr_limmed 0x0012,0x0034,fr12 + test_fr_limmed 0x0056,0x0078,fr13 + + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x2222,0x2222,fr13 + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc2,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc6,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc3,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc7,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + pass diff --git a/sim/testsuite/sim/frv/cmbtohe.cgs b/sim/testsuite/sim/frv/cmbtohe.cgs new file mode 100644 index 00000000000..eb6b51492ee --- /dev/null +++ b/sim/testsuite/sim/frv/cmbtohe.cgs @@ -0,0 +1,100 @@ +# frv testcase for cmbtohe $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + start + + .global cmbtohe +cmbtohe: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc0,1 + test_fr_limmed 0x00de,0x00de,fr12 + test_fr_limmed 0x00ad,0x00ad,fr13 + test_fr_limmed 0x00be,0x00be,fr14 + test_fr_limmed 0x00ef,0x00ef,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc4,1 + test_fr_limmed 0x0012,0x0012,fr12 + test_fr_limmed 0x0034,0x0034,fr13 + test_fr_limmed 0x0056,0x0056,fr14 + test_fr_limmed 0x0078,0x0078,fr15 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc1,0 + test_fr_limmed 0x00de,0x00de,fr12 + test_fr_limmed 0x00ad,0x00ad,fr13 + test_fr_limmed 0x00be,0x00be,fr14 + test_fr_limmed 0x00ef,0x00ef,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc5,0 + test_fr_limmed 0x0012,0x0012,fr12 + test_fr_limmed 0x0034,0x0034,fr13 + test_fr_limmed 0x0056,0x0056,fr14 + test_fr_limmed 0x0078,0x0078,fr15 + + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x2222,0x2222,fr13 + set_fr_iimmed 0x3333,0x3333,fr14 + set_fr_iimmed 0x4444,0x4444,fr15 + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc2,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc6,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc3,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc7,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + pass diff --git a/sim/testsuite/sim/frv/cmcpxis.cgs b/sim/testsuite/sim/frv/cmcpxis.cgs new file mode 100644 index 00000000000..ded030078d4 --- /dev/null +++ b/sim/testsuite/sim/frv/cmcpxis.cgs @@ -0,0 +1,971 @@ +# frv testcase for cmcpxis $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmcpxis +cmcpxis: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x3ff8,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xc000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -9,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xffff,fr7 ; 15 bit result + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbfff,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8001,0x0000,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x8000,0x0000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + ; Positive operands + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x3ff8,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xc000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -9,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xffff,fr7 ; 15 bit result + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbfff,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8001,0x0000,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x8000,0x0000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 +; + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/sim/frv/cmcpxiu.cgs b/sim/testsuite/sim/frv/cmcpxiu.cgs new file mode 100644 index 00000000000..8c6c29bda9c --- /dev/null +++ b/sim/testsuite/sim/frv/cmcpxiu.cgs @@ -0,0 +1,508 @@ +# frv testcase for cmcpxiu $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmcpxiu +cmcpxiu: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 5,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7fff,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0x00010001,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 1,accg0 + test_acc_immed 0xfffb0003,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 1,accg0 + test_acc_immed 0xfffc0002,acc0 + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 5,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7fff,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010001,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffb0003,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffc0002,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/sim/frv/cmcpxrs.cgs b/sim/testsuite/sim/frv/cmcpxrs.cgs new file mode 100644 index 00000000000..ea1242c1cdb --- /dev/null +++ b/sim/testsuite/sim/frv/cmcpxrs.cgs @@ -0,0 +1,649 @@ +# frv testcase for cmcpxrs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmcpxrs +cmcpxrs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ff0,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -3,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbff0,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8006,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8000,0x8000,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x7fff,0x8000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ff0,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -3,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbff0,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8006,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8000,0x8000,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x7fff,0x8000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 +; + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/sim/frv/cmcpxru.cgs b/sim/testsuite/sim/frv/cmcpxru.cgs new file mode 100644 index 00000000000..98f78e619d9 --- /dev/null +++ b/sim/testsuite/sim/frv/cmcpxru.cgs @@ -0,0 +1,544 @@ +# frv testcase for cmcpxru $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmcpxru +cmcpxru: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffd,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0x0001ffff,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffd,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0x0001ffff,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 +; + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/sim/frv/cmexpdhd.cgs b/sim/testsuite/sim/frv/cmexpdhd.cgs new file mode 100644 index 00000000000..33a3c009375 --- /dev/null +++ b/sim/testsuite/sim/frv/cmexpdhd.cgs @@ -0,0 +1,116 @@ +# frv testcase for cmexpdhd $FRi,$s6,$FRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmexpdhd +cmexpdhd: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc0,1 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + cmexpdhd fr10,1,fr12,cc0,1 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + cmexpdhd fr10,62,fr12,cc4,1 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + cmexpdhd fr10,63,fr12,cc4,1 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc1,0 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + cmexpdhd fr10,1,fr12,cc1,0 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + cmexpdhd fr10,62,fr12,cc5,0 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + cmexpdhd fr10,63,fr12,cc5,0 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x2222,0x2222,fr13 + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,1,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,62,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,63,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,1,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,62,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,63,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc2,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,1,fr12,cc2,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,62,fr12,cc6,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,63,fr12,cc6,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc3,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,1,fr12,cc3,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,62,fr12,cc7,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,63,fr12,cc7,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + pass diff --git a/sim/testsuite/sim/frv/cmexpdhw.cgs b/sim/testsuite/sim/frv/cmexpdhw.cgs new file mode 100644 index 00000000000..330d404562b --- /dev/null +++ b/sim/testsuite/sim/frv/cmexpdhw.cgs @@ -0,0 +1,91 @@ +# frv testcase for cmexpdhw $FRi,$s6,$FRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmexpdhw +cmexpdhw: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc0,1 + test_fr_limmed 0xdead,0xdead,fr12 + + cmexpdhw fr10,1,fr12,cc0,1 + test_fr_limmed 0xbeef,0xbeef,fr12 + + cmexpdhw fr10,62,fr12,cc4,1 + test_fr_limmed 0xdead,0xdead,fr12 + + cmexpdhw fr10,63,fr12,cc4,1 + test_fr_limmed 0xbeef,0xbeef,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc1,0 + test_fr_limmed 0xdead,0xdead,fr12 + + cmexpdhw fr10,1,fr12,cc1,0 + test_fr_limmed 0xbeef,0xbeef,fr12 + + cmexpdhw fr10,62,fr12,cc5,0 + test_fr_limmed 0xdead,0xdead,fr12 + + cmexpdhw fr10,63,fr12,cc5,0 + test_fr_limmed 0xbeef,0xbeef,fr12 + + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,1,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,62,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,63,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,1,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,62,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,63,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc2,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,1,fr12,cc2,0 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,62,fr12,cc6,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,63,fr12,cc6,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc3,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,1,fr12,cc3,0 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,62,fr12,cc7,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,63,fr12,cc7,0 + test_fr_limmed 0x1111,0x1111,fr12 + + pass diff --git a/sim/testsuite/sim/frv/cmhtob.cgs b/sim/testsuite/sim/frv/cmhtob.cgs new file mode 100644 index 00000000000..a3f00c52cef --- /dev/null +++ b/sim/testsuite/sim/frv/cmhtob.cgs @@ -0,0 +1,103 @@ +# frv testcase for cmhtob $FRj,$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmhtob +cmhtob: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc0,1 + test_fr_limmed 0xadef,0x3478,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc0,1 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc4,1 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc1,0 + test_fr_limmed 0xadef,0x3478,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc1,0 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc5,0 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc2,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc2,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc6,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc3,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc7,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc7,1 + test_fr_limmed 0x1111,0x1111,fr12 + + pass diff --git a/sim/testsuite/sim/frv/cmmachs.cgs b/sim/testsuite/sim/frv/cmmachs.cgs new file mode 100644 index 00000000000..399e66163ef --- /dev/null +++ b/sim/testsuite/sim/frv/cmmachs.cgs @@ -0,0 +1,1631 @@ +# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmmachs +cmmachs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0007,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0001,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xbffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xbffd,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffd,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc003,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc005,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc005,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3ffec006,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x7ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x7ffec006,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc4,1 +;;;;;;;;;;;; + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed -128,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed -128,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 ; saturation + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0007,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0001,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xbffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xbffd,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffd,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc003,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc005,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc005,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3ffec006,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x7ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x7ffec006,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 +; + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass diff --git a/sim/testsuite/sim/frv/cmmachu.cgs b/sim/testsuite/sim/frv/cmmachu.cgs new file mode 100644 index 00000000000..378f0929fc0 --- /dev/null +++ b/sim/testsuite/sim/frv/cmmachu.cgs @@ -0,0 +1,864 @@ +# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmmachu +cmmachu: + set_spr_immed 0x1b1b,cccr + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x00020006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00020006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x40010007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40010007,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x8001,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x8001,0x0007,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x7fff,0x0008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x7fff,0x0008,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x00020006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00020006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x40010007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40010007,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x8001,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x8001,0x0007,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x7fff,0x0008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x7fff,0x0008,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 +; + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + pass diff --git a/sim/testsuite/sim/frv/cmmulhs.cgs b/sim/testsuite/sim/frv/cmmulhs.cgs new file mode 100644 index 00000000000..01ee59822e4 --- /dev/null +++ b/sim/testsuite/sim/frv/cmmulhs.cgs @@ -0,0 +1,814 @@ +# frv testcase for cmmulhs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmmulhs +cmmulhs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -2,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffe,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffe,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x8000,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -2,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffe,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffe,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x8000,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + pass diff --git a/sim/testsuite/sim/frv/cmmulhu.cgs b/sim/testsuite/sim/frv/cmmulhu.cgs new file mode 100644 index 00000000000..9e8fbb881cc --- /dev/null +++ b/sim/testsuite/sim/frv/cmmulhu.cgs @@ -0,0 +1,460 @@ +# frv testcase for cmmulhu $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmmulhu +cmmulhu: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x00010000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00010000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00010000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + pass diff --git a/sim/testsuite/sim/frv/cmnot.cgs b/sim/testsuite/sim/frv/cmnot.cgs new file mode 100644 index 00000000000..cc93c016e20 --- /dev/null +++ b/sim/testsuite/sim/frv/cmnot.cgs @@ -0,0 +1,60 @@ +# frv testcase for cmnot $FRintj,$FRintk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmnot +cmnot: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc0,1 + test_fr_iimmed 0x55555555,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc4,1 + test_fr_iimmed 0x21524110,fr7 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc1,0 + test_fr_iimmed 0x55555555,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc5,0 + test_fr_iimmed 0x21524110,fr7 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc0,0 + test_fr_iimmed 0xaaaaaaaa,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc4,0 + test_fr_iimmed 0xdeadbeef,fr7 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc1,1 + test_fr_iimmed 0xaaaaaaaa,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc5,1 + test_fr_iimmed 0xdeadbeef,fr7 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc2,0 + test_fr_iimmed 0xaaaaaaaa,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc6,1 + test_fr_iimmed 0xdeadbeef,fr7 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc3,0 + test_fr_iimmed 0xaaaaaaaa,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc7,1 + test_fr_iimmed 0xdeadbeef,fr7 + + pass diff --git a/sim/testsuite/sim/frv/cmor.cgs b/sim/testsuite/sim/frv/cmor.cgs new file mode 100644 index 00000000000..ebdc5f2a313 --- /dev/null +++ b/sim/testsuite/sim/frv/cmor.cgs @@ -0,0 +1,101 @@ +# frv testcase for cmor $FRinti,$FRintj,$FRintk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmor +cmor: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc4,1 + test_fr_iimmed 0xdeadbeef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc5,0 + test_fr_iimmed 0xdeadbeef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc4,0 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc5,1 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc2,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc2,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc6,0 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc3,1 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc3,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc7,1 + test_fr_iimmed 0x0000beef,fr8 + pass diff --git a/sim/testsuite/sim/frv/cmov.cgs b/sim/testsuite/sim/frv/cmov.cgs new file mode 100644 index 00000000000..236bb20f086 --- /dev/null +++ b/sim/testsuite/sim/frv/cmov.cgs @@ -0,0 +1,54 @@ +# frv testcase for cmov $GRi,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmov +cmov: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cmov gr7,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0xdeadbeef,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cmov gr7,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00007fff,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cmov gr7,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00007fff,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cmov gr7,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 0xdeadbeef,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + cmov gr7,gr8,cc2,0 + test_icc 1 0 0 0 icc2 + test_gr_immed 0xdeadbeef,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + cmov gr7,gr8,cc3,0 + test_icc 1 0 0 0 icc3 + test_gr_immed 0xdeadbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cmovfg.cgs b/sim/testsuite/sim/frv/cmovfg.cgs new file mode 100644 index 00000000000..4109842cfa4 --- /dev/null +++ b/sim/testsuite/sim/frv/cmovfg.cgs @@ -0,0 +1,84 @@ +# frv testcase for cmovfg $FRk,$GRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmovfg +cmovfg: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc0,0 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc4,0 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc1,1 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc5,1 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc2,0 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc2,1 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc3,1 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc7,0 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/cmovfgd.cgs b/sim/testsuite/sim/frv/cmovfgd.cgs new file mode 100644 index 00000000000..5d1757d1f38 --- /dev/null +++ b/sim/testsuite/sim/frv/cmovfgd.cgs @@ -0,0 +1,132 @@ +# frv testcase for cmovfgd $FRk,$GRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmovfgd +cmovfgd: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc0,0 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc4,0 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc1,1 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc5,1 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc2,0 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc6,1 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc3,1 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc7,0 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + pass diff --git a/sim/testsuite/sim/frv/cmovgf.cgs b/sim/testsuite/sim/frv/cmovgf.cgs new file mode 100644 index 00000000000..58ed1d85356 --- /dev/null +++ b/sim/testsuite/sim/frv/cmovgf.cgs @@ -0,0 +1,84 @@ +# frv testcase for cmovgf $GRj,$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmovgf +cmovgf: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc6,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc7,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + pass diff --git a/sim/testsuite/sim/frv/cmovgfd.cgs b/sim/testsuite/sim/frv/cmovgfd.cgs new file mode 100644 index 00000000000..67bb2728508 --- /dev/null +++ b/sim/testsuite/sim/frv/cmovgfd.cgs @@ -0,0 +1,132 @@ +# frv testcase for cmovgfd $GRj,$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmovgfd +cmovgfd: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc6,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc7,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + pass diff --git a/sim/testsuite/sim/frv/cmp.cgs b/sim/testsuite/sim/frv/cmp.cgs new file mode 100644 index 00000000000..e6694c14a7c --- /dev/null +++ b/sim/testsuite/sim/frv/cmp.cgs @@ -0,0 +1,31 @@ +# frv testcase for cmp $GRi,$GRj,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global cmp +cmp: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + cmp gr8,gr7,icc0 + test_icc 0 0 0 0 icc0 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + cmp gr8,gr7,icc0 + test_icc 0 0 1 0 icc0 + + set_icc 0x0b,0 ; Set mask opposite of expected + cmp gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + + set_gr_immed 0,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + cmp gr8,gr7,icc0 + test_icc 1 0 0 1 icc0 + + pass diff --git a/sim/testsuite/sim/frv/cmpb.cgs b/sim/testsuite/sim/frv/cmpb.cgs new file mode 100644 index 00000000000..72d9920272b --- /dev/null +++ b/sim/testsuite/sim/frv/cmpb.cgs @@ -0,0 +1,41 @@ +# frv testcase for cmpb $GRi,$GRj,$ICCi_1 +# mach: fr400 + + .include "testutils.inc" + + start + + .global cmpb +cmpb: + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xdead,0xbeef,gr8 + set_icc 0x00,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 1 1 1 1 icc0 + + set_gr_limmed 0x21ad,0xbeef,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 0 1 1 1 icc0 + + set_gr_limmed 0xde52,0xbeef,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 1 0 1 1 icc0 + + set_gr_limmed 0xdead,0x41ef,gr8 + set_icc 0x02,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 1 1 0 1 icc0 + + set_gr_limmed 0xdead,0xbe10,gr8 + set_icc 0x01,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 1 1 1 0 icc0 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 0 0 0 0 icc0 + + pass diff --git a/sim/testsuite/sim/frv/cmpba.cgs b/sim/testsuite/sim/frv/cmpba.cgs new file mode 100644 index 00000000000..2806dc2db28 --- /dev/null +++ b/sim/testsuite/sim/frv/cmpba.cgs @@ -0,0 +1,41 @@ +# frv testcase for cmpba $GRi,$GRj,$ICCi_1 +# mach: fr400 + + .include "testutils.inc" + + start + + .global cmpba +cmpba: + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xdead,0xbeef,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0x21ad,0xbeef,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0xde52,0xbeef,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0xdead,0x41ef,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0xdead,0xbe10,gr8 + set_icc 0x03,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 0 icc0 + + pass diff --git a/sim/testsuite/sim/frv/cmpi.cgs b/sim/testsuite/sim/frv/cmpi.cgs new file mode 100644 index 00000000000..a8324db5531 --- /dev/null +++ b/sim/testsuite/sim/frv/cmpi.cgs @@ -0,0 +1,50 @@ +# frv testcase for cmpi $GRi,$s12,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global cmpi +cmpi: + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + cmpi gr8,1,icc0 + test_icc 0 0 0 0 icc0 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + cmpi gr8,1,icc0 + test_icc 0 0 1 0 icc0 + + set_gr_immed 0x1ff,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cmpi gr8,0x1ff,icc0 + test_icc 0 1 0 0 icc0 + + set_gr_immed 0,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + cmpi gr8,1,icc0 + test_icc 1 0 0 1 icc0 + + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpi gr8,-1,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + cmpi gr8,-1,icc0 + test_icc 1 0 0 1 icc0 + + set_gr_immed -512,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cmpi gr8,-512,icc0 + test_icc 0 1 0 0 icc0 + + set_gr_immed 0,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpi gr8,-1,icc0 + test_icc 0 0 0 1 icc0 + + pass diff --git a/sim/testsuite/sim/frv/cmqmachs.cgs b/sim/testsuite/sim/frv/cmqmachs.cgs new file mode 100644 index 00000000000..a0f28d38dd6 --- /dev/null +++ b/sim/testsuite/sim/frv/cmqmachs.cgs @@ -0,0 +1,1268 @@ +# frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmqmachs +cmqmachs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 +; + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + pass + + diff --git a/sim/testsuite/sim/frv/cmqmachu.cgs b/sim/testsuite/sim/frv/cmqmachu.cgs new file mode 100644 index 00000000000..32dabb8988c --- /dev/null +++ b/sim/testsuite/sim/frv/cmqmachu.cgs @@ -0,0 +1,876 @@ +# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmqmachu +cmqmachu: + set_spr_immed 0x1b1b,cccr + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8000,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00018000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00018000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff8007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff8007,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4001,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4001,0x8000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x3ffd,0x8008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x3ffd,0x8008,acc1 + test_accg_immed 1,accg2 + test_acc_limmed 0x3fff,0x8001,acc2 + test_accg_immed 1,accg3 + test_acc_limmed 0x3fff,0x8001,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8000,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00018000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00018000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff8007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff8007,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4001,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4001,0x8000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x3ffd,0x8008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x3ffd,0x8008,acc1 + test_accg_immed 1,accg2 + test_acc_limmed 0x3fff,0x8001,acc2 + test_accg_immed 1,accg3 + test_acc_limmed 0x3fff,0x8001,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 +; + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/cmqmulhs.cgs b/sim/testsuite/sim/frv/cmqmulhs.cgs new file mode 100644 index 00000000000..b3157373bfc --- /dev/null +++ b/sim/testsuite/sim/frv/cmqmulhs.cgs @@ -0,0 +1,734 @@ +# frv testcase for cmqmulhs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmqmulhs +cmqmulhs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x0001,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -2,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -2,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffe,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffe,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xc000,0x8000,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xc000,0x8000,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x40000000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x40000000,acc3 + + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x0001,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -2,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -2,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffe,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffe,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xc000,0x8000,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xc000,0x8000,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x40000000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x40000000,acc3 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 +; + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + pass diff --git a/sim/testsuite/sim/frv/cmqmulhu.cgs b/sim/testsuite/sim/frv/cmqmulhu.cgs new file mode 100644 index 00000000000..36f0c2f45b1 --- /dev/null +++ b/sim/testsuite/sim/frv/cmqmulhu.cgs @@ -0,0 +1,464 @@ +# frv testcase for cmqmulhu $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmqmulhu +cmqmulhu: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00010000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00010000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4000,0x0000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xfffe,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xfffe,0x0001,acc3 + + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00010000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00010000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4000,0x0000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xfffe,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xfffe,0x0001,acc3 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 +; + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + pass diff --git a/sim/testsuite/sim/frv/cmsubhss.cgs b/sim/testsuite/sim/frv/cmsubhss.cgs new file mode 100644 index 00000000000..92f7d1260ac --- /dev/null +++ b/sim/testsuite/sim/frv/cmsubhss.cgs @@ -0,0 +1,562 @@ +# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmsubhss +cmsubhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0x4111,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x4111,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x1235,0x5679,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc4,1 + cmsubhss fr11,fr10,fr13,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x8000,0x8000,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0x4111,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x4111,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x1235,0x5679,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc5,0 + cmsubhss fr11,fr10,fr13,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x8000,0x8000,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc4,0 + cmsubhss fr11,fr10,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc5,1 + cmsubhss fr11,fr10,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc6,1 + cmsubhss fr11,fr10,fr13,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set +; + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc7,1 + cmsubhss fr11,fr10,fr13,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/sim/frv/cmsubhus.cgs b/sim/testsuite/sim/frv/cmsubhus.cgs new file mode 100644 index 00000000000..9348edc4b21 --- /dev/null +++ b/sim/testsuite/sim/frv/cmsubhus.cgs @@ -0,0 +1,442 @@ +# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmsubhus +cmsubhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x7ffc,0x7ffd,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc4,1 + cmsubhus fr10,fr11,fr13,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x0000,0x0000,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x7ffc,0x7ffd,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc5,0 + cmsubhus fr10,fr11,fr13,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x0000,0x0000,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc4,0 + cmsubhus fr10,fr11,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc5,1 + cmsubhus fr10,fr11,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc6,0 + cmsubhus fr10,fr11,fr13,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set +; + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc7,0 + cmsubhus fr10,fr11,fr13,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/sim/frv/cmxor.cgs b/sim/testsuite/sim/frv/cmxor.cgs new file mode 100644 index 00000000000..236e2fed0e4 --- /dev/null +++ b/sim/testsuite/sim/frv/cmxor.cgs @@ -0,0 +1,132 @@ +# frv testcase for cmxor $FRinti,$FRintj,$FRintk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmxor +cmxor: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc4,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc4,1 + test_fr_iimmed 0xdeadbeef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc5,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc5,0 + test_fr_iimmed 0xdeadbeef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc4,0 + test_fr_iimmed 0xaaaaaaaa,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc4,0 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc5,1 + test_fr_iimmed 0xaaaaaaaa,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc5,1 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc2,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc2,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc6,0 + test_fr_iimmed 0xaaaaaaaa,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc6,1 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc3,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc3,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc7,0 + test_fr_iimmed 0xaaaaaaaa,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc7,1 + test_fr_iimmed 0x0000beef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/cnot.cgs b/sim/testsuite/sim/frv/cnot.cgs new file mode 100644 index 00000000000..3169887914d --- /dev/null +++ b/sim/testsuite/sim/frv/cnot.cgs @@ -0,0 +1,60 @@ +# frv testcase for cnot $GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global cnot +cnot: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc0,1 + test_gr_limmed 0x5555,0x5555,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc4,1 + test_gr_limmed 0x2152,0x4110,gr7 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc0,0 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr7 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc1,0 + test_gr_limmed 0x5555,0x5555,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc5,0 + test_gr_limmed 0x2152,0x4110,gr7 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc1,1 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr7 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc2,0 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc6,1 + test_gr_limmed 0xdead,0xbeef,gr7 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc3,0 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc7,1 + test_gr_limmed 0xdead,0xbeef,gr7 + + pass diff --git a/sim/testsuite/sim/frv/commitfa.cgs b/sim/testsuite/sim/frv/commitfa.cgs new file mode 100644 index 00000000000..8208cab5226 --- /dev/null +++ b/sim/testsuite/sim/frv/commitfa.cgs @@ -0,0 +1,61 @@ +# frv testcase for commitfa +# mach: frv + + .include "testutils.inc" + + start + + .global commitfa +commitfa: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x190,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + set_gr_immed 0,gr15 + + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 + set_spr_immed 0x00000000,fner1 + set_spr_immed 0x00000000,fner0 + set_spr_addr bad,lr + commitfa ; should be nop + test_spr_immed 0x00000000,fner1 + test_spr_immed 0x00000000,fner0 + test_spr_immed 0xd4800001,nesr0 + test_spr_gr neear0,sp + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xf4800801,nesr2 + test_spr_gr neear2,sp + + or_spr_immed 0x00100000,fner1 + or_spr_immed 0x00200000,fner1 + or_spr_immed 0x00100000,fner0 + set_spr_addr ok,lr + set_gr_addr com1,gr16 +com1: commitfa + test_gr_immed 1,gr15 + + pass + +ok: test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr16 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear + test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear + test_spr_immed 0x00000000,fner1 + test_spr_immed 0x00000000,fner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0,nesr2 + test_spr_immed 0,neear2 + inc_gr_immed 1,gr15 + rett 0 + +bad: fail diff --git a/sim/testsuite/sim/frv/commitfr.cgs b/sim/testsuite/sim/frv/commitfr.cgs new file mode 100644 index 00000000000..97491dc38f2 --- /dev/null +++ b/sim/testsuite/sim/frv/commitfr.cgs @@ -0,0 +1,61 @@ +# frv testcase for commitfr $FRk +# mach: frv + + .include "testutils.inc" + + start + + .global commitfr +commitfr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x190,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + set_gr_immed 0,gr15 + + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 + set_spr_immed 0x00000000,fner1 + set_spr_immed 0x00000000,fner0 + set_spr_addr bad,lr + commitfr fr20 ; should be nop + test_spr_immed 0x00000000,fner1 + test_spr_immed 0x00000000,fner0 + test_spr_immed 0xd4800001,nesr0 + test_spr_gr neear0,sp + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xf4800801,nesr2 + test_spr_gr neear2,sp + + or_spr_immed 0x00100000,fner1 + or_spr_immed 0x00200000,fner1 + or_spr_immed 0x00100000,fner0 + set_spr_addr ok,lr + set_gr_addr com1,gr16 +com1: commitfr fr20 + test_gr_immed 1,gr15 + + pass + +ok: test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr16 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear + test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear + test_spr_immed 0x00200000,fner1 + test_spr_immed 0x00100000,fner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xf4800801,nesr2 + test_spr_gr neear2,sp + inc_gr_immed 1,gr15 + rett 0 + +bad: fail diff --git a/sim/testsuite/sim/frv/commitga.cgs b/sim/testsuite/sim/frv/commitga.cgs new file mode 100644 index 00000000000..57100b82284 --- /dev/null +++ b/sim/testsuite/sim/frv/commitga.cgs @@ -0,0 +1,62 @@ +# frv testcase for commitga +# mach: frv + + .include "testutils.inc" + + start + + .global commitga +commitga: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x190,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + set_gr_immed 0,gr15 + + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 + set_spr_immed 0x00000000,gner1 + set_spr_immed 0x00000000,gner0 + set_spr_addr bad,lr + commitga ; should be a nop + test_gr_immed 0,gr15 + test_spr_immed 0x00000000,gner1 + test_spr_immed 0x00000000,gner0 + test_spr_immed 0x94800001,nesr0 + test_spr_gr neear0,sp + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xb4800801,nesr2 + test_spr_gr neear2,sp + + or_spr_immed 0x00100000,gner1 + or_spr_immed 0x00200000,gner1 + or_spr_immed 0x00100000,gner0 + set_spr_addr ok,lr + set_gr_addr com1,gr16 +com1: commitga + test_gr_immed 1,gr15 + + pass + +ok: test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr16 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear + test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear + test_spr_immed 0x00000000,gner1 + test_spr_immed 0x00000000,gner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0,nesr2 + test_spr_immed 0,neear0 + inc_gr_immed 1,gr15 + rett 0 + +bad: fail diff --git a/sim/testsuite/sim/frv/commitgr.cgs b/sim/testsuite/sim/frv/commitgr.cgs new file mode 100644 index 00000000000..45553da052e --- /dev/null +++ b/sim/testsuite/sim/frv/commitgr.cgs @@ -0,0 +1,62 @@ +# frv testcase for commitgr $GRk +# mach: frv + + .include "testutils.inc" + + start + + .global commitgr +commitgr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x190,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + set_gr_immed 0,gr15 + + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 + set_spr_immed 0x00000000,gner1 + set_spr_immed 0x00000000,gner0 + set_spr_addr bad,lr + commitgr gr20 ; should only clear ne flags + test_gr_immed 0,gr15 + test_spr_immed 0x00000000,gner1 + test_spr_immed 0x00000000,gner0 + test_spr_immed 0x94800001,nesr0 + test_spr_gr neear0,sp + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xb4800801,nesr2 + test_spr_gr neear2,sp + + or_spr_immed 0x00100000,gner1 + or_spr_immed 0x00200000,gner1 + or_spr_immed 0x00100000,gner0 + set_spr_addr ok,lr + set_gr_addr com1,gr16 +com1: commitgr gr20 + test_gr_immed 1,gr15 + + pass + +ok: test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr16 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear + test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear + test_spr_immed 0x00200000,gner1 + test_spr_immed 0x00100000,gner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xb4800801,nesr2 + test_spr_gr neear2,sp + inc_gr_immed 1,gr15 + rett 0 + +bad: fail diff --git a/sim/testsuite/sim/frv/cop1.cgs b/sim/testsuite/sim/frv/cop1.cgs new file mode 100644 index 00000000000..652e3550e0e --- /dev/null +++ b/sim/testsuite/sim/frv/cop1.cgs @@ -0,0 +1,14 @@ +# frv testcase for cop1 $s6_1,$CPRi,$CPRj,$CPRk +# mach: frv + + .include "testutils.inc" + + start + + .global cop1 +cop1: + cop1 0,cpr0,cpr15,cpr31 + cop1 31,cpr32,cpr45,cpr63 + cop1 -32,cpr32,cpr45,cpr63 + + pass diff --git a/sim/testsuite/sim/frv/cop2.cgs b/sim/testsuite/sim/frv/cop2.cgs new file mode 100644 index 00000000000..858ed2b4ce2 --- /dev/null +++ b/sim/testsuite/sim/frv/cop2.cgs @@ -0,0 +1,14 @@ +# frv testcase for cop2 $s6_1,$CPRi,$CPRj,$CPRk +# mach: frv + + .include "testutils.inc" + + start + + .global cop2 +cop2: + cop2 0,cpr0,cpr15,cpr31 + cop2 31,cpr32,cpr45,cpr63 + cop2 -32,cpr32,cpr45,cpr63 + + pass diff --git a/sim/testsuite/sim/frv/cor.cgs b/sim/testsuite/sim/frv/cor.cgs new file mode 100644 index 00000000000..ef19985b672 --- /dev/null +++ b/sim/testsuite/sim/frv/cor.cgs @@ -0,0 +1,138 @@ +# frv testcase for cor $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cor +cor: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc0,1 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc4,1 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc0,0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc4,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc1,0 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc5,0 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc1,1 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc5,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc2,0 + test_icc 0 1 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 0 icc2 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc6,1 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc3,0 + test_icc 0 1 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 0 icc3 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc7,1 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x0000,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/corcc.cgs b/sim/testsuite/sim/frv/corcc.cgs new file mode 100644 index 00000000000..527665802e6 --- /dev/null +++ b/sim/testsuite/sim/frv/corcc.cgs @@ -0,0 +1,138 @@ +# frv testcase for corcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global corcc +corcc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc0,1 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc1,0 + test_icc 0 1 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 0 1 icc1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 0 icc2 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc6,1 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 0 icc3 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc7,1 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x0000,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cscan.cgs b/sim/testsuite/sim/frv/cscan.cgs new file mode 100644 index 00000000000..505bb5a384e --- /dev/null +++ b/sim/testsuite/sim/frv/cscan.cgs @@ -0,0 +1,394 @@ +# frv testcase for cscan $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cscan +cscan: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0x5555,gr8 + cscan gr7,gr8,gr9,cc0,1 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0x5555,gr8 + + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + cscan gr7,gr8,gr9,cc0,1 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + cscan gr7,gr8,gr9,cc0,1 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + cscan gr7,gr8,gr9,cc0,1 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc0,1 + test_gr_immed 0,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc4,1 + test_gr_immed 2,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc4,1 + test_gr_immed 16,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc4,1 + test_gr_immed 31,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc4,1 + test_gr_immed 7,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0x7fff,gr9 + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc0,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xaaaa,0xaaab,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc0,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaab,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc0,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5554,gr8 + cscan gr7,gr8,gr9,cc0,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5554,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc0,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc4,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc4,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc4,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc4,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + cscan gr7,gr8,gr9,cc1,0 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + cscan gr7,gr8,gr9,cc1,0 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + cscan gr7,gr8,gr9,cc1,0 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + cscan gr7,gr8,gr9,cc1,0 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc1,0 + test_gr_immed 0,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc5,0 + test_gr_immed 2,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc5,0 + test_gr_immed 16,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc5,0 + test_gr_immed 31,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc5,0 + test_gr_immed 7,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0x7fff,gr9 + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc1,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xaaaa,0xaaab,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc1,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaab,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc1,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5554,gr8 + cscan gr7,gr8,gr9,cc1,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5554,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc1,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc5,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc5,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc5,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc5,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0x7fff,gr9 + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc2,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xaaaa,0xaaab,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc2,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaab,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc2,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5554,gr8 + cscan gr7,gr8,gr9,cc2,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5554,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc2,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc6,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc6,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc6,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc6,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0x7fff,gr9 + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc3,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xaaaa,0xaaab,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc3,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaab,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc3,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5554,gr8 + cscan gr7,gr8,gr9,cc3,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5554,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc3,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc7,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc7,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc7,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc7,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/sim/frv/csdiv.cgs b/sim/testsuite/sim/frv/csdiv.cgs new file mode 100644 index 00000000000..c6bfb976967 --- /dev/null +++ b/sim/testsuite/sim/frv/csdiv.cgs @@ -0,0 +1,190 @@ +# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csdiv +csdiv: + set_spr_immed 0x1b1b,cccr + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_addr e1,gr17 + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e1: csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_addr e2,gr17 + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e2: csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed 2,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/csll.cgs b/sim/testsuite/sim/frv/csll.cgs new file mode 100644 index 00000000000..0186756fed6 --- /dev/null +++ b/sim/testsuite/sim/frv/csll.cgs @@ -0,0 +1,180 @@ +# frv testcase for csll $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csll +csll: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc0,1 + test_icc 1 1 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc0,1 + test_icc 1 1 1 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc0,0 + test_icc 1 1 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc4,0 + test_icc 0 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc1,0 + test_icc 1 1 0 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc1,0 + test_icc 1 1 1 1 icc1 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc1,1 + test_icc 1 1 0 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc5,1 + test_icc 0 1 1 1 icc1 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc2,0 + test_icc 1 1 0 1 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc6,1 + test_icc 0 1 1 1 icc2 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc3,0 + test_icc 1 1 0 1 icc3 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc7,1 + test_icc 0 1 1 1 icc3 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_immed 2,gr8 + + pass diff --git a/sim/testsuite/sim/frv/csllcc.cgs b/sim/testsuite/sim/frv/csllcc.cgs new file mode 100644 index 00000000000..0c5b9af8ae4 --- /dev/null +++ b/sim/testsuite/sim/frv/csllcc.cgs @@ -0,0 +1,180 @@ +# frv testcase for csllcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csllcc +csllcc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc4,1 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc4,1 + test_icc 0 1 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc0,0 + test_icc 1 1 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc4,0 + test_icc 0 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc5,0 + test_icc 1 0 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc5,0 + test_icc 0 1 1 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc1,1 + test_icc 1 1 0 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc5,1 + test_icc 0 1 1 1 icc1 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc2,0 + test_icc 1 1 0 1 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc6,1 + test_icc 0 1 1 1 icc2 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc3,0 + test_icc 1 1 0 1 icc3 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc7,1 + test_icc 0 1 1 1 icc3 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_immed 2,gr8 + + pass diff --git a/sim/testsuite/sim/frv/csmul.cgs b/sim/testsuite/sim/frv/csmul.cgs new file mode 100644 index 00000000000..25346e7d18f --- /dev/null +++ b/sim/testsuite/sim/frv/csmul.cgs @@ -0,0 +1,1044 @@ +# frv testcase for csmul $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csmul +csmul: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + pass diff --git a/sim/testsuite/sim/frv/csmulcc.cgs b/sim/testsuite/sim/frv/csmulcc.cgs new file mode 100644 index 00000000000..26c7e66e136 --- /dev/null +++ b/sim/testsuite/sim/frv/csmulcc.cgs @@ -0,0 +1,1380 @@ +# frv testcase for csmulcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csmulcc +csmulcc: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0xc,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0xd,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xe,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0xb,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x8,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0xd,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0xe,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0xf,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 1 icc0 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0xc,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x5,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x6,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x7,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x4,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0x9,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xa,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x4,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x5,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x6,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x7,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xc,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xd,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0xe,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0xc,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0xd,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xe,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xf,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 0 0 0 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x1,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 0 0 1 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x2,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 0 1 0 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0x3,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 0 1 1 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x4,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0x5,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0x6,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 1 0 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0x7,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 1 1 icc0 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x8,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x9,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 1 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xa,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xb,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xc,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 1 0 0 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0xd,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 1 0 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xe,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 1 1 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x0,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 0 0 0 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x1,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 0 0 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x2,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 0 1 0 icc0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x3,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 0 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x4,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 0 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x5,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0x6,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 1 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 1 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x8,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x9,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 1 icc0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xa,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xb,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0xc,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0xd,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xe,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0xb,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x8,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 1 0 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0xd,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0xe,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 0 icc1 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0xf,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 1 icc1 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0xc,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x5,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 1 icc1 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x6,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x7,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 1 icc1 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x4,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0x9,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 1 0 1 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xa,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 1 1 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x4,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x5,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x6,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x7,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xc,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xd,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0xe,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 1 icc1 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0xc,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0xd,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xe,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 0 icc1 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xf,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 1 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 0 0 0 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x1,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 0 0 1 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x2,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 0 1 0 icc1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0x3,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 0 1 1 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x4,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0x5,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0x6,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 1 0 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0x7,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 1 1 icc1 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x8,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x9,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 1 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xa,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xb,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xc,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 1 0 0 icc1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0xd,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 1 0 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xe,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 1 1 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 1 1 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x0,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 0 0 0 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x1,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 0 0 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x2,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 0 1 0 icc1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x3,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 0 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x4,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 0 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x5,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0x6,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 1 0 icc1 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 1 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x8,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x9,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 1 icc1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xa,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xb,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 0 0 0 0 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x1,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 0 0 0 1 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x2,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 0 0 1 0 icc2 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0x3,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 0 0 1 1 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x4,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 0 0 icc2 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0x5,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 0 1 0 1 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0x6,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 0 1 1 0 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0x7,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 0 1 1 1 icc2 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x8,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 1 0 0 0 icc2 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x9,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 1 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xa,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xb,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 1 0 1 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xc,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 1 1 0 0 icc2 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0xd,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 1 1 0 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xe,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 1 1 1 0 icc2 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 1 1 1 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x0,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 0 0 0 0 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x1,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 0 0 0 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x2,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 0 0 1 0 icc2 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x3,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 0 0 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x4,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 0 1 0 0 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x5,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0x6,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 0 1 1 0 icc2 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 0 1 1 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x8,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 1 0 0 0 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x9,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 1 icc2 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xa,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xb,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 0 0 0 0 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x1,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 0 0 0 1 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x2,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 0 0 1 0 icc3 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0x3,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 0 0 1 1 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x4,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 0 0 icc3 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0x5,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 0 1 0 1 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0x6,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 0 1 1 0 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0x7,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 0 1 1 1 icc3 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x8,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 1 0 0 0 icc3 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x9,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 1 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xa,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xb,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 1 0 1 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xc,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 1 1 0 0 icc3 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0xd,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 1 1 0 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xe,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 1 1 1 0 icc3 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 1 1 1 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x0,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 0 0 0 0 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x1,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 0 0 0 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x2,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 0 0 1 0 icc3 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x3,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 0 0 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x4,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 0 1 0 0 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x5,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0x6,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 0 1 1 0 icc3 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 0 1 1 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x8,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 1 0 0 0 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x9,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 1 icc3 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xa,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xb,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + pass diff --git a/sim/testsuite/sim/frv/csra.cgs b/sim/testsuite/sim/frv/csra.cgs new file mode 100644 index 00000000000..f59de057d68 --- /dev/null +++ b/sim/testsuite/sim/frv/csra.cgs @@ -0,0 +1,180 @@ +# frv testcase for csra $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csra +csra: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc0,1 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc0,1 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc4,1 + test_icc 1 1 1 1 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc4,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc1,0 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc1,0 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc5,0 + test_icc 1 1 1 1 icc1 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc5,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc6,1 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc7,1 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_limmed 0x4000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/csracc.cgs b/sim/testsuite/sim/frv/csracc.cgs new file mode 100644 index 00000000000..64d4cbfb56a --- /dev/null +++ b/sim/testsuite/sim/frv/csracc.cgs @@ -0,0 +1,180 @@ +# frv testcase for csracc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csracc +csracc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc0,1 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc4,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc1,0 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc5,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc6,1 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc7,1 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_limmed 0x4000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/csrl.cgs b/sim/testsuite/sim/frv/csrl.cgs new file mode 100644 index 00000000000..7a71db4bddb --- /dev/null +++ b/sim/testsuite/sim/frv/csrl.cgs @@ -0,0 +1,180 @@ +# frv testcase for csrl $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csrl +csrl: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc0,1 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc0,1 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc4,1 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc4,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc1,0 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc1,0 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc5,0 + test_icc 1 1 1 1 icc1 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc5,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc6,1 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc7,1 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_limmed 0x4000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/csrlcc.cgs b/sim/testsuite/sim/frv/csrlcc.cgs new file mode 100644 index 00000000000..fb89456f5a5 --- /dev/null +++ b/sim/testsuite/sim/frv/csrlcc.cgs @@ -0,0 +1,180 @@ +# frv testcase for csrlcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csrlcc +csrlcc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc0,1 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc4,1 + test_icc 0 0 1 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc4,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc1,0 + test_icc 0 0 1 0 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc5,0 + test_icc 0 0 1 0 icc1 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc5,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc6,1 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc7,1 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_limmed 0x4000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cst.cgs b/sim/testsuite/sim/frv/cst.cgs new file mode 100644 index 00000000000..8244edf0d27 --- /dev/null +++ b/sim/testsuite/sim/frv/cst.cgs @@ -0,0 +1,126 @@ +# frv testcase for cst $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global cst +cst: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xffff,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xeeee,0xffff,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xcccc,0xdddd,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xffff,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xeeee,0xffff,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xcccc,0xdddd,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + pass diff --git a/sim/testsuite/sim/frv/cstb.cgs b/sim/testsuite/sim/frv/cstb.cgs new file mode 100644 index 00000000000..7b62558d83c --- /dev/null +++ b/sim/testsuite/sim/frv/cstb.cgs @@ -0,0 +1,120 @@ +# frv testcase for cstb $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xeeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc4,1 + inc_gr_immed -4,sp + test_mem_limmed 0xffad,0xee00,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc4,0 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xeeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc5,0 + inc_gr_immed -4,sp + test_mem_limmed 0xffad,0xee00,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc5,1 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc6,0 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc7,1 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/cstbf.cgs b/sim/testsuite/sim/frv/cstbf.cgs new file mode 100644 index 00000000000..23e1ae432de --- /dev/null +++ b/sim/testsuite/sim/frv/cstbf.cgs @@ -0,0 +1,120 @@ +# frv testcase for cstbf $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstbf +cstbf: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xaaef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xffad,0xaabb,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xaaef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xffad,0xaabb,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cstbfu.cgs b/sim/testsuite/sim/frv/cstbfu.cgs new file mode 100644 index 00000000000..01943be1e88 --- /dev/null +++ b/sim/testsuite/sim/frv/cstbfu.cgs @@ -0,0 +1,152 @@ +# frv testcase for cstbfu $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstbfu +cstbfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,gr21 + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xaaef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 1,gr21 + inc_gr_immed 2,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xffad,0xaabb,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,gr21 + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xaaef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 1,gr21 + inc_gr_immed 2,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xffad,0xaabb,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + pass diff --git a/sim/testsuite/sim/frv/cstbu.cgs b/sim/testsuite/sim/frv/cstbu.cgs new file mode 100644 index 00000000000..f8a9d0f1b70 --- /dev/null +++ b/sim/testsuite/sim/frv/cstbu.cgs @@ -0,0 +1,152 @@ +# frv testcase for cstbu $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstbu +cstbu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xbeef,sp + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xeeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 1,gr20 + set_gr_immed -1,gr7 + inc_gr_immed 2,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc4,1 + inc_gr_immed -4,sp + test_mem_limmed 0xffad,0xee00,gr21 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed -1,gr7 + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xbeef,sp + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xeeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 1,gr20 + set_gr_immed -1,gr7 + inc_gr_immed 2,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc5,0 + inc_gr_immed -4,sp + test_mem_limmed 0xffad,0xee00,gr21 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed -1,gr7 + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed -1,gr7 + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed -1,gr7 + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cstd.cgs b/sim/testsuite/sim/frv/cstd.cgs new file mode 100644 index 00000000000..6904414a73f --- /dev/null +++ b/sim/testsuite/sim/frv/cstd.cgs @@ -0,0 +1,221 @@ +# frv testcase for cstd $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global cstd +cstd: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + pass diff --git a/sim/testsuite/sim/frv/cstdf.cgs b/sim/testsuite/sim/frv/cstdf.cgs new file mode 100644 index 00000000000..fabbe93f3b6 --- /dev/null +++ b/sim/testsuite/sim/frv/cstdf.cgs @@ -0,0 +1,222 @@ +# frv testcase for cstdf $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstdf +cstdf: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc0,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc0,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xaaaa,0xaaaa,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbbbb,0xbbbb,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc4,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xcccc,0xcccc,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdddd,0xdddd,gr22 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc0,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc0,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc4,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc1,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc1,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xaaaa,0xaaaa,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbbbb,0xbbbb,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc5,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xcccc,0xcccc,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdddd,0xdddd,gr22 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc1,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc1,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc5,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc2,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc2,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc6,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc3,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc3,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc7,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + pass diff --git a/sim/testsuite/sim/frv/cstdfu.cgs b/sim/testsuite/sim/frv/cstdfu.cgs new file mode 100644 index 00000000000..b489bc900c6 --- /dev/null +++ b/sim/testsuite/sim/frv/cstdfu.cgs @@ -0,0 +1,248 @@ +# frv testcase for cstdfu $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstdfu +cstdfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc0,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc0,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xaaaa,0xaaaa,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbbbb,0xbbbb,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc4,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xcccc,0xcccc,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdddd,0xdddd,gr22 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc0,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_gr sp,gr23 + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc0,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + inc_gr_immed 16,sp + set_gr_gr sp,gr23 + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc4,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc1,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc1,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xaaaa,0xaaaa,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbbbb,0xbbbb,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc5,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xcccc,0xcccc,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdddd,0xdddd,gr22 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc1,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_gr sp,gr23 + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc1,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + inc_gr_immed 16,sp + set_gr_gr sp,gr23 + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc5,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc2,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_gr sp,gr23 + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc2,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + inc_gr_immed 16,sp + set_gr_gr sp,gr23 + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc6,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc3,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_gr sp,gr23 + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc3,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + inc_gr_immed 16,sp + set_gr_gr sp,gr23 + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc7,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + pass diff --git a/sim/testsuite/sim/frv/cstdu.cgs b/sim/testsuite/sim/frv/cstdu.cgs new file mode 100644 index 00000000000..a996ef6d1b7 --- /dev/null +++ b/sim/testsuite/sim/frv/cstdu.cgs @@ -0,0 +1,251 @@ +# frv testcase for cstdu $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstdu +cstdu: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_gr sp,gr22 + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_gr sp,gr22 + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_gr sp,gr22 + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_gr sp,gr22 + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_gr sp,gr22 + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_gr sp,gr22 + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_gr sp,gr22 + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_gr sp,gr22 + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_gr sp,gr22 + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_gr sp,gr22 + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_gr sp,gr22 + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_gr sp,gr22 + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + pass diff --git a/sim/testsuite/sim/frv/cstf.cgs b/sim/testsuite/sim/frv/cstf.cgs new file mode 100644 index 00000000000..94c0f052e56 --- /dev/null +++ b/sim/testsuite/sim/frv/cstf.cgs @@ -0,0 +1,126 @@ +# frv testcase for cstf $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstf +cstf: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xffff,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xeeee,0xeeee,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xdddd,0xdddd,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xffff,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xeeee,0xeeee,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xdddd,0xdddd,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cstfu.cgs b/sim/testsuite/sim/frv/cstfu.cgs new file mode 100644 index 00000000000..ee450c84334 --- /dev/null +++ b/sim/testsuite/sim/frv/cstfu.cgs @@ -0,0 +1,158 @@ +# frv testcase for cstfu $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstfu +cstfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xffff,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 4,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xdddd,0xdddd,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + inc_gr_immed -4,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + inc_gr_immed 8,gr21 + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xffff,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 4,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xdddd,0xdddd,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + inc_gr_immed -4,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + inc_gr_immed 8,gr21 + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + inc_gr_immed -4,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + inc_gr_immed 8,gr21 + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + inc_gr_immed -4,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + inc_gr_immed 8,gr21 + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + pass diff --git a/sim/testsuite/sim/frv/csth.cgs b/sim/testsuite/sim/frv/csth.cgs new file mode 100644 index 00000000000..b9f743cbd71 --- /dev/null +++ b/sim/testsuite/sim/frv/csth.cgs @@ -0,0 +1,120 @@ +# frv testcase for csth $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csth +csth: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xeeee,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc4,1 + inc_gr_immed -4,sp + test_mem_limmed 0xffff,0xdddd,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc4,0 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xeeee,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc5,0 + inc_gr_immed -4,sp + test_mem_limmed 0xffff,0xdddd,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc5,1 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc6,0 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc7,1 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/csthf.cgs b/sim/testsuite/sim/frv/csthf.cgs new file mode 100644 index 00000000000..21a64c8ae53 --- /dev/null +++ b/sim/testsuite/sim/frv/csthf.cgs @@ -0,0 +1,120 @@ +# frv testcase for csthf $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csthf +csthf: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xaaaa,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xffff,0xbbbb,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xaaaa,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xffff,0xbbbb,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/csthfu.cgs b/sim/testsuite/sim/frv/csthfu.cgs new file mode 100644 index 00000000000..252ae7da0a2 --- /dev/null +++ b/sim/testsuite/sim/frv/csthfu.cgs @@ -0,0 +1,150 @@ +# frv testcase for csthfu $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csthfu +csthfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,gr21 + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xaaaa,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xffff,0xbbbb,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,gr21 + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xaaaa,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xffff,0xbbbb,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + pass diff --git a/sim/testsuite/sim/frv/csthu.cgs b/sim/testsuite/sim/frv/csthu.cgs new file mode 100644 index 00000000000..c7e2255ccaa --- /dev/null +++ b/sim/testsuite/sim/frv/csthu.cgs @@ -0,0 +1,150 @@ +# frv testcase for csthu $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csthu +csthu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + set_gr_limmed 0xdead,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xeeee,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 2,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xffff,0xdddd,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,gr20 + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + set_gr_limmed 0xdead,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xeeee,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 2,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xffff,0xdddd,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cstq.cgs b/sim/testsuite/sim/frv/cstq.cgs new file mode 100644 index 00000000000..6f183322cd7 --- /dev/null +++ b/sim/testsuite/sim/frv/cstq.cgs @@ -0,0 +1,355 @@ +# frv testcase for cstq $GRk,@($GRi,$GRj),$CCi,$cond +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global cstq +cstq: + set_spr_immed 0x1b1b,cccr + + set_gr_gr sp,gr22 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xbeef,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0x1111,0x1111,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x2222,0x2222,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x3333,0x3333,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x4444,0x4444,gr21 + + set_gr_gr gr22,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr22,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xbeef,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0x1111,0x1111,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x2222,0x2222,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x3333,0x3333,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x4444,0x4444,gr21 + + set_gr_gr gr22,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr22,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr22,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + pass diff --git a/sim/testsuite/sim/frv/cstu.cgs b/sim/testsuite/sim/frv/cstu.cgs new file mode 100644 index 00000000000..81a5b82496c --- /dev/null +++ b/sim/testsuite/sim/frv/cstu.cgs @@ -0,0 +1,152 @@ +# frv testcase for cstu $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstu +cstu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xffff,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xeeee,0xffff,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xcccc,0xdddd,gr21 + test_gr_gr sp,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_gr sp,gr20 + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 8,sp + set_gr_gr sp,gr20 + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xffff,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xeeee,0xffff,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xcccc,0xdddd,gr21 + test_gr_gr sp,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_gr sp,gr20 + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 8,sp + set_gr_gr sp,gr20 + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_gr sp,gr20 + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 8,sp + set_gr_gr sp,gr20 + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_gr sp,gr20 + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 8,sp + set_gr_gr sp,gr20 + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/csub.cgs b/sim/testsuite/sim/frv/csub.cgs new file mode 100644 index 00000000000..7d07c147327 --- /dev/null +++ b/sim/testsuite/sim/frv/csub.cgs @@ -0,0 +1,108 @@ +# frv testcase for csub $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csub +csub: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc4,1 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc4,1 + test_gr_limmed 0x7fff,0xffff,gr8 + + csub gr8,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + + csub gr8,gr7,gr8,cc4,1 + test_gr_immed -1,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc4,0 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc4,0 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr8,gr8,cc4,0 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr7,gr8,cc4,0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc5,0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc5,0 + test_gr_limmed 0x7fff,0xffff,gr8 + + csub gr8,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + + csub gr8,gr7,gr8,cc5,0 + test_gr_immed -1,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc5,1 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc5,1 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr8,gr8,cc5,1 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr7,gr8,cc5,1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc6,1 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc6,0 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr8,gr8,cc6,1 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr7,gr8,cc6,0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc7,0 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc7,1 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr8,gr8,cc7,0 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr7,gr8,cc7,1 + test_gr_limmed 0x8000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/csubcc.cgs b/sim/testsuite/sim/frv/csubcc.cgs new file mode 100644 index 00000000000..64cd93b16f5 --- /dev/null +++ b/sim/testsuite/sim/frv/csubcc.cgs @@ -0,0 +1,156 @@ +# frv testcase for csubcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csubcc +csubcc: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc0,1 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_icc 0x0b,0 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc4,1 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc4,1 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc0,0 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x0b,0 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x06,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc4,0 + test_icc 0 1 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc1,0 + test_icc 0 0 1 0 icc1 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_icc 0x0b,1 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc5,0 + test_icc 0 1 0 0 icc1 + test_gr_immed 0,gr8 + + set_icc 0x06,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc5,0 + test_icc 1 0 0 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc1,1 + test_icc 1 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x0b,1 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x06,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc5,1 + test_icc 0 1 1 0 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc2,0 + test_icc 1 1 0 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x0b,2 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc6,1 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x06,2 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc6,1 + test_icc 0 1 1 0 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc3,0 + test_icc 1 1 0 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x0b,3 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc7,1 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x06,3 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc7,1 + test_icc 0 1 1 0 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cswap.cgs b/sim/testsuite/sim/frv/cswap.cgs new file mode 100644 index 00000000000..19a51d5481d --- /dev/null +++ b/sim/testsuite/sim/frv/cswap.cgs @@ -0,0 +1,212 @@ +# frv testcase for cswap @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cswap +cswap: + set_spr_immed 0x1b1b,cccr + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xbeef,0xdead,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xbeef,0xdead,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cudiv.cgs b/sim/testsuite/sim/frv/cudiv.cgs new file mode 100644 index 00000000000..78f44ae8407 --- /dev/null +++ b/sim/testsuite/sim/frv/cudiv.cgs @@ -0,0 +1,96 @@ +# frv testcase for cudiv $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cudiv +cudiv: + set_spr_immed 0x1b1b,cccr + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc0,1 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc4,1 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc0,0 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x0000000c,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc4,0 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_limmed 0xfedc,0xba98,gr3 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc1,0 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc5,0 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc1,1 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x0000000c,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc5,1 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_limmed 0xfedc,0xba98,gr3 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc2,0 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x0000000c,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc6,1 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_limmed 0xfedc,0xba98,gr3 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc3,0 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x0000000c,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc7,1 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_limmed 0xfedc,0xba98,gr3 + + pass diff --git a/sim/testsuite/sim/frv/cxor.cgs b/sim/testsuite/sim/frv/cxor.cgs new file mode 100644 index 00000000000..54a672dfe70 --- /dev/null +++ b/sim/testsuite/sim/frv/cxor.cgs @@ -0,0 +1,180 @@ +# frv testcase for cxor $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cxor +cxor: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc0,1 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc4,1 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc0,0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc4,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc1,0 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 1 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc5,0 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc1,1 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc5,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc2,0 + test_icc 0 1 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 0 icc2 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,2 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc6,1 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc6,1 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc3,0 + test_icc 0 1 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 0 icc3 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,3 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc7,1 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc7,1 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x0000,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cxorcc.cgs b/sim/testsuite/sim/frv/cxorcc.cgs new file mode 100644 index 00000000000..86d917d288c --- /dev/null +++ b/sim/testsuite/sim/frv/cxorcc.cgs @@ -0,0 +1,180 @@ +# frv testcase for cxorcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cxorcc +cxorcc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc0,1 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc1,0 + test_icc 0 1 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 0 1 icc1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 0 icc2 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,2 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc6,1 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc6,1 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 0 icc3 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,3 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc7,1 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc7,1 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x0000,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/dcef.cgs b/sim/testsuite/sim/frv/dcef.cgs new file mode 100644 index 00000000000..0b9d0a74de9 --- /dev/null +++ b/sim/testsuite/sim/frv/dcef.cgs @@ -0,0 +1,50 @@ +# frv testcase for dcef @(GRi,GRj),a +# mach: fr400 + + .include "testutils.inc" + + start + + .global dcef +dcef: + and_spr_immed 0x7fffffff,hsr0 ; data cache only: copy-back mode + set_gr_addr doit,gr10 + set_gr_immed 0,gr11 + set_gr_immed 1,gr12 + set_gr_immed 2,gr13 + set_gr_immed 3,gr14 + + set_spr_addr ok1,lr + bra doit +ok1: test_gr_immed 1,gr11 + + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache + set_spr_addr ok2,lr + bra doit +ok2: test_gr_immed 2,gr11 ; still only added 1 + + set_gr_addr doit1,gr10 + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache + dcef @(gr10,gr0),1 ; flush data cache + set_spr_addr ok3,lr + bra doit1 +ok3: test_gr_immed 4,gr11 ; added 2 this time + + set_gr_addr doit2,gr10 + set_mem_immed 0x9600b00e,gr10 ; change to add gr11,gr14,gr11 in cache + dcef @(gr0,gr0),1 ; flush data cache + set_spr_addr ok4,lr + bra doit2 +ok4: test_gr_immed 7,gr11 ; added 3 this time + + pass + +doit: add gr11,gr12,gr11 + bralr + +doit1: add gr11,gr12,gr11 + bralr + +doit2: add gr11,gr12,gr11 + bralr + diff --git a/sim/testsuite/sim/frv/dcei.cgs b/sim/testsuite/sim/frv/dcei.cgs new file mode 100644 index 00000000000..0b45147b4cc --- /dev/null +++ b/sim/testsuite/sim/frv/dcei.cgs @@ -0,0 +1,27 @@ +# frv testcase for dcei @(GRi,GRj),a +# mach: fr400 + + .include "testutils.inc" + + start + + .global dcei +dcei: + or_spr_immed 0x08000000,hsr0 ; data cache: copy-back mode + + set_mem_immed 0xdeadbeef,sp + test_mem_immed 0xdeadbeef,sp + + flush_data_cache sp + set_mem_immed 0xbeefdead,sp + test_mem_immed 0xbeefdead,sp + + dcei @(sp,gr0),1 + test_mem_immed 0xdeadbeef,sp + + set_mem_immed 0xbeefdead,sp + test_mem_immed 0xbeefdead,sp + dcei @(gr0,gr0),1 + test_mem_immed 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/dcf.cgs b/sim/testsuite/sim/frv/dcf.cgs new file mode 100644 index 00000000000..f6e670e7b43 --- /dev/null +++ b/sim/testsuite/sim/frv/dcf.cgs @@ -0,0 +1,39 @@ +# FRV testcase for dcf @(GRi,GRj) +# mach: all + + .include "testutils.inc" + + start + + .global dcf +dcf: + and_spr_immed 0x7fffffff,hsr0 ; data cache only: copy-back mode + set_gr_addr doit,gr10 + set_gr_immed 0,gr11 + set_gr_immed 1,gr12 + set_gr_immed 2,gr13 + + set_spr_addr ok1,lr + bra doit +ok1: test_gr_immed 1,gr11 + + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache + set_spr_addr ok2,lr + bra doit +ok2: test_gr_immed 2,gr11 ; still only added 1 + + set_gr_addr doit1,gr10 + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache + dcf @(gr10,gr0) ; flush data cache + set_spr_addr ok3,lr + bra doit1 +ok3: test_gr_immed 4,gr11 ; added 2 this time + + pass + +doit: add gr11,gr12,gr11 + bralr + +doit1: add gr11,gr12,gr11 + bralr + diff --git a/sim/testsuite/sim/frv/dci.cgs b/sim/testsuite/sim/frv/dci.cgs new file mode 100644 index 00000000000..de481c363c4 --- /dev/null +++ b/sim/testsuite/sim/frv/dci.cgs @@ -0,0 +1,22 @@ +# FRV testcase for dci @(GRi,GRj) +# mach: all + + .include "testutils.inc" + + start + + .global dci +dci: + or_spr_immed 0x08000000,hsr0 ; data cache: copy-back mode + + set_mem_immed 0xdeadbeef,sp + test_mem_immed 0xdeadbeef,sp + + flush_data_cache sp + set_mem_immed 0xbeefdead,sp + test_mem_immed 0xbeefdead,sp + + dci @(sp,gr0) + test_mem_immed 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/fabsd.cgs b/sim/testsuite/sim/frv/fabsd.cgs new file mode 100644 index 00000000000..41a485e19eb --- /dev/null +++ b/sim/testsuite/sim/frv/fabsd.cgs @@ -0,0 +1,26 @@ +# frv testcase for fabsd $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fabsd +fabsd: + fabsd fr0,fr2 + test_dfr_dfr fr2,fr52 + fabsd fr8,fr2 + test_dfr_dfr fr2,fr28 + fabsd fr12,fr2 + test_dfr_dfr fr2,fr24 + fabsd fr24,fr2 + test_dfr_dfr fr2,fr24 + fabsd fr28,fr2 + test_dfr_dfr fr2,fr28 + fabsd fr52,fr2 + test_dfr_dfr fr2,fr52 + + pass diff --git a/sim/testsuite/sim/frv/fabss.cgs b/sim/testsuite/sim/frv/fabss.cgs new file mode 100644 index 00000000000..2c253462769 --- /dev/null +++ b/sim/testsuite/sim/frv/fabss.cgs @@ -0,0 +1,25 @@ +# frv testcase for fabss $FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fabss +fabss: + fabss fr0,fr1 + test_fr_fr fr1,fr52 + fabss fr8,fr1 + test_fr_fr fr1,fr28 + fabss fr12,fr1 + test_fr_fr fr1,fr24 + fabss fr24,fr1 + test_fr_fr fr1,fr24 + fabss fr28,fr1 + test_fr_fr fr1,fr28 + fabss fr52,fr1 + test_fr_fr fr1,fr52 + + pass diff --git a/sim/testsuite/sim/frv/faddd.cgs b/sim/testsuite/sim/frv/faddd.cgs new file mode 100644 index 00000000000..dbb6373bb4d --- /dev/null +++ b/sim/testsuite/sim/frv/faddd.cgs @@ -0,0 +1,93 @@ +# frv testcase for faddd $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global faddd +faddd: + faddd fr16,fr0,fr2 + test_dfr_dfr fr2,fr0 + faddd fr16,fr4,fr2 + test_dfr_dfr fr2,fr4 + faddd fr16,fr8,fr2 + test_dfr_dfr fr2,fr8 + faddd fr16,fr12,fr2 + test_dfr_dfr fr2,fr12 + faddd fr16,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + faddd fr16,fr20,fr2 + test_dfr_dfr fr2,fr26 + test_dfr_dfr fr2,fr20 + faddd fr16,fr24,fr2 + test_dfr_dfr fr2,fr24 + faddd fr16,fr28,fr2 + test_dfr_dfr fr2,fr28 + faddd fr16,fr32,fr2 + test_dfr_dfr fr2,fr32 + faddd fr16,fr36,fr2 + test_dfr_dfr fr2,fr36 + faddd fr16,fr40,fr2 + test_dfr_dfr fr2,fr40 + faddd fr16,fr44,fr2 + test_dfr_dfr fr2,fr44 + faddd fr16,fr48,fr2 + test_dfr_dfr fr2,fr48 + faddd fr16,fr52,fr2 + test_dfr_dfr fr2,fr52 + + faddd fr20,fr0,fr2 + test_dfr_dfr fr2,fr0 + faddd fr20,fr4,fr2 + test_dfr_dfr fr2,fr4 + faddd fr20,fr8,fr2 + test_dfr_dfr fr2,fr8 + faddd fr20,fr12,fr2 + test_dfr_dfr fr2,fr12 + faddd fr20,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + faddd fr20,fr20,fr2 + test_dfr_dfr fr2,fr26 + test_dfr_dfr fr2,fr20 + faddd fr20,fr24,fr2 + test_dfr_dfr fr2,fr24 + faddd fr20,fr28,fr2 + test_dfr_dfr fr2,fr28 + faddd fr20,fr32,fr2 + test_dfr_dfr fr2,fr32 + faddd fr20,fr36,fr2 + test_dfr_dfr fr2,fr36 + faddd fr20,fr40,fr2 + test_dfr_dfr fr2,fr40 + faddd fr20,fr44,fr2 + test_dfr_dfr fr2,fr44 + faddd fr20,fr48,fr2 + test_dfr_dfr fr2,fr48 + faddd fr20,fr52,fr2 + test_dfr_dfr fr2,fr52 + + faddd fr8,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + faddd fr12,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + faddd fr24,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + faddd fr28,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + faddd fr36,fr40,fr2 + test_dfr_dfr fr2,fr44 + + pass + + diff --git a/sim/testsuite/sim/frv/fadds.cgs b/sim/testsuite/sim/frv/fadds.cgs new file mode 100644 index 00000000000..ff3a5fb2201 --- /dev/null +++ b/sim/testsuite/sim/frv/fadds.cgs @@ -0,0 +1,92 @@ +# frv testcase for fadds $GRi,$GRj,$GRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fadds +fadds: + fadds fr16,fr0,fr1 + test_fr_fr fr1,fr0 + fadds fr16,fr4,fr1 + test_fr_fr fr1,fr4 + fadds fr16,fr8,fr1 + test_fr_fr fr1,fr8 + fadds fr16,fr12,fr1 + test_fr_fr fr1,fr12 + fadds fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr16,fr24,fr1 + test_fr_fr fr1,fr24 + fadds fr16,fr28,fr1 + test_fr_fr fr1,fr28 + fadds fr16,fr32,fr1 + test_fr_fr fr1,fr32 + fadds fr16,fr36,fr1 + test_fr_fr fr1,fr36 + fadds fr16,fr40,fr1 + test_fr_fr fr1,fr40 + fadds fr16,fr44,fr1 + test_fr_fr fr1,fr44 + fadds fr16,fr48,fr1 + test_fr_fr fr1,fr48 + fadds fr16,fr52,fr1 + test_fr_fr fr1,fr52 + + fadds fr20,fr0,fr1 + test_fr_fr fr1,fr0 + fadds fr20,fr4,fr1 + test_fr_fr fr1,fr4 + fadds fr20,fr8,fr1 + test_fr_fr fr1,fr8 + fadds fr20,fr12,fr1 + test_fr_fr fr1,fr12 + fadds fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr20,fr24,fr1 + test_fr_fr fr1,fr24 + fadds fr20,fr28,fr1 + test_fr_fr fr1,fr28 + fadds fr20,fr32,fr1 + test_fr_fr fr1,fr32 + fadds fr20,fr36,fr1 + test_fr_fr fr1,fr36 + fadds fr20,fr40,fr1 + test_fr_fr fr1,fr40 + fadds fr20,fr44,fr1 + test_fr_fr fr1,fr44 + fadds fr20,fr48,fr1 + test_fr_fr fr1,fr48 + fadds fr20,fr52,fr1 + test_fr_fr fr1,fr52 + + fadds fr8,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr12,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr24,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr28,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fadds fr36,fr40,fr1 + test_fr_fr fr1,fr44 + + pass + + diff --git a/sim/testsuite/sim/frv/fbeq.cgs b/sim/testsuite/sim/frv/fbeq.cgs new file mode 100644 index 00000000000..e51b2c96dcc --- /dev/null +++ b/sim/testsuite/sim/frv/fbeq.cgs @@ -0,0 +1,61 @@ +# frv testcase for fbeq $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbeq +fbeq: + set_fcc 0x0 0 + fbeq fcc0,0,bad + set_fcc 0x1 1 + fbeq fcc1,1,bad + set_fcc 0x2 2 + fbeq fcc2,2,bad + set_fcc 0x3 3 + fbeq fcc3,3,bad + set_fcc 0x4 0 + fbeq fcc0,0,bad + set_fcc 0x5 1 + fbeq fcc1,1,bad + set_fcc 0x6 2 + fbeq fcc2,2,bad + set_fcc 0x7 3 + fbeq fcc3,3,bad + set_fcc 0x8 0 + fbeq fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbeq fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbeq fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbeq fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbeq fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbeq fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbeq fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbeq fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbeqlr.cgs b/sim/testsuite/sim/frv/fbeqlr.cgs new file mode 100644 index 00000000000..af29cb909c4 --- /dev/null +++ b/sim/testsuite/sim/frv/fbeqlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for fbeqlr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbeqlr +fbeqlr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbeqlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fbeqlr fcc1,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fbeqlr fcc2,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fbeqlr fcc3,3 + + set_spr_addr bad,lr + set_fcc 0x4 0 + fbeqlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fbeqlr fcc1,1 + + set_spr_addr bad,lr + set_fcc 0x6 2 + fbeqlr fcc2,2 + + set_spr_addr bad,lr + set_fcc 0x7 3 + fbeqlr fcc3,3 + + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbeqlr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbeqlr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbeqlr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbeqlr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbeqlr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbeqlr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbeqlr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbeqlr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbge.cgs b/sim/testsuite/sim/frv/fbge.cgs new file mode 100644 index 00000000000..a20029e6613 --- /dev/null +++ b/sim/testsuite/sim/frv/fbge.cgs @@ -0,0 +1,69 @@ +# frv testcase for fbge $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbge +fbge: + set_fcc 0x0 0 + fbge fcc0,0,bad + set_fcc 0x1 1 + fbge fcc1,1,bad + set_fcc 0x2 2 + fbge fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbge fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbge fcc0,0,bad + set_fcc 0x5 1 + fbge fcc1,1,bad + set_fcc 0x6 2 + fbge fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbge fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbge fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbge fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbge fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbge fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbge fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbge fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbge fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbge fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbgelr.cgs b/sim/testsuite/sim/frv/fbgelr.cgs new file mode 100644 index 00000000000..59e941084ba --- /dev/null +++ b/sim/testsuite/sim/frv/fbgelr.cgs @@ -0,0 +1,88 @@ +# frv testcase for fbgelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbgelr +fbgelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbgelr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fbgelr fcc1,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbgelr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbgelr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbgelr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fbgelr fcc1,1 + + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbgelr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbgelr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbgelr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbgelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbgelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbgelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbgelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbgelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbgelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbgelr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbgt.cgs b/sim/testsuite/sim/frv/fbgt.cgs new file mode 100644 index 00000000000..7cc4ea7ab4b --- /dev/null +++ b/sim/testsuite/sim/frv/fbgt.cgs @@ -0,0 +1,61 @@ +# frv testcase for fbgt $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbgt +fbgt: + set_fcc 0x0 0 + fbgt fcc0,0,bad + set_fcc 0x1 1 + fbgt fcc1,1,bad + set_fcc 0x2 2 + fbgt fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbgt fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbgt fcc0,0,bad + set_fcc 0x5 1 + fbgt fcc1,1,bad + set_fcc 0x6 2 + fbgt fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbgt fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbgt fcc0,0,bad + set_fcc 0x9 1 + fbgt fcc1,1,bad + set_fcc 0xa 2 + fbgt fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbgt fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbgt fcc0,0,bad + set_fcc 0xd 1 + fbgt fcc1,1,bad + set_fcc 0xe 2 + fbgt fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbgt fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbgtlr.cgs b/sim/testsuite/sim/frv/fbgtlr.cgs new file mode 100644 index 00000000000..7e4a7a51275 --- /dev/null +++ b/sim/testsuite/sim/frv/fbgtlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for fbgtlr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbgtlr +fbgtlr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbgtlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fbgtlr fcc1,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbgtlr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbgtlr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbgtlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fbgtlr fcc1,1 + + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbgtlr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbgtlr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbgtlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fbgtlr fcc1,1 + + set_spr_addr okb,lr + set_fcc 0xa 2 + fbgtlr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbgtlr fcc3,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fbgtlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0xd 1 + fbgtlr fcc1,1 + + set_spr_addr okf,lr + set_fcc 0xe 2 + fbgtlr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbgtlr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fble.cgs b/sim/testsuite/sim/frv/fble.cgs new file mode 100644 index 00000000000..e52936a776b --- /dev/null +++ b/sim/testsuite/sim/frv/fble.cgs @@ -0,0 +1,69 @@ +# frv testcase for fble $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fble +fble: + set_fcc 0x0 0 + fble fcc0,0,bad + set_fcc 0x1 1 + fble fcc1,1,bad + set_fcc 0x2 2 + fble fcc2,2,bad + set_fcc 0x3 3 + fble fcc3,3,bad + set_fcc 0x4 0 + fble fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fble fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fble fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fble fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fble fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fble fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fble fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fble fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fble fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fble fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fble fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fble fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fblelr.cgs b/sim/testsuite/sim/frv/fblelr.cgs new file mode 100644 index 00000000000..92a47bc970f --- /dev/null +++ b/sim/testsuite/sim/frv/fblelr.cgs @@ -0,0 +1,89 @@ +# frv testcase for fblelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fblelr +fblelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fblelr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fblelr fcc1,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fblelr fcc2,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fblelr fcc3,3 + + set_spr_addr ok5,lr + set_fcc 0x4 0 + fblelr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fblelr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fblelr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fblelr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fblelr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fblelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fblelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fblelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fblelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fblelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fblelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fblelr fcc3,3 + fail +okg: + pass +bad: + fail + diff --git a/sim/testsuite/sim/frv/fblg.cgs b/sim/testsuite/sim/frv/fblg.cgs new file mode 100644 index 00000000000..a16f80289f5 --- /dev/null +++ b/sim/testsuite/sim/frv/fblg.cgs @@ -0,0 +1,69 @@ +# frv testcase for fblg $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fblg +fblg: + set_fcc 0x0 0 + fblg fcc0,0,bad + set_fcc 0x1 1 + fblg fcc1,1,bad + set_fcc 0x2 2 + fblg fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fblg fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fblg fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fblg fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fblg fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fblg fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fblg fcc0,0,bad + set_fcc 0x9 1 + fblg fcc1,1,bad + set_fcc 0xa 2 + fblg fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fblg fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fblg fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fblg fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fblg fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fblg fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fblglr.cgs b/sim/testsuite/sim/frv/fblglr.cgs new file mode 100644 index 00000000000..e7a32b04ce7 --- /dev/null +++ b/sim/testsuite/sim/frv/fblglr.cgs @@ -0,0 +1,88 @@ +# frv testcase for fblglr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fblglr +fblglr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fblglr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fblglr fcc1,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fblglr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fblglr fcc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fblglr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fblglr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fblglr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fblglr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fblglr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fblglr fcc1,1 + + set_spr_addr okb,lr + set_fcc 0xa 2 + fblglr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fblglr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fblglr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fblglr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fblglr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fblglr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fblt.cgs b/sim/testsuite/sim/frv/fblt.cgs new file mode 100644 index 00000000000..ef7e5c78c45 --- /dev/null +++ b/sim/testsuite/sim/frv/fblt.cgs @@ -0,0 +1,61 @@ +# frv testcase for fblt $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fblt +fblt: + set_fcc 0x0 0 + fblt fcc0,0,bad + set_fcc 0x1 1 + fblt fcc1,1,bad + set_fcc 0x2 2 + fblt fcc2,2,bad + set_fcc 0x3 3 + fblt fcc3,3,bad + set_fcc 0x4 0 + fblt fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fblt fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fblt fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fblt fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fblt fcc0,0,bad + set_fcc 0x9 1 + fblt fcc1,1,bad + set_fcc 0xa 2 + fblt fcc2,2,bad + set_fcc 0xb 3 + fblt fcc3,3,bad + set_fcc 0xc 0 + fblt fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fblt fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fblt fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fblt fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbltlr.cgs b/sim/testsuite/sim/frv/fbltlr.cgs new file mode 100644 index 00000000000..0a2c43696d3 --- /dev/null +++ b/sim/testsuite/sim/frv/fbltlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for fbltlr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbltlr +fbltlr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbltlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fbltlr fcc1,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fbltlr fcc2,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fbltlr fcc3,3 + + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbltlr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbltlr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbltlr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbltlr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbltlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fbltlr fcc1,1 + + set_spr_addr bad,lr + set_fcc 0xa 2 + fbltlr fcc2,2 + + set_spr_addr bad,lr + set_fcc 0xb 3 + fbltlr fcc3,3 + + set_spr_addr okd,lr + set_fcc 0xc 0 + fbltlr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbltlr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbltlr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbltlr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbne.cgs b/sim/testsuite/sim/frv/fbne.cgs new file mode 100644 index 00000000000..f376eeaeac0 --- /dev/null +++ b/sim/testsuite/sim/frv/fbne.cgs @@ -0,0 +1,73 @@ +# frv testcase for fbne $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbne +fbne: + set_fcc 0x0 0 + fbne fcc0,0,bad + set_fcc 0x1 1 + fbne fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbne fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbne fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbne fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fbne fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbne fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbne fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbne fcc0,0,bad + set_fcc 0x9 1 + fbne fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbne fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbne fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbne fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbne fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbne fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbne fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbnelr.cgs b/sim/testsuite/sim/frv/fbnelr.cgs new file mode 100644 index 00000000000..334d185a4d4 --- /dev/null +++ b/sim/testsuite/sim/frv/fbnelr.cgs @@ -0,0 +1,90 @@ +# frv testcase for fbnelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbnelr +fbnelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbnelr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbnelr fcc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbnelr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbnelr fcc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbnelr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbnelr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbnelr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbnelr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbnelr fcc0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fbnelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbnelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbnelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbnelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbnelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbnelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbnelr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbno.cgs b/sim/testsuite/sim/frv/fbno.cgs new file mode 100644 index 00000000000..a3dc5877f47 --- /dev/null +++ b/sim/testsuite/sim/frv/fbno.cgs @@ -0,0 +1,45 @@ +# frv testcase for fbno $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbno +fbno: + set_fcc 0x0 0 + fbno + set_fcc 0x1 1 + fbno + set_fcc 0x2 2 + fbno + set_fcc 0x3 3 + fbno + set_fcc 0x4 0 + fbno + set_fcc 0x5 1 + fbno + set_fcc 0x6 2 + fbno + set_fcc 0x7 3 + fbno + set_fcc 0x8 0 + fbno + set_fcc 0x9 1 + fbno + set_fcc 0xa 2 + fbno + set_fcc 0xb 3 + fbno + set_fcc 0xc 0 + fbno + set_fcc 0xd 1 + fbno + set_fcc 0xe 2 + fbno + set_fcc 0xf 3 + fbno + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbnolr.cgs b/sim/testsuite/sim/frv/fbnolr.cgs new file mode 100644 index 00000000000..be5a0ef9a6c --- /dev/null +++ b/sim/testsuite/sim/frv/fbnolr.cgs @@ -0,0 +1,47 @@ +# frv testcase for fbnolr +# mach: all + + .include "testutils.inc" + + start + + .global fbnolr +fbnolr: + set_spr_addr bad,lr + + set_fcc 0x0 0 + fbnolr + set_fcc 0x1 1 + fbnolr + set_fcc 0x2 2 + fbnolr + set_fcc 0x3 3 + fbnolr + set_fcc 0x4 0 + fbnolr + set_fcc 0x5 1 + fbnolr + set_fcc 0x6 2 + fbnolr + set_fcc 0x7 3 + fbnolr + set_fcc 0x8 0 + fbnolr + set_fcc 0x9 1 + fbnolr + set_fcc 0xa 2 + fbnolr + set_fcc 0xb 3 + fbnolr + set_fcc 0xc 0 + fbnolr + set_fcc 0xd 1 + fbnolr + set_fcc 0xe 2 + fbnolr + set_fcc 0xf 3 + fbnolr + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbo.cgs b/sim/testsuite/sim/frv/fbo.cgs new file mode 100644 index 00000000000..42062c93f0f --- /dev/null +++ b/sim/testsuite/sim/frv/fbo.cgs @@ -0,0 +1,73 @@ +# frv testcase for fbo $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbo +fbo: + set_fcc 0x0 0 + fbo fcc0,0,bad + set_fcc 0x1 1 + fbo fcc1,1,bad + set_fcc 0x2 2 + fbo fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbo fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbo fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fbo fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbo fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbo fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbo fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbo fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbo fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbo fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbo fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbo fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbo fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbo fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbolr.cgs b/sim/testsuite/sim/frv/fbolr.cgs new file mode 100644 index 00000000000..2f9bfb34bf3 --- /dev/null +++ b/sim/testsuite/sim/frv/fbolr.cgs @@ -0,0 +1,90 @@ +# frv testcase for fbolr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbolr +fbolr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbolr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fbolr fcc1,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbolr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbolr fcc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbolr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbolr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbolr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbolr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbolr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbolr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbolr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbolr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbolr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbolr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbolr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbolr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbra.cgs b/sim/testsuite/sim/frv/fbra.cgs new file mode 100644 index 00000000000..2f293081ff0 --- /dev/null +++ b/sim/testsuite/sim/frv/fbra.cgs @@ -0,0 +1,75 @@ +# frv testcase for fbra $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbra +fbra: + set_fcc 0x0 0 + fbra ok1 + fail +ok1: + set_fcc 0x1 1 + fbra ok2 + fail +ok2: + set_fcc 0x2 2 + fbra ok3 + fail +ok3: + set_fcc 0x3 3 + fbra ok4 + fail +ok4: + set_fcc 0x4 0 + fbra ok5 + fail +ok5: + set_fcc 0x5 1 + fbra ok6 + fail +ok6: + set_fcc 0x6 2 + fbra ok7 + fail +ok7: + set_fcc 0x7 3 + fbra ok8 + fail +ok8: + set_fcc 0x8 0 + fbra ok9 + fail +ok9: + set_fcc 0x9 1 + fbra oka + fail +oka: + set_fcc 0xa 2 + fbra okb + fail +okb: + set_fcc 0xb 3 + fbra okc + fail +okc: + set_fcc 0xc 0 + fbra okd + fail +okd: + set_fcc 0xd 1 + fbra oke + fail +oke: + set_fcc 0xe 2 + fbra okf + fail +okf: + set_fcc 0xf 3 + fbra okg + fail +okg: + + pass diff --git a/sim/testsuite/sim/frv/fbralr.cgs b/sim/testsuite/sim/frv/fbralr.cgs new file mode 100644 index 00000000000..d57afc9e68a --- /dev/null +++ b/sim/testsuite/sim/frv/fbralr.cgs @@ -0,0 +1,91 @@ +# frv testcase for fbralr +# mach: all + + .include "testutils.inc" + + start + + .global fbralr +fbralr: + set_spr_addr ok1,lr + set_fcc 0x0 0 + fbralr + fail +ok1: + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbralr + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbralr + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbralr + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbralr + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbralr + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbralr + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbralr + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbralr + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbralr + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbralr + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbralr + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbralr + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbralr + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbralr + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbralr + fail +okg: + + pass diff --git a/sim/testsuite/sim/frv/fbu.cgs b/sim/testsuite/sim/frv/fbu.cgs new file mode 100644 index 00000000000..f3970012a17 --- /dev/null +++ b/sim/testsuite/sim/frv/fbu.cgs @@ -0,0 +1,61 @@ +# frv testcase for fbu $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbu +fbu: + set_fcc 0x0 0 + fbu fcc0,0,bad + set_fcc 0x1 1 + fbu fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbu fcc2,2,bad + set_fcc 0x3 3 + fbu fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbu fcc0,0,bad + set_fcc 0x5 1 + fbu fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbu fcc2,2,bad + set_fcc 0x7 3 + fbu fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbu fcc0,0,bad + set_fcc 0x9 1 + fbu fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbu fcc2,2,bad + set_fcc 0xb 3 + fbu fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbu fcc0,0,bad + set_fcc 0xd 1 + fbu fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbu fcc2,2,bad + set_fcc 0xf 3 + fbu fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbue.cgs b/sim/testsuite/sim/frv/fbue.cgs new file mode 100644 index 00000000000..dd1d636a18e --- /dev/null +++ b/sim/testsuite/sim/frv/fbue.cgs @@ -0,0 +1,69 @@ +# frv testcase for fbue $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbue +fbue: + set_fcc 0x0 0 + fbue fcc0,0,bad + set_fcc 0x1 1 + fbue fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbue fcc2,2,bad + set_fcc 0x3 3 + fbue fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbue fcc0,0,bad + set_fcc 0x5 1 + fbue fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbue fcc2,2,bad + set_fcc 0x7 3 + fbue fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbue fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbue fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbue fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbue fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbue fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbue fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbue fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbue fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbuelr.cgs b/sim/testsuite/sim/frv/fbuelr.cgs new file mode 100644 index 00000000000..62ca6aa7063 --- /dev/null +++ b/sim/testsuite/sim/frv/fbuelr.cgs @@ -0,0 +1,88 @@ +# frv testcase for fbuelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbuelr +fbuelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbuelr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbuelr fcc1,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fbuelr fcc2,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbuelr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbuelr fcc0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbuelr fcc1,1 + fail +ok6: + set_spr_addr bad,lr + set_fcc 0x6 2 + fbuelr fcc2,2 + + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbuelr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbuelr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbuelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbuelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbuelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbuelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbuelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbuelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbuelr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbug.cgs b/sim/testsuite/sim/frv/fbug.cgs new file mode 100644 index 00000000000..3a5ee01aa3f --- /dev/null +++ b/sim/testsuite/sim/frv/fbug.cgs @@ -0,0 +1,69 @@ +# frv testcase for fbug $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbug +fbug: + set_fcc 0x0 0 + fbug fcc0,0,bad + set_fcc 0x1 1 + fbug fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbug fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbug fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbug fcc0,0,bad + set_fcc 0x5 1 + fbug fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbug fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbug fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbug fcc0,0,bad + set_fcc 0x9 1 + fbug fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbug fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbug fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbug fcc0,0,bad + set_fcc 0xd 1 + fbug fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbug fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbug fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbuge.cgs b/sim/testsuite/sim/frv/fbuge.cgs new file mode 100644 index 00000000000..edbf7f83461 --- /dev/null +++ b/sim/testsuite/sim/frv/fbuge.cgs @@ -0,0 +1,73 @@ +# frv testcase for fbuge $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbuge +fbuge: + set_fcc 0x0 0 + fbuge fcc0,0,bad + set_fcc 0x1 1 + fbuge fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbuge fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbuge fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbuge fcc0,0,bad + set_fcc 0x5 1 + fbuge fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbuge fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbuge fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbuge fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbuge fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbuge fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbuge fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbuge fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbuge fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbuge fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbuge fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbugelr.cgs b/sim/testsuite/sim/frv/fbugelr.cgs new file mode 100644 index 00000000000..b1799c56918 --- /dev/null +++ b/sim/testsuite/sim/frv/fbugelr.cgs @@ -0,0 +1,90 @@ +# frv testcase for fbugelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbugelr +fbugelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbugelr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbugelr fcc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbugelr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbugelr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbugelr fcc0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbugelr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbugelr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbugelr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbugelr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbugelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbugelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbugelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbugelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbugelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbugelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbugelr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbuglr.cgs b/sim/testsuite/sim/frv/fbuglr.cgs new file mode 100644 index 00000000000..d660a95d810 --- /dev/null +++ b/sim/testsuite/sim/frv/fbuglr.cgs @@ -0,0 +1,88 @@ +# frv testcase for fbuglr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbuglr +fbuglr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbuglr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbuglr fcc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbuglr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbuglr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbuglr fcc0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbuglr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbuglr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbuglr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbuglr fcc0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fbuglr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbuglr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbuglr fcc3,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fbuglr fcc0,0 + + set_spr_addr oke,lr + set_fcc 0xd 1 + fbuglr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbuglr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbuglr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbul.cgs b/sim/testsuite/sim/frv/fbul.cgs new file mode 100644 index 00000000000..47b689d6ea5 --- /dev/null +++ b/sim/testsuite/sim/frv/fbul.cgs @@ -0,0 +1,69 @@ +# frv testcase for fbul $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbul +fbul: + set_fcc 0x0 0 + fbul fcc0,0,bad + set_fcc 0x1 1 + fbul fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbul fcc2,2,bad + set_fcc 0x3 3 + fbul fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbul fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fbul fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbul fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbul fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbul fcc0,0,bad + set_fcc 0x9 1 + fbul fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbul fcc2,2,bad + set_fcc 0xb 3 + fbul fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbul fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbul fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbul fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbul fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbule.cgs b/sim/testsuite/sim/frv/fbule.cgs new file mode 100644 index 00000000000..ad5f4e9b173 --- /dev/null +++ b/sim/testsuite/sim/frv/fbule.cgs @@ -0,0 +1,73 @@ +# frv testcase for fbule $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbule +fbule: + set_fcc 0x0 0 + fbule fcc0,0,bad + set_fcc 0x1 1 + fbule fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbule fcc2,2,bad + set_fcc 0x3 3 + fbule fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbule fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fbule fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbule fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbule fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbule fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbule fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbule fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbule fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbule fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbule fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbule fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbule fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbulelr.cgs b/sim/testsuite/sim/frv/fbulelr.cgs new file mode 100644 index 00000000000..f34d58cfc6e --- /dev/null +++ b/sim/testsuite/sim/frv/fbulelr.cgs @@ -0,0 +1,90 @@ +# frv testcase for fbulelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbulelr +fbulelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbulelr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbulelr fcc1,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fbulelr fcc2,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbulelr fcc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbulelr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbulelr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbulelr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbulelr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbulelr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbulelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbulelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbulelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbulelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbulelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbulelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbulelr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbullr.cgs b/sim/testsuite/sim/frv/fbullr.cgs new file mode 100644 index 00000000000..2d5b251ce00 --- /dev/null +++ b/sim/testsuite/sim/frv/fbullr.cgs @@ -0,0 +1,88 @@ +# frv testcase for fbullr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbullr +fbullr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbullr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbullr fcc1,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fbullr fcc2,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbullr fcc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbullr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbullr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbullr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbullr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbullr fcc0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fbullr fcc1,1 + fail +oka: + set_spr_addr bad,lr + set_fcc 0xa 2 + fbullr fcc2,2 + + set_spr_addr okc,lr + set_fcc 0xb 3 + fbullr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbullr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbullr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbullr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbullr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbulr.cgs b/sim/testsuite/sim/frv/fbulr.cgs new file mode 100644 index 00000000000..d8594bc3b91 --- /dev/null +++ b/sim/testsuite/sim/frv/fbulr.cgs @@ -0,0 +1,84 @@ +# frv testcase for fbulr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbulr +fbulr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbulr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbulr fcc1,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fbulr fcc2,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbulr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbulr fcc0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbulr fcc1,1 + fail +ok6: + set_spr_addr bad,lr + set_fcc 0x6 2 + fbulr fcc2,2 + + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbulr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbulr fcc0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fbulr fcc1,1 + fail +oka: + set_spr_addr bad,lr + set_fcc 0xa 2 + fbulr fcc2,2 + + set_spr_addr okc,lr + set_fcc 0xb 3 + fbulr fcc3,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fbulr fcc0,0 + + set_spr_addr oke,lr + set_fcc 0xd 1 + fbulr fcc1,1 + fail +oke: + set_spr_addr bad,lr + set_fcc 0xe 2 + fbulr fcc2,2 + + set_spr_addr okg,lr + set_fcc 0xf 3 + fbulr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbeqlr.cgs b/sim/testsuite/sim/frv/fcbeqlr.cgs new file mode 100644 index 00000000000..b87e77f34a4 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbeqlr.cgs @@ -0,0 +1,262 @@ +# frv testcase for fcbeqlr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbeqlr +fcbeqlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbeqlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbeqlr fcc1,0,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbeqlr fcc2,0,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fcbeqlr fcc3,0,3 + + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbeqlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbeqlr fcc1,0,1 + + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbeqlr fcc2,0,2 + + set_spr_addr bad,lr + set_fcc 0x7 3 + fcbeqlr fcc3,0,3 + + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbeqlr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbeqlr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbeqlr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbeqlr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbeqlr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbeqlr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbeqlr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbeqlr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbeqlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbeqlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbeqlr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x3 3 + fcbeqlr fcc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbeqlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbeqlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbeqlr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x7 3 + fcbeqlr fcc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbeqlr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbeqlr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbeqlr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbeqlr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbeqlr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbeqlr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbeqlr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbeqlr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbeqlr fcc0,1,0 + set_fcc 0x1 1 + fcbeqlr fcc1,1,1 + set_fcc 0x2 2 + fcbeqlr fcc2,1,2 + set_fcc 0x3 3 + fcbeqlr fcc3,1,3 + set_fcc 0x4 0 + fcbeqlr fcc0,1,0 + set_fcc 0x5 1 + fcbeqlr fcc1,1,1 + set_fcc 0x6 2 + fcbeqlr fcc2,1,2 + set_fcc 0x7 3 + fcbeqlr fcc3,1,3 + set_fcc 0x8 0 + fcbeqlr fcc0,1,0 + set_fcc 0x9 1 + fcbeqlr fcc1,1,1 + set_fcc 0xa 2 + fcbeqlr fcc2,1,2 + set_fcc 0xb 3 + fcbeqlr fcc3,1,3 + set_fcc 0xc 0 + fcbeqlr fcc0,1,0 + set_fcc 0xd 1 + fcbeqlr fcc1,1,1 + set_fcc 0xe 2 + fcbeqlr fcc2,1,2 + set_fcc 0xf 3 + fcbeqlr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbeqlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbeqlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbeqlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbeqlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbeqlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbeqlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbeqlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbeqlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbeqlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbeqlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbeqlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbeqlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbeqlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbeqlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbeqlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbeqlr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbgelr.cgs b/sim/testsuite/sim/frv/fcbgelr.cgs new file mode 100644 index 00000000000..cc1b9d7c78c --- /dev/null +++ b/sim/testsuite/sim/frv/fcbgelr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcbgelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbgelr +fcbgelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbgelr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbgelr fcc1,0,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbgelr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbgelr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbgelr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbgelr fcc1,0,1 + + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbgelr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbgelr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbgelr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbgelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbgelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbgelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbgelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbgelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbgelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbgelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbgelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbgelr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbgelr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbgelr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbgelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbgelr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbgelr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbgelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbgelr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbgelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbgelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbgelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbgelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbgelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbgelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbgelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbgelr fcc0,1,0 + set_fcc 0x1 1 + fcbgelr fcc1,1,1 + set_fcc 0x2 2 + fcbgelr fcc2,1,2 + set_fcc 0x3 3 + fcbgelr fcc3,1,3 + set_fcc 0x4 0 + fcbgelr fcc0,1,0 + set_fcc 0x5 1 + fcbgelr fcc1,1,1 + set_fcc 0x6 2 + fcbgelr fcc2,1,2 + set_fcc 0x7 3 + fcbgelr fcc3,1,3 + set_fcc 0x8 0 + fcbgelr fcc0,1,0 + set_fcc 0x9 1 + fcbgelr fcc1,1,1 + set_fcc 0xa 2 + fcbgelr fcc2,1,2 + set_fcc 0xb 3 + fcbgelr fcc3,1,3 + set_fcc 0xc 0 + fcbgelr fcc0,1,0 + set_fcc 0xd 1 + fcbgelr fcc1,1,1 + set_fcc 0xe 2 + fcbgelr fcc2,1,2 + set_fcc 0xf 3 + fcbgelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbgelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbgelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbgelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbgelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbgelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbgelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbgelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbgelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbgelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbgelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbgelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbgelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbgelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbgelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbgelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbgelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbgtlr.cgs b/sim/testsuite/sim/frv/fcbgtlr.cgs new file mode 100644 index 00000000000..76204e235ab --- /dev/null +++ b/sim/testsuite/sim/frv/fcbgtlr.cgs @@ -0,0 +1,262 @@ +# frv testcase for fcbgtlr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbgtlr +fcbgtlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbgtlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbgtlr fcc1,0,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbgtlr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbgtlr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbgtlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbgtlr fcc1,0,1 + + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbgtlr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbgtlr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbgtlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fcbgtlr fcc1,0,1 + + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbgtlr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbgtlr fcc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbgtlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0xd 1 + fcbgtlr fcc1,0,1 + + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbgtlr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbgtlr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbgtlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbgtlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbgtlr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbgtlr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbgtlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbgtlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbgtlr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbgtlr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbgtlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x9 1 + fcbgtlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbgtlr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbgtlr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbgtlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xd 1 + fcbgtlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbgtlr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbgtlr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbgtlr fcc0,1,0 + set_fcc 0x1 1 + fcbgtlr fcc1,1,1 + set_fcc 0x2 2 + fcbgtlr fcc2,1,2 + set_fcc 0x3 3 + fcbgtlr fcc3,1,3 + set_fcc 0x4 0 + fcbgtlr fcc0,1,0 + set_fcc 0x5 1 + fcbgtlr fcc1,1,1 + set_fcc 0x6 2 + fcbgtlr fcc2,1,2 + set_fcc 0x7 3 + fcbgtlr fcc3,1,3 + set_fcc 0x8 0 + fcbgtlr fcc0,1,0 + set_fcc 0x9 1 + fcbgtlr fcc1,1,1 + set_fcc 0xa 2 + fcbgtlr fcc2,1,2 + set_fcc 0xb 3 + fcbgtlr fcc3,1,3 + set_fcc 0xc 0 + fcbgtlr fcc0,1,0 + set_fcc 0xd 1 + fcbgtlr fcc1,1,1 + set_fcc 0xe 2 + fcbgtlr fcc2,1,2 + set_fcc 0xf 3 + fcbgtlr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbgtlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbgtlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbgtlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbgtlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbgtlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbgtlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbgtlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbgtlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbgtlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbgtlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbgtlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbgtlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbgtlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbgtlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbgtlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbgtlr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcblelr.cgs b/sim/testsuite/sim/frv/fcblelr.cgs new file mode 100644 index 00000000000..b9850d6863d --- /dev/null +++ b/sim/testsuite/sim/frv/fcblelr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcblelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcblelr +fcblelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcblelr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcblelr fcc1,0,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fcblelr fcc2,0,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fcblelr fcc3,0,3 + + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcblelr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcblelr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcblelr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcblelr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcblelr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcblelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcblelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcblelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcblelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcblelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcblelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcblelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcblelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcblelr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcblelr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x3 3 + fcblelr fcc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcblelr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcblelr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcblelr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcblelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcblelr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcblelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcblelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcblelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcblelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcblelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcblelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcblelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcblelr fcc0,1,0 + set_fcc 0x1 1 + fcblelr fcc1,1,1 + set_fcc 0x2 2 + fcblelr fcc2,1,2 + set_fcc 0x3 3 + fcblelr fcc3,1,3 + set_fcc 0x4 0 + fcblelr fcc0,1,0 + set_fcc 0x5 1 + fcblelr fcc1,1,1 + set_fcc 0x6 2 + fcblelr fcc2,1,2 + set_fcc 0x7 3 + fcblelr fcc3,1,3 + set_fcc 0x8 0 + fcblelr fcc0,1,0 + set_fcc 0x9 1 + fcblelr fcc1,1,1 + set_fcc 0xa 2 + fcblelr fcc2,1,2 + set_fcc 0xb 3 + fcblelr fcc3,1,3 + set_fcc 0xc 0 + fcblelr fcc0,1,0 + set_fcc 0xd 1 + fcblelr fcc1,1,1 + set_fcc 0xe 2 + fcblelr fcc2,1,2 + set_fcc 0xf 3 + fcblelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcblelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcblelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcblelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcblelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcblelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcblelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcblelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcblelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcblelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcblelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcblelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcblelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcblelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcblelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcblelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcblelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcblglr.cgs b/sim/testsuite/sim/frv/fcblglr.cgs new file mode 100644 index 00000000000..e875d40fb1d --- /dev/null +++ b/sim/testsuite/sim/frv/fcblglr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcblglr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcblglr +fcblglr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcblglr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcblglr fcc1,0,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcblglr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcblglr fcc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcblglr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcblglr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcblglr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcblglr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcblglr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fcblglr fcc1,0,1 + + set_spr_addr okb,lr + set_fcc 0xa 2 + fcblglr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcblglr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcblglr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcblglr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcblglr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcblglr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcblglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcblglr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcblglr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcblglr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcblglr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcblglr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcblglr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcblglr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcblglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x9 1 + fcblglr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcblglr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcblglr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcblglr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcblglr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcblglr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcblglr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcblglr fcc0,1,0 + set_fcc 0x1 1 + fcblglr fcc1,1,1 + set_fcc 0x2 2 + fcblglr fcc2,1,2 + set_fcc 0x3 3 + fcblglr fcc3,1,3 + set_fcc 0x4 0 + fcblglr fcc0,1,0 + set_fcc 0x5 1 + fcblglr fcc1,1,1 + set_fcc 0x6 2 + fcblglr fcc2,1,2 + set_fcc 0x7 3 + fcblglr fcc3,1,3 + set_fcc 0x8 0 + fcblglr fcc0,1,0 + set_fcc 0x9 1 + fcblglr fcc1,1,1 + set_fcc 0xa 2 + fcblglr fcc2,1,2 + set_fcc 0xb 3 + fcblglr fcc3,1,3 + set_fcc 0xc 0 + fcblglr fcc0,1,0 + set_fcc 0xd 1 + fcblglr fcc1,1,1 + set_fcc 0xe 2 + fcblglr fcc2,1,2 + set_fcc 0xf 3 + fcblglr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcblglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcblglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcblglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcblglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcblglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcblglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcblglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcblglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcblglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcblglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcblglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcblglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcblglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcblglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcblglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcblglr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbltlr.cgs b/sim/testsuite/sim/frv/fcbltlr.cgs new file mode 100644 index 00000000000..d15dd3083c3 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbltlr.cgs @@ -0,0 +1,262 @@ +# frv testcase for fcbltlr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbltlr +fcbltlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbltlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbltlr fcc1,0,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbltlr fcc2,0,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fcbltlr fcc3,0,3 + + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbltlr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbltlr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbltlr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbltlr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbltlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fcbltlr fcc1,0,1 + + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbltlr fcc2,0,2 + + set_spr_addr bad,lr + set_fcc 0xb 3 + fcbltlr fcc3,0,3 + + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbltlr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbltlr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbltlr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbltlr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbltlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbltlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbltlr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x3 3 + fcbltlr fcc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbltlr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbltlr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbltlr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbltlr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbltlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x9 1 + fcbltlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbltlr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xb 3 + fcbltlr fcc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbltlr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbltlr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbltlr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbltlr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbltlr fcc0,1,0 + set_fcc 0x1 1 + fcbltlr fcc1,1,1 + set_fcc 0x2 2 + fcbltlr fcc2,1,2 + set_fcc 0x3 3 + fcbltlr fcc3,1,3 + set_fcc 0x4 0 + fcbltlr fcc0,1,0 + set_fcc 0x5 1 + fcbltlr fcc1,1,1 + set_fcc 0x6 2 + fcbltlr fcc2,1,2 + set_fcc 0x7 3 + fcbltlr fcc3,1,3 + set_fcc 0x8 0 + fcbltlr fcc0,1,0 + set_fcc 0x9 1 + fcbltlr fcc1,1,1 + set_fcc 0xa 2 + fcbltlr fcc2,1,2 + set_fcc 0xb 3 + fcbltlr fcc3,1,3 + set_fcc 0xc 0 + fcbltlr fcc0,1,0 + set_fcc 0xd 1 + fcbltlr fcc1,1,1 + set_fcc 0xe 2 + fcbltlr fcc2,1,2 + set_fcc 0xf 3 + fcbltlr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbltlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbltlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbltlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbltlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbltlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbltlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbltlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbltlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbltlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbltlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbltlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbltlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbltlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbltlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbltlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbltlr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbnelr.cgs b/sim/testsuite/sim/frv/fcbnelr.cgs new file mode 100644 index 00000000000..cb0aa26a74b --- /dev/null +++ b/sim/testsuite/sim/frv/fcbnelr.cgs @@ -0,0 +1,274 @@ +# frv testcase for fcbnelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbnelr +fcbnelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbnelr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbnelr fcc1,0,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbnelr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbnelr fcc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbnelr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbnelr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbnelr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbnelr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbnelr fcc0,0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbnelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbnelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbnelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbnelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbnelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbnelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbnelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbnelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbnelr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbnelr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbnelr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbnelr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbnelr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbnelr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbnelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbnelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbnelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbnelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbnelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbnelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbnelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbnelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbnelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbnelr fcc0,1,0 + set_fcc 0x1 1 + fcbnelr fcc1,1,1 + set_fcc 0x2 2 + fcbnelr fcc2,1,2 + set_fcc 0x3 3 + fcbnelr fcc3,1,3 + set_fcc 0x4 0 + fcbnelr fcc0,1,0 + set_fcc 0x5 1 + fcbnelr fcc1,1,1 + set_fcc 0x6 2 + fcbnelr fcc2,1,2 + set_fcc 0x7 3 + fcbnelr fcc3,1,3 + set_fcc 0x8 0 + fcbnelr fcc0,1,0 + set_fcc 0x9 1 + fcbnelr fcc1,1,1 + set_fcc 0xa 2 + fcbnelr fcc2,1,2 + set_fcc 0xb 3 + fcbnelr fcc3,1,3 + set_fcc 0xc 0 + fcbnelr fcc0,1,0 + set_fcc 0xd 1 + fcbnelr fcc1,1,1 + set_fcc 0xe 2 + fcbnelr fcc2,1,2 + set_fcc 0xf 3 + fcbnelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbnelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbnelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbnelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbnelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbnelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbnelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbnelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbnelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbnelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbnelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbnelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbnelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbnelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbnelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbnelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbnelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbnolr.cgs b/sim/testsuite/sim/frv/fcbnolr.cgs new file mode 100644 index 00000000000..3c1b73a64e6 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbnolr.cgs @@ -0,0 +1,185 @@ +# frv testcase for fcbnolr +# mach: all + + .include "testutils.inc" + + start + + .global fcbnolr +fcbnolr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + + set_fcc 0x0 0 + fcbnolr + set_fcc 0x1 1 + fcbnolr + set_fcc 0x2 2 + fcbnolr + set_fcc 0x3 3 + fcbnolr + set_fcc 0x4 0 + fcbnolr + set_fcc 0x5 1 + fcbnolr + set_fcc 0x6 2 + fcbnolr + set_fcc 0x7 3 + fcbnolr + set_fcc 0x8 0 + fcbnolr + set_fcc 0x9 1 + fcbnolr + set_fcc 0xa 2 + fcbnolr + set_fcc 0xb 3 + fcbnolr + set_fcc 0xc 0 + fcbnolr + set_fcc 0xd 1 + fcbnolr + set_fcc 0xe 2 + fcbnolr + set_fcc 0xf 3 + fcbnolr + + ; ccond is true + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbnolr + + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbnolr + set_fcc 0x1 1 + fcbnolr + set_fcc 0x2 2 + fcbnolr + set_fcc 0x3 3 + fcbnolr + set_fcc 0x4 0 + fcbnolr + set_fcc 0x5 1 + fcbnolr + set_fcc 0x6 2 + fcbnolr + set_fcc 0x7 3 + fcbnolr + set_fcc 0x8 0 + fcbnolr + set_fcc 0x9 1 + fcbnolr + set_fcc 0xa 2 + fcbnolr + set_fcc 0xb 3 + fcbnolr + set_fcc 0xc 0 + fcbnolr + set_fcc 0xd 1 + fcbnolr + set_fcc 0xe 2 + fcbnolr + set_fcc 0xf 3 + fcbnolr + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbnolr + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbolr.cgs b/sim/testsuite/sim/frv/fcbolr.cgs new file mode 100644 index 00000000000..31909f1bb2a --- /dev/null +++ b/sim/testsuite/sim/frv/fcbolr.cgs @@ -0,0 +1,274 @@ +# frv testcase for fcbolr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbolr +fcbolr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbolr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbolr fcc1,0,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbolr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbolr fcc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbolr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbolr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbolr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbolr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbolr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbolr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbolr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbolr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbolr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbolr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbolr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbolr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbolr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbolr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbolr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbolr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbolr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbolr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbolr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbolr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbolr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbolr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbolr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbolr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbolr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbolr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbolr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbolr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbolr fcc0,1,0 + set_fcc 0x1 1 + fcbolr fcc1,1,1 + set_fcc 0x2 2 + fcbolr fcc2,1,2 + set_fcc 0x3 3 + fcbolr fcc3,1,3 + set_fcc 0x4 0 + fcbolr fcc0,1,0 + set_fcc 0x5 1 + fcbolr fcc1,1,1 + set_fcc 0x6 2 + fcbolr fcc2,1,2 + set_fcc 0x7 3 + fcbolr fcc3,1,3 + set_fcc 0x8 0 + fcbolr fcc0,1,0 + set_fcc 0x9 1 + fcbolr fcc1,1,1 + set_fcc 0xa 2 + fcbolr fcc2,1,2 + set_fcc 0xb 3 + fcbolr fcc3,1,3 + set_fcc 0xc 0 + fcbolr fcc0,1,0 + set_fcc 0xd 1 + fcbolr fcc1,1,1 + set_fcc 0xe 2 + fcbolr fcc2,1,2 + set_fcc 0xf 3 + fcbolr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbolr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbolr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbolr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbolr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbolr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbolr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbolr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbolr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbolr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbolr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbolr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbolr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbolr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbolr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbolr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbolr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbralr.cgs b/sim/testsuite/sim/frv/fcbralr.cgs new file mode 100644 index 00000000000..60359d8201e --- /dev/null +++ b/sim/testsuite/sim/frv/fcbralr.cgs @@ -0,0 +1,276 @@ +# frv testcase for fcbralr $ccond +# mach: all + + .include "testutils.inc" + + start + + .global fcbralr +fcbralr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_fcc 0x0 0 + fcbralr 0 + fail +ok1: + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbralr 0 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbralr 0 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbralr 0 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbralr 0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbralr 0 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbralr 0 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbralr 0 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbralr 0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbralr 0 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbralr 0 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbralr 0 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbralr 0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbralr 0 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbralr 0 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbralr 0 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_fcc 0x0 0 + fcbralr 1 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbralr 1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbralr 1 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbralr 1 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbralr 1 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbralr 1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbralr 1 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbralr 1 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbralr 1 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbralr 1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbralr 1 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbralr 1 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbralr 1 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbralr 1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbralr 1 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbralr 1 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbralr 1 + set_fcc 0x1 1 + fcbralr 1 + set_fcc 0x2 2 + fcbralr 1 + set_fcc 0x3 3 + fcbralr 1 + set_fcc 0x4 0 + fcbralr 1 + set_fcc 0x5 1 + fcbralr 1 + set_fcc 0x6 2 + fcbralr 1 + set_fcc 0x7 3 + fcbralr 1 + set_fcc 0x8 0 + fcbralr 1 + set_fcc 0x9 1 + fcbralr 1 + set_fcc 0xa 2 + fcbralr 1 + set_fcc 0xb 3 + fcbralr 1 + set_fcc 0xc 0 + fcbralr 1 + set_fcc 0xd 1 + fcbralr 1 + set_fcc 0xe 2 + fcbralr 1 + set_fcc 0xf 3 + fcbralr 1 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbralr 0 + + pass diff --git a/sim/testsuite/sim/frv/fcbuelr.cgs b/sim/testsuite/sim/frv/fcbuelr.cgs new file mode 100644 index 00000000000..e102ee31dec --- /dev/null +++ b/sim/testsuite/sim/frv/fcbuelr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcbuelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbuelr +fcbuelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbuelr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbuelr fcc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbuelr fcc2,0,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbuelr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbuelr fcc0,0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbuelr fcc1,0,1 + fail +ok6: + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbuelr fcc2,0,2 + + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbuelr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbuelr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbuelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbuelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbuelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbuelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbuelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbuelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbuelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbuelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbuelr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbuelr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbuelr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbuelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbuelr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbuelr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbuelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbuelr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbuelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbuelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbuelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbuelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbuelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbuelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbuelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbuelr fcc0,1,0 + set_fcc 0x1 1 + fcbuelr fcc1,1,1 + set_fcc 0x2 2 + fcbuelr fcc2,1,2 + set_fcc 0x3 3 + fcbuelr fcc3,1,3 + set_fcc 0x4 0 + fcbuelr fcc0,1,0 + set_fcc 0x5 1 + fcbuelr fcc1,1,1 + set_fcc 0x6 2 + fcbuelr fcc2,1,2 + set_fcc 0x7 3 + fcbuelr fcc3,1,3 + set_fcc 0x8 0 + fcbuelr fcc0,1,0 + set_fcc 0x9 1 + fcbuelr fcc1,1,1 + set_fcc 0xa 2 + fcbuelr fcc2,1,2 + set_fcc 0xb 3 + fcbuelr fcc3,1,3 + set_fcc 0xc 0 + fcbuelr fcc0,1,0 + set_fcc 0xd 1 + fcbuelr fcc1,1,1 + set_fcc 0xe 2 + fcbuelr fcc2,1,2 + set_fcc 0xf 3 + fcbuelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbuelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbuelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbuelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbuelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbuelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbuelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbuelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbuelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbuelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbuelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbuelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbuelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbuelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbuelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbuelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbuelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbugelr.cgs b/sim/testsuite/sim/frv/fcbugelr.cgs new file mode 100644 index 00000000000..8ecd1411115 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbugelr.cgs @@ -0,0 +1,274 @@ +# frv testcase for fcbugelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbugelr +fcbugelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbugelr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbugelr fcc1,0,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbugelr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbugelr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbugelr fcc0,0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbugelr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbugelr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbugelr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbugelr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbugelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbugelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbugelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbugelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbugelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbugelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbugelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbugelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbugelr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbugelr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbugelr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbugelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbugelr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbugelr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbugelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbugelr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbugelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbugelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbugelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbugelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbugelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbugelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbugelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbugelr fcc0,1,0 + set_fcc 0x1 1 + fcbugelr fcc1,1,1 + set_fcc 0x2 2 + fcbugelr fcc2,1,2 + set_fcc 0x3 3 + fcbugelr fcc3,1,3 + set_fcc 0x4 0 + fcbugelr fcc0,1,0 + set_fcc 0x5 1 + fcbugelr fcc1,1,1 + set_fcc 0x6 2 + fcbugelr fcc2,1,2 + set_fcc 0x7 3 + fcbugelr fcc3,1,3 + set_fcc 0x8 0 + fcbugelr fcc0,1,0 + set_fcc 0x9 1 + fcbugelr fcc1,1,1 + set_fcc 0xa 2 + fcbugelr fcc2,1,2 + set_fcc 0xb 3 + fcbugelr fcc3,1,3 + set_fcc 0xc 0 + fcbugelr fcc0,1,0 + set_fcc 0xd 1 + fcbugelr fcc1,1,1 + set_fcc 0xe 2 + fcbugelr fcc2,1,2 + set_fcc 0xf 3 + fcbugelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbugelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbugelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbugelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbugelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbugelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbugelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbugelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbugelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbugelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbugelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbugelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbugelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbugelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbugelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbugelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbugelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbuglr.cgs b/sim/testsuite/sim/frv/fcbuglr.cgs new file mode 100644 index 00000000000..d9470a81a89 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbuglr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcbuglr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbuglr +fcbuglr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbuglr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbuglr fcc1,0,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbuglr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbuglr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbuglr fcc0,0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbuglr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbuglr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbuglr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbuglr fcc0,0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbuglr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbuglr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbuglr fcc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbuglr fcc0,0,0 + + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbuglr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbuglr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbuglr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbuglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbuglr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbuglr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbuglr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbuglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbuglr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbuglr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbuglr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbuglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbuglr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbuglr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbuglr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbuglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbuglr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbuglr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbuglr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbuglr fcc0,1,0 + set_fcc 0x1 1 + fcbuglr fcc1,1,1 + set_fcc 0x2 2 + fcbuglr fcc2,1,2 + set_fcc 0x3 3 + fcbuglr fcc3,1,3 + set_fcc 0x4 0 + fcbuglr fcc0,1,0 + set_fcc 0x5 1 + fcbuglr fcc1,1,1 + set_fcc 0x6 2 + fcbuglr fcc2,1,2 + set_fcc 0x7 3 + fcbuglr fcc3,1,3 + set_fcc 0x8 0 + fcbuglr fcc0,1,0 + set_fcc 0x9 1 + fcbuglr fcc1,1,1 + set_fcc 0xa 2 + fcbuglr fcc2,1,2 + set_fcc 0xb 3 + fcbuglr fcc3,1,3 + set_fcc 0xc 0 + fcbuglr fcc0,1,0 + set_fcc 0xd 1 + fcbuglr fcc1,1,1 + set_fcc 0xe 2 + fcbuglr fcc2,1,2 + set_fcc 0xf 3 + fcbuglr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbuglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbuglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbuglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbuglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbuglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbuglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbuglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbuglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbuglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbuglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbuglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbuglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbuglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbuglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbuglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbuglr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbulelr.cgs b/sim/testsuite/sim/frv/fcbulelr.cgs new file mode 100644 index 00000000000..3f1da04a79b --- /dev/null +++ b/sim/testsuite/sim/frv/fcbulelr.cgs @@ -0,0 +1,274 @@ +# frv testcase for fcbulelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbulelr +fcbulelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbulelr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbulelr fcc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbulelr fcc2,0,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbulelr fcc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbulelr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbulelr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbulelr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbulelr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbulelr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbulelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbulelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbulelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbulelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbulelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbulelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbulelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbulelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbulelr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbulelr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbulelr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbulelr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbulelr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbulelr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbulelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbulelr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbulelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbulelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbulelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbulelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbulelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbulelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbulelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbulelr fcc0,1,0 + set_fcc 0x1 1 + fcbulelr fcc1,1,1 + set_fcc 0x2 2 + fcbulelr fcc2,1,2 + set_fcc 0x3 3 + fcbulelr fcc3,1,3 + set_fcc 0x4 0 + fcbulelr fcc0,1,0 + set_fcc 0x5 1 + fcbulelr fcc1,1,1 + set_fcc 0x6 2 + fcbulelr fcc2,1,2 + set_fcc 0x7 3 + fcbulelr fcc3,1,3 + set_fcc 0x8 0 + fcbulelr fcc0,1,0 + set_fcc 0x9 1 + fcbulelr fcc1,1,1 + set_fcc 0xa 2 + fcbulelr fcc2,1,2 + set_fcc 0xb 3 + fcbulelr fcc3,1,3 + set_fcc 0xc 0 + fcbulelr fcc0,1,0 + set_fcc 0xd 1 + fcbulelr fcc1,1,1 + set_fcc 0xe 2 + fcbulelr fcc2,1,2 + set_fcc 0xf 3 + fcbulelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbulelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbulelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbulelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbulelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbulelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbulelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbulelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbulelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbulelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbulelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbulelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbulelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbulelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbulelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbulelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbulelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbullr.cgs b/sim/testsuite/sim/frv/fcbullr.cgs new file mode 100644 index 00000000000..1a87dde129e --- /dev/null +++ b/sim/testsuite/sim/frv/fcbullr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcbullr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbullr +fcbullr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbullr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbullr fcc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbullr fcc2,0,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbullr fcc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbullr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbullr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbullr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbullr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbullr fcc0,0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbullr fcc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbullr fcc2,0,2 + + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbullr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbullr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbullr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbullr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbullr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbullr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbullr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbullr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbullr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbullr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbullr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbullr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbullr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbullr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbullr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbullr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbullr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbullr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbullr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbullr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbullr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbullr fcc0,1,0 + set_fcc 0x1 1 + fcbullr fcc1,1,1 + set_fcc 0x2 2 + fcbullr fcc2,1,2 + set_fcc 0x3 3 + fcbullr fcc3,1,3 + set_fcc 0x4 0 + fcbullr fcc0,1,0 + set_fcc 0x5 1 + fcbullr fcc1,1,1 + set_fcc 0x6 2 + fcbullr fcc2,1,2 + set_fcc 0x7 3 + fcbullr fcc3,1,3 + set_fcc 0x8 0 + fcbullr fcc0,1,0 + set_fcc 0x9 1 + fcbullr fcc1,1,1 + set_fcc 0xa 2 + fcbullr fcc2,1,2 + set_fcc 0xb 3 + fcbullr fcc3,1,3 + set_fcc 0xc 0 + fcbullr fcc0,1,0 + set_fcc 0xd 1 + fcbullr fcc1,1,1 + set_fcc 0xe 2 + fcbullr fcc2,1,2 + set_fcc 0xf 3 + fcbullr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbullr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbullr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbullr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbullr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbullr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbullr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbullr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbullr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbullr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbullr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbullr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbullr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbullr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbullr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbullr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbullr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbulr.cgs b/sim/testsuite/sim/frv/fcbulr.cgs new file mode 100644 index 00000000000..c81dff3e13c --- /dev/null +++ b/sim/testsuite/sim/frv/fcbulr.cgs @@ -0,0 +1,262 @@ +# frv testcase for fcbulr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbulr +fcbulr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbulr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbulr fcc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbulr fcc2,0,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbulr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbulr fcc0,0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbulr fcc1,0,1 + fail +ok6: + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbulr fcc2,0,2 + + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbulr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbulr fcc0,0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbulr fcc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbulr fcc2,0,2 + + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbulr fcc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbulr fcc0,0,0 + + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbulr fcc1,0,1 + fail +oke: + set_spr_addr bad,lr + set_fcc 0xe 2 + fcbulr fcc2,0,2 + + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbulr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbulr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbulr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbulr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbulr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbulr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbulr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbulr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbulr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbulr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbulr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbulr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbulr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbulr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbulr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xe 2 + fcbulr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbulr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbulr fcc0,1,0 + set_fcc 0x1 1 + fcbulr fcc1,1,1 + set_fcc 0x2 2 + fcbulr fcc2,1,2 + set_fcc 0x3 3 + fcbulr fcc3,1,3 + set_fcc 0x4 0 + fcbulr fcc0,1,0 + set_fcc 0x5 1 + fcbulr fcc1,1,1 + set_fcc 0x6 2 + fcbulr fcc2,1,2 + set_fcc 0x7 3 + fcbulr fcc3,1,3 + set_fcc 0x8 0 + fcbulr fcc0,1,0 + set_fcc 0x9 1 + fcbulr fcc1,1,1 + set_fcc 0xa 2 + fcbulr fcc2,1,2 + set_fcc 0xb 3 + fcbulr fcc3,1,3 + set_fcc 0xc 0 + fcbulr fcc0,1,0 + set_fcc 0xd 1 + fcbulr fcc1,1,1 + set_fcc 0xe 2 + fcbulr fcc2,1,2 + set_fcc 0xf 3 + fcbulr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbulr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbulr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbulr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbulr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbulr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbulr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbulr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbulr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbulr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbulr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbulr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbulr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbulr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbulr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbulr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbulr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fckeq.cgs b/sim/testsuite/sim/frv/fckeq.cgs new file mode 100644 index 00000000000..572a86d2438 --- /dev/null +++ b/sim/testsuite/sim/frv/fckeq.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckeq $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckeq +fckeq: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckge.cgs b/sim/testsuite/sim/frv/fckge.cgs new file mode 100644 index 00000000000..91a1efdfa9e --- /dev/null +++ b/sim/testsuite/sim/frv/fckge.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckge $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckge +fckge: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckgt.cgs b/sim/testsuite/sim/frv/fckgt.cgs new file mode 100644 index 00000000000..06715f96d0d --- /dev/null +++ b/sim/testsuite/sim/frv/fckgt.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckgt $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckgt +fckgt: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckle.cgs b/sim/testsuite/sim/frv/fckle.cgs new file mode 100644 index 00000000000..7d5e6dae951 --- /dev/null +++ b/sim/testsuite/sim/frv/fckle.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckle $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckle +fckle: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckle fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckle fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckle fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckle fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fcklg.cgs b/sim/testsuite/sim/frv/fcklg.cgs new file mode 100644 index 00000000000..f8df5a1152c --- /dev/null +++ b/sim/testsuite/sim/frv/fcklg.cgs @@ -0,0 +1,90 @@ +# frv testcase for fcklg $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fcklg +fcklg: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fcklg fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fcklg fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fcklg fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fcklg fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fcklt.cgs b/sim/testsuite/sim/frv/fcklt.cgs new file mode 100644 index 00000000000..14e53711879 --- /dev/null +++ b/sim/testsuite/sim/frv/fcklt.cgs @@ -0,0 +1,90 @@ +# frv testcase for fcklt $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fcklt +fcklt: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckne.cgs b/sim/testsuite/sim/frv/fckne.cgs new file mode 100644 index 00000000000..774f8379bfc --- /dev/null +++ b/sim/testsuite/sim/frv/fckne.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckne $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckne +fckne: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckne fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckne fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckno.cgs b/sim/testsuite/sim/frv/fckno.cgs new file mode 100644 index 00000000000..08513a25198 --- /dev/null +++ b/sim/testsuite/sim/frv/fckno.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckno $CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckno +fckno: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/sim/frv/fcko.cgs b/sim/testsuite/sim/frv/fcko.cgs new file mode 100644 index 00000000000..06d56407448 --- /dev/null +++ b/sim/testsuite/sim/frv/fcko.cgs @@ -0,0 +1,90 @@ +# frv testcase for fcko $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fcko +fcko: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fcko fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fcko fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckra.cgs b/sim/testsuite/sim/frv/fckra.cgs new file mode 100644 index 00000000000..a74b9fc32e6 --- /dev/null +++ b/sim/testsuite/sim/frv/fckra.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckra $CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckra +fckra: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fcku.cgs b/sim/testsuite/sim/frv/fcku.cgs new file mode 100644 index 00000000000..9aaa635eef7 --- /dev/null +++ b/sim/testsuite/sim/frv/fcku.cgs @@ -0,0 +1,90 @@ +# frv testcase for fcku $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fcku +fcku: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckue.cgs b/sim/testsuite/sim/frv/fckue.cgs new file mode 100644 index 00000000000..0bd7696171d --- /dev/null +++ b/sim/testsuite/sim/frv/fckue.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckue $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckue +fckue: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckue fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckue fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckue fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckue fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckug.cgs b/sim/testsuite/sim/frv/fckug.cgs new file mode 100644 index 00000000000..f810335eda4 --- /dev/null +++ b/sim/testsuite/sim/frv/fckug.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckug $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckug +fckug: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckug fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckug fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckug fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckug fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckuge.cgs b/sim/testsuite/sim/frv/fckuge.cgs new file mode 100644 index 00000000000..d8126389f77 --- /dev/null +++ b/sim/testsuite/sim/frv/fckuge.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckuge $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckuge +fckuge: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckuge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckuge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckul.cgs b/sim/testsuite/sim/frv/fckul.cgs new file mode 100644 index 00000000000..2d30d924186 --- /dev/null +++ b/sim/testsuite/sim/frv/fckul.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckul $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckul +fckul: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckul fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckul fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckul fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckul fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckule.cgs b/sim/testsuite/sim/frv/fckule.cgs new file mode 100644 index 00000000000..9830a66a8f5 --- /dev/null +++ b/sim/testsuite/sim/frv/fckule.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckule $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckule +fckule: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckule fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckule fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fcmpd.cgs b/sim/testsuite/sim/frv/fcmpd.cgs new file mode 100644 index 00000000000..5c862664845 --- /dev/null +++ b/sim/testsuite/sim/frv/fcmpd.cgs @@ -0,0 +1,601 @@ +# frv testcase for fcmpd $GRi,$GRj,$FCCi_2 +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fcmpd +fcmpd: + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr0,fr0,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr4,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr8,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr0,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr0,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr4,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr4,fr4,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr8,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr4,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr4,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr8,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr8,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr8,fr8,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr8,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr8,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr12,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr12,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr12,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr12,fr12,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr12,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr12,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr16,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr16,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr16,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr16,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr16,fr16,fcc0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr16,fr20,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr16,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr16,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr20,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr20,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr20,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr20,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr20,fr16,fcc0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr20,fr20,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr20,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr20,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr24,fr24,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr24,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr24,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr28,fr28,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr28,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr28,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr28,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr32,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr36,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr40,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr44,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr48,fr48,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr48,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr48,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr48,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr28,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr32,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr36,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr40,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr44,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr48,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr52,fr52,fcc0 + test_fcc 0x8,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr52,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr52,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr0,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr4,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr8,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr12,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr16,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr20,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr24,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr28,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr32,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr36,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr40,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr44,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr48,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr52,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr0,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr4,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr8,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr12,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr16,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr20,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr24,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr28,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr32,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr36,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr40,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr44,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr48,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr52,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr60,fcc0 + test_fcc 0x1,0 + + pass diff --git a/sim/testsuite/sim/frv/fcmps.cgs b/sim/testsuite/sim/frv/fcmps.cgs new file mode 100644 index 00000000000..93bf3ea2c31 --- /dev/null +++ b/sim/testsuite/sim/frv/fcmps.cgs @@ -0,0 +1,600 @@ +# frv testcase for fcmps $GRi,$GRj,$FCCi_2 +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fcmps +fcmps: + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr0,fr0,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr4,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr8,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr0,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr0,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr4,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr4,fr4,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr8,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr4,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr4,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr8,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr8,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr8,fr8,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr8,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr8,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr12,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr12,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr12,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr12,fr12,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr12,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr12,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr16,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr16,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr16,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr16,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr16,fr16,fcc0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr16,fr20,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr16,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr16,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr20,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr20,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr20,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr20,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr20,fr16,fcc0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr20,fr20,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr20,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr20,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr24,fr24,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr24,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr24,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr28,fr28,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr28,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr28,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr28,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr32,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr36,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr40,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr44,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr48,fr48,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr48,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr48,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr48,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr28,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr32,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr36,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr40,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr44,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr48,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr52,fr52,fcc0 + test_fcc 0x8,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr52,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr52,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr0,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr4,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr8,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr12,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr16,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr20,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr24,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr28,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr32,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr36,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr40,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr44,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr48,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr52,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr0,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr4,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr8,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr12,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr16,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr20,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr24,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr28,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr32,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr36,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr40,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr44,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr48,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr52,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr60,fcc0 + test_fcc 0x1,0 + + pass diff --git a/sim/testsuite/sim/frv/fdabss.cgs b/sim/testsuite/sim/frv/fdabss.cgs new file mode 100644 index 00000000000..83d3e1c723e --- /dev/null +++ b/sim/testsuite/sim/frv/fdabss.cgs @@ -0,0 +1,25 @@ +# frv testcase for fdabss $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdabss +fdabss: + set_fr_fr fr8,fr1 + fdabss fr0,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr28 + set_fr_fr fr24,fr13 + fdabss fr12,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + set_fr_fr fr52,fr29 + fdabss fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr52 + + pass diff --git a/sim/testsuite/sim/frv/fdadds.cgs b/sim/testsuite/sim/frv/fdadds.cgs new file mode 100644 index 00000000000..f72f6e632e0 --- /dev/null +++ b/sim/testsuite/sim/frv/fdadds.cgs @@ -0,0 +1,134 @@ +# frv testcase for fdadds $GRi,$GRj,$GRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdadds +fdadds: + fdadds fr16,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdadds fr16,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdadds fr16,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdadds fr16,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdadds fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr16,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdadds fr16,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdadds fr16,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdadds fr16,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdadds fr16,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdadds fr16,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdadds fr16,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdadds fr16,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdadds fr20,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdadds fr20,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdadds fr20,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdadds fr20,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdadds fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr20,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdadds fr20,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdadds fr20,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdadds fr20,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdadds fr20,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdadds fr20,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdadds fr20,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdadds fr20,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdadds fr8,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr12,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr24,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr28,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdadds fr36,fr40,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + + pass + + diff --git a/sim/testsuite/sim/frv/fdcmps.cgs b/sim/testsuite/sim/frv/fdcmps.cgs new file mode 100644 index 00000000000..90686331e0b --- /dev/null +++ b/sim/testsuite/sim/frv/fdcmps.cgs @@ -0,0 +1,985 @@ +# frv testcase for fdcmps $FRi,$FRj,$FCCi_2 +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdcmps +fdcmps: + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr0,fr0,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr4,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr8,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr0,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr0,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr4,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr4,fr4,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr8,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr4,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr4,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr8,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr8,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr8,fr8,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr8,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr8,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr12,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr12,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr12,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr12,fr12,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr12,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr12,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr16,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr16,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr16,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr16,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr16,fr16,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr16,fr20,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr16,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr16,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr20,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr20,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr20,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr20,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr20,fr16,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr20,fr20,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr20,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr20,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr24,fr24,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr24,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr24,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr28,fr28,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr28,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr28,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr28,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr32,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr36,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr40,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr44,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr48,fr48,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr48,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr48,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr48,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr28,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr32,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr36,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr40,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr44,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr48,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr52,fr52,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr52,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr52,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr0,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr4,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr8,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr12,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr16,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr20,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr24,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr28,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr32,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr36,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr40,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr44,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr48,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr52,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr0,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr4,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr8,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr12,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr16,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr20,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr24,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr28,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr32,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr36,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr40,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr44,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr48,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr52,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + pass diff --git a/sim/testsuite/sim/frv/fddivs.cgs b/sim/testsuite/sim/frv/fddivs.cgs new file mode 100644 index 00000000000..ac423b29b1a --- /dev/null +++ b/sim/testsuite/sim/frv/fddivs.cgs @@ -0,0 +1,195 @@ +# frv testcase for fddivs $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fddivs +fddivs: + fddivs fr0,fr28,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fddivs fr4,fr28,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fddivs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fddivs fr12,fr28,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fddivs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr24,fr28,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fddivs fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fddivs fr32,fr28,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fddivs fr36,fr28,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fddivs fr40,fr28,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fddivs fr44,fr28,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fddivs fr48,fr28,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fddivs fr52,fr28,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fddivs fr16,fr0,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr52,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fddivs fr20,fr0,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr52,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fddivs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fddivs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + + fddivs fr40,fr32,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + + pass + + diff --git a/sim/testsuite/sim/frv/fditos.cgs b/sim/testsuite/sim/frv/fditos.cgs new file mode 100644 index 00000000000..412e8afa649 --- /dev/null +++ b/sim/testsuite/sim/frv/fditos.cgs @@ -0,0 +1,25 @@ +# frv testcase for fditos $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fditos +fditos: + set_fr_iimmed 0,0,fr2 + set_fr_iimmed 0x0000,0x0002,fr3 + fditos fr2,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + + set_fr_iimmed 0xdead,0xbeef,fr2 + set_fr_iimmed 0xdead,0xbeef,fr3 + fditos fr2,fr2 + test_fr_iimmed 0xce054904,fr2 + test_fr_iimmed 0xce054904,fr3 + + pass diff --git a/sim/testsuite/sim/frv/fdivd.cgs b/sim/testsuite/sim/frv/fdivd.cgs new file mode 100644 index 00000000000..65222bb64bf --- /dev/null +++ b/sim/testsuite/sim/frv/fdivd.cgs @@ -0,0 +1,128 @@ +# frv testcase for fdivd $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fdivd +fdivd: + fdivd fr0,fr28,fr2 + test_dfr_dfr fr2,fr0 + fdivd fr4,fr28,fr2 + test_dfr_dfr fr2,fr4 + fdivd fr8,fr28,fr2 + test_dfr_dfr fr2,fr8 + fdivd fr12,fr28,fr2 + test_dfr_dfr fr2,fr12 + fdivd fr16,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr24,fr28,fr2 + test_dfr_dfr fr2,fr24 + fdivd fr28,fr28,fr2 + test_dfr_dfr fr2,fr28 + fdivd fr32,fr28,fr2 + test_dfr_dfr fr2,fr32 + fdivd fr36,fr28,fr2 + test_dfr_dfr fr2,fr36 + fdivd fr40,fr28,fr2 + test_dfr_dfr fr2,fr40 + fdivd fr44,fr28,fr2 + test_dfr_dfr fr2,fr44 + fdivd fr48,fr28,fr2 + test_dfr_dfr fr2,fr48 + fdivd fr52,fr28,fr2 + test_dfr_dfr fr2,fr52 + + fdivd fr16,fr0,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr52,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fdivd fr20,fr0,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr52,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fdivd fr8,fr28,fr2 + test_dfr_dfr fr2,fr8 + fdivd fr28,fr8,fr2 + test_dfr_dfr fr2,fr8 + + fdivd fr40,fr32,fr2 + test_dfr_dfr fr2,fr36 + + pass + + diff --git a/sim/testsuite/sim/frv/fdivs.cgs b/sim/testsuite/sim/frv/fdivs.cgs new file mode 100644 index 00000000000..abb3092139d --- /dev/null +++ b/sim/testsuite/sim/frv/fdivs.cgs @@ -0,0 +1,127 @@ +# frv testcase for fdivs $GRi,$GRj,$GRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdivs +fdivs: + fdivs fr0,fr28,fr1 + test_fr_fr fr1,fr0 + fdivs fr4,fr28,fr1 + test_fr_fr fr1,fr4 + fdivs fr8,fr28,fr1 + test_fr_fr fr1,fr8 + fdivs fr12,fr28,fr1 + test_fr_fr fr1,fr12 + fdivs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr24,fr28,fr1 + test_fr_fr fr1,fr24 + fdivs fr28,fr28,fr1 + test_fr_fr fr1,fr28 + fdivs fr32,fr28,fr1 + test_fr_fr fr1,fr32 + fdivs fr36,fr28,fr1 + test_fr_fr fr1,fr36 + fdivs fr40,fr28,fr1 + test_fr_fr fr1,fr40 + fdivs fr44,fr28,fr1 + test_fr_fr fr1,fr44 + fdivs fr48,fr28,fr1 + test_fr_fr fr1,fr48 + fdivs fr52,fr28,fr1 + test_fr_fr fr1,fr52 + + fdivs fr16,fr0,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr52,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fdivs fr20,fr0,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr52,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fdivs fr8,fr28,fr1 + test_fr_fr fr1,fr8 + fdivs fr28,fr8,fr1 + test_fr_fr fr1,fr8 + + fdivs fr40,fr32,fr1 + test_fr_fr fr1,fr36 + + pass + + diff --git a/sim/testsuite/sim/frv/fdmadds.cgs b/sim/testsuite/sim/frv/fdmadds.cgs new file mode 100644 index 00000000000..7035366ac50 --- /dev/null +++ b/sim/testsuite/sim/frv/fdmadds.cgs @@ -0,0 +1,226 @@ +# frv testcase for fdmadds $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdmadds +fdmadds: + fdmadds fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdmadds fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + set_fr_fr fr36,fr2 + set_fr_fr fr36,fr3 + fdmadds fr28,fr8,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdmadds fr8,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + + set_fr_fr fr36,fr2 + set_fr_fr fr36,fr3 + fdmadds fr32,fr36,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + + pass diff --git a/sim/testsuite/sim/frv/fdmas.cgs b/sim/testsuite/sim/frv/fdmas.cgs new file mode 100644 index 00000000000..a7162db296e --- /dev/null +++ b/sim/testsuite/sim/frv/fdmas.cgs @@ -0,0 +1,265 @@ +# frv testcase for fdmas $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + load_float_constants2 + load_float_constants3 + + .global fdmas +fdmas: + fdmas fr16,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr4 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr4 + fdmas fr16,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + fdmas fr16,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr12 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr12 + fdmas fr16,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr16,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr16,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr24 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr24 + fdmas fr16,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmas fr16,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr32 + fdmas fr16,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr36 + fdmas fr16,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr40 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr40 + fdmas fr16,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr44 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr44 + fdmas fr16,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr48 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr48 + + fdmas fr20,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr4 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr4 + fdmas fr20,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + fdmas fr20,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr12 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr12 + fdmas fr20,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr20,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr20,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr24 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr24 + fdmas fr20,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmas fr20,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr32 + fdmas fr20,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr36 + fdmas fr20,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr40 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr40 + fdmas fr20,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr44 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr44 + fdmas fr20,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr48 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr48 + + fdmas fr28,fr0,fr60 + test_fr_fr fr60,fr0 + test_fr_fr fr62,fr0 + fdmas fr28,fr4,fr60 + test_fr_fr fr60,fr4 + test_fr_fr fr62,fr4 + fdmas fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr28,fr12,fr60 + test_fr_fr fr60,fr12 + test_fr_fr fr62,fr12 + fdmas fr28,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmas fr28,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmas fr28,fr24,fr60 + test_fr_fr fr60,fr24 + test_fr_fr fr62,fr24 + fdmas fr28,fr28,fr60 + test_fr_fr fr60,fr28 + test_fr_fr fr62,fr28 + fdmas fr28,fr32,fr60 + test_fr_fr fr60,fr32 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr32 + test_fr_fr fr63,fr36 + fdmas fr28,fr36,fr60 + test_fr_fr fr60,fr36 + test_fr_fr fr62,fr36 + fdmas fr28,fr40,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + fdmas fr28,fr44,fr60 + test_fr_fr fr60,fr44 + test_fr_fr fr62,fr44 + fdmas fr28,fr48,fr60 + test_fr_fr fr60,fr48 + test_fr_fr fr62,fr48 + fdmas fr28,fr52,fr60 + test_fr_fr fr60,fr52 + test_fr_fr fr62,fr52 + + fdmas fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr8,fr28,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + + fdmas fr32,fr36,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + + pass diff --git a/sim/testsuite/sim/frv/fdmovs.cgs b/sim/testsuite/sim/frv/fdmovs.cgs new file mode 100644 index 00000000000..58e9607ccfc --- /dev/null +++ b/sim/testsuite/sim/frv/fdmovs.cgs @@ -0,0 +1,45 @@ +# frv testcase for fdmovs $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdmovs +fdmovs: + set_fr_fr fr4,fr1 + fdmovs fr0,fr2 + test_fr_fr fr0,fr2 + test_fr_fr fr4,fr3 + set_fr_fr fr12,fr9 + fdmovs fr8,fr2 + test_fr_fr fr8,fr2 + test_fr_fr fr12,fr3 + set_fr_fr fr20,fr17 + fdmovs fr16,fr2 + test_fr_fr fr16,fr2 + test_fr_fr fr20,fr3 + set_fr_fr fr28,fr25 + fdmovs fr24,fr2 + test_fr_fr fr24,fr2 + test_fr_fr fr28,fr3 + set_fr_fr fr36,fr33 + fdmovs fr32,fr2 + test_fr_fr fr32,fr2 + test_fr_fr fr36,fr3 + set_fr_fr fr44,fr41 + fdmovs fr40,fr2 + test_fr_fr fr40,fr2 + test_fr_fr fr44,fr3 + set_fr_fr fr52,fr49 + fdmovs fr48,fr2 + test_fr_fr fr48,fr2 + test_fr_fr fr52,fr3 + set_fr_fr fr60,fr57 + fdmovs fr56,fr2 + test_fr_iimmed 0x7fc00000,fr2 + test_fr_iimmed 0x7f800001,fr3 + + pass diff --git a/sim/testsuite/sim/frv/fdmss.cgs b/sim/testsuite/sim/frv/fdmss.cgs new file mode 100644 index 00000000000..5457a1ee600 --- /dev/null +++ b/sim/testsuite/sim/frv/fdmss.cgs @@ -0,0 +1,235 @@ +# frv testcase for fdmss $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + load_float_constants2 + load_float_constants3 + + .global fdmss +fdmss: + fdmss fr16,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmss fr16,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmss fr16,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmss fr16,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + fdmss fr16,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + + fdmss fr20,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmss fr20,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmss fr20,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmss fr20,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + fdmss fr20,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + + fdmss fr28,fr0,fr60 + test_fr_fr fr60,fr0 + test_fr_fr fr62,fr0 + fdmss fr28,fr4,fr60 + test_fr_fr fr60,fr4 + test_fr_fr fr62,fr4 + fdmss fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr32 + fdmss fr28,fr12,fr60 + test_fr_fr fr60,fr12 + test_fr_fr fr62,fr12 + fdmss fr28,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmss fr28,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmss fr28,fr24,fr60 + test_fr_fr fr60,fr24 + test_fr_fr fr62,fr24 + fdmss fr28,fr28,fr60 + test_fr_fr fr60,fr28 + test_fr_fr fr61,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr62,fr28 + test_fr_fr fr63,fr20 + test_fr_fr fr63,fr16 + fdmss fr28,fr32,fr60 + test_fr_fr fr60,fr32 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr32 + test_fr_fr fr63,fr8 + fdmss fr28,fr36,fr60 + test_fr_fr fr60,fr36 + test_fr_fr fr62,fr36 + fdmss fr28,fr40,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + fdmss fr28,fr44,fr60 + test_fr_fr fr60,fr44 + test_fr_fr fr62,fr44 + fdmss fr28,fr48,fr60 + test_fr_fr fr60,fr48 + test_fr_fr fr62,fr48 + fdmss fr28,fr52,fr60 + test_fr_fr fr60,fr52 + test_fr_fr fr62,fr52 + + fdmss fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr32 + fdmss fr8,fr28,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr62,fr8 + + fdmss fr32,fr36,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr40 + test_fr_fr fr63,fr8 + + pass diff --git a/sim/testsuite/sim/frv/fdmulcs.cgs b/sim/testsuite/sim/frv/fdmulcs.cgs new file mode 100644 index 00000000000..d243ed7ab92 --- /dev/null +++ b/sim/testsuite/sim/frv/fdmulcs.cgs @@ -0,0 +1,201 @@ +# frv testcase for fdmulcs $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdmulcs +fdmulcs: + fdmulcs fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdmulcs fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr2,fr20 + fdmulcs fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdmulcs fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdmulcs fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdmulcs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdmulcs fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdmulcs fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdmulcs fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdmulcs fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdmulcs fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdmulcs fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdmulcs fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdmulcs fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdmulcs fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdmulcs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdmulcs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + + fdmulcs fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + + set_fr_fr fr32,fr50 ; 2 + set_fr_fr fr28,fr51 ; 1 + set_fr_fr fr44,fr52 ; 9 + set_fr_fr fr36,fr53 ; 3 + fdmulcs fr50,fr52,fr54 ; 2*3, 1*9 + test_fr_fr fr54,fr40 ; 6 + test_fr_fr fr55,fr44 ; 9 + + pass diff --git a/sim/testsuite/sim/frv/fdmuls.cgs b/sim/testsuite/sim/frv/fdmuls.cgs new file mode 100644 index 00000000000..180f0e73b45 --- /dev/null +++ b/sim/testsuite/sim/frv/fdmuls.cgs @@ -0,0 +1,193 @@ +# frv testcase for fdmuls $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdmuls +fdmuls: + fdmuls fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdmuls fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr2,fr20 + fdmuls fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdmuls fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdmuls fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdmuls fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdmuls fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdmuls fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdmuls fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdmuls fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdmuls fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdmuls fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdmuls fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdmuls fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdmuls fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdmuls fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdmuls fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + + fdmuls fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + + pass diff --git a/sim/testsuite/sim/frv/fdnegs.cgs b/sim/testsuite/sim/frv/fdnegs.cgs new file mode 100644 index 00000000000..db409cb04a4 --- /dev/null +++ b/sim/testsuite/sim/frv/fdnegs.cgs @@ -0,0 +1,25 @@ +# frv testcase for fdnegs $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdnegs +fdnegs: + set_fr_fr fr8,fr1 + fdnegs fr0,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr28 + set_fr_fr fr24,fr13 + fdnegs fr12,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr12 + set_fr_fr fr52,fr29 + fdnegs fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr0 + + pass diff --git a/sim/testsuite/sim/frv/fdsads.cgs b/sim/testsuite/sim/frv/fdsads.cgs new file mode 100644 index 00000000000..55e6ed103bc --- /dev/null +++ b/sim/testsuite/sim/frv/fdsads.cgs @@ -0,0 +1,119 @@ +# frv testcase for fdsads $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdsads +fdsads: + fdsads fr16,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr52 + fdsads fr16,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr48 + fdsads fr16,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr28 + fdsads fr16,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr24 + fdsads fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsads fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsads fr16,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr12 + fdsads fr16,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr8 + fdsads fr16,fr32,fr2 + test_fr_fr fr2,fr32 + fdsads fr16,fr36,fr2 + test_fr_fr fr2,fr36 + fdsads fr16,fr40,fr2 + test_fr_fr fr2,fr40 + fdsads fr16,fr44,fr2 + test_fr_fr fr2,fr44 + fdsads fr16,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr4 + fdsads fr16,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr0 + + fdsads fr20,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr52 + fdsads fr20,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr48 + fdsads fr20,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr28 + fdsads fr20,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr24 + fdsads fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsads fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsads fr20,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr12 + fdsads fr20,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr8 + fdsads fr20,fr32,fr2 + test_fr_fr fr2,fr32 + fdsads fr20,fr36,fr2 + test_fr_fr fr2,fr36 + fdsads fr20,fr40,fr2 + test_fr_fr fr2,fr40 + fdsads fr20,fr44,fr2 + test_fr_fr fr2,fr44 + fdsads fr20,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr4 + fdsads fr20,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr0 + + fdsads fr8,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fdsads fr12,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fdsads fr24,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fdsads fr28,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + test_fr_fr fr3,fr32 + + fdsads fr36,fr40,fr2 + test_fr_fr fr2,fr44 + + pass + + diff --git a/sim/testsuite/sim/frv/fdsqrts.cgs b/sim/testsuite/sim/frv/fdsqrts.cgs new file mode 100644 index 00000000000..6026b93a2a0 --- /dev/null +++ b/sim/testsuite/sim/frv/fdsqrts.cgs @@ -0,0 +1,17 @@ +# frv testcase for fdsqrts $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdsqrts +fdsqrts: + set_fr_iimmed 0x4049,0x0fdb,fr45 ; 3.141592654 + fdsqrts fr44,fr2 ; 9.0 + test_fr_fr fr2,fr36 ; 3.0 + test_fr_iimmed 0x3fe2dfc5,fr3 ; 1.7724539 + + pass diff --git a/sim/testsuite/sim/frv/fdstoi.cgs b/sim/testsuite/sim/frv/fdstoi.cgs new file mode 100644 index 00000000000..5c79e49dfc6 --- /dev/null +++ b/sim/testsuite/sim/frv/fdstoi.cgs @@ -0,0 +1,23 @@ +# frv testcase for fdstoi $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdstoi +fdstoi: + set_fr_fr fr20,fr17 + fdstoi fr16,fr2 + test_fr_iimmed 0,fr2 + test_fr_iimmed 0,fr3 + + set_fr_iimmed 0xce05,0x4904,fr2 + set_fr_fr fr32,fr3 + fdstoi fr2,fr2 + test_fr_iimmed 0xdeadbf00,fr2 + test_fr_iimmed 0x00000002,fr3 + + pass diff --git a/sim/testsuite/sim/frv/fdsubs.cgs b/sim/testsuite/sim/frv/fdsubs.cgs new file mode 100644 index 00000000000..34121de237c --- /dev/null +++ b/sim/testsuite/sim/frv/fdsubs.cgs @@ -0,0 +1,117 @@ +# frv testcase for fdsubs $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdsubs +fdsubs: + fdsubs fr0,fr16,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdsubs fr4,fr16,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdsubs fr8,fr16,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdsubs fr12,fr16,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdsubs fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsubs fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsubs fr24,fr16,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdsubs fr28,fr16,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdsubs fr32,fr16,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdsubs fr36,fr16,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdsubs fr40,fr16,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdsubs fr44,fr16,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdsubs fr48,fr16,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdsubs fr52,fr16,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdsubs fr0,fr20,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdsubs fr4,fr20,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdsubs fr8,fr20,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdsubs fr12,fr20,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdsubs fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsubs fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsubs fr24,fr20,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdsubs fr28,fr20,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdsubs fr32,fr20,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdsubs fr36,fr20,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdsubs fr40,fr20,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdsubs fr44,fr20,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdsubs fr48,fr20,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdsubs fr52,fr20,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdsubs fr32,fr36,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + + fdsubs fr44,fr40,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + + pass + + diff --git a/sim/testsuite/sim/frv/fdtoi.cgs b/sim/testsuite/sim/frv/fdtoi.cgs new file mode 100644 index 00000000000..1749852263e --- /dev/null +++ b/sim/testsuite/sim/frv/fdtoi.cgs @@ -0,0 +1,32 @@ +# frv testcase for fdtoi $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global fdtoi +fdtoi: + set_fr_iimmed 0,0,fr2 + set_fr_iimmed 0,0,fr3 + fdtoi fr2,fr2 + test_fr_iimmed 0,fr2 + + set_fr_iimmed 0x4000,0x0000,fr2 + set_fr_iimmed 0x0000,0x0000,fr3 + fdtoi fr2,fr2 + test_fr_iimmed 0x00000002,fr2 + + set_fr_iimmed 0xc1c0,0xa920,fr2 + set_fr_iimmed 0x8880,0x0000,fr3 + fdtoi fr2,fr2 + test_fr_iimmed 0xdeadbeef,fr2 + + set_gr_limmed 0x4031,0x0000,gr8 + set_gr_limmed 0x0000,0x0000,gr9 + movgfd gr8,fr0 + fdtoi fr0,fr0 + test_fr_iimmed 17,fr0 + + pass diff --git a/sim/testsuite/sim/frv/fitod.cgs b/sim/testsuite/sim/frv/fitod.cgs new file mode 100644 index 00000000000..62ef1f21f39 --- /dev/null +++ b/sim/testsuite/sim/frv/fitod.cgs @@ -0,0 +1,26 @@ +# frv testcase for fitod $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global fitod +fitod: + set_fr_iimmed 0,0,fr2 + fitod fr2,fr2 + test_fr_iimmed 0,fr2 + test_fr_iimmed 0,fr3 + + set_fr_iimmed 0x0000,0x0002,fr2 + fitod fr2,fr2 + test_fr_iimmed 0x40000000,fr2 + test_fr_iimmed 0x00000000,fr3 + + set_fr_iimmed 0xdead,0xbeef,fr2 + fitod fr2,fr2 + test_fr_iimmed 0xc1c0a920,fr2 + test_fr_iimmed 0x88800000,fr3 + + pass diff --git a/sim/testsuite/sim/frv/fitos.cgs b/sim/testsuite/sim/frv/fitos.cgs new file mode 100644 index 00000000000..b9369125597 --- /dev/null +++ b/sim/testsuite/sim/frv/fitos.cgs @@ -0,0 +1,25 @@ +# frv testcase for fitos $FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fitos +fitos: + set_fr_iimmed 0,0,fr1 + fitos fr1,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_iimmed 0x0000,0x0002,fr1 + fitos fr1,fr1 + test_fr_fr fr1,fr32 + + set_fr_iimmed 0xdead,0xbeef,fr1 + fitos fr1,fr1 + test_fr_iimmed 0xce054904,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fmad.cgs b/sim/testsuite/sim/frv/fmad.cgs new file mode 100644 index 00000000000..64fee9c56ea --- /dev/null +++ b/sim/testsuite/sim/frv/fmad.cgs @@ -0,0 +1,161 @@ +# frv testcase for fmad $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fmad +fmad: + fmad fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + fmad fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmad fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + fmad fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + fmad fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmad fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + fmad fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + fmad fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + fmad fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + fmad fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + fmad fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + fmad fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmad fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + fmad fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + fmad fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmad fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + fmad fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + fmad fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + fmad fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + fmad fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + fmad fr28,fr0,fr2 + test_fr_fr fr2,fr0 + fmad fr28,fr4,fr2 + test_fr_fr fr2,fr4 + fmad fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr28,fr12,fr2 + test_fr_fr fr2,fr12 + fmad fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmad fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmad fr28,fr24,fr2 + test_fr_fr fr2,fr24 + fmad fr28,fr28,fr2 + test_fr_fr fr2,fr28 + fmad fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr36 + fmad fr28,fr36,fr2 + test_fr_fr fr2,fr36 + fmad fr28,fr40,fr2 + test_fr_fr fr2,fr40 + fmad fr28,fr44,fr2 + test_fr_fr fr2,fr44 + fmad fr28,fr48,fr2 + test_fr_fr fr2,fr48 + fmad fr28,fr52,fr2 + test_fr_fr fr2,fr52 + + fmad fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fmad fr32,fr36,fr2 + test_fr_fr fr2,fr40 + + pass diff --git a/sim/testsuite/sim/frv/fmaddd.cgs b/sim/testsuite/sim/frv/fmaddd.cgs new file mode 100644 index 00000000000..bfa816f1a2a --- /dev/null +++ b/sim/testsuite/sim/frv/fmaddd.cgs @@ -0,0 +1,143 @@ +# frv testcase for fmaddd $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fmaddd +fmaddd: + set_dfr_dfr fr16,fr2 + fmaddd fr16,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fmaddd fr20,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr0,fr2 + test_dfr_dfr fr2,fr0 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr4,fr2 + test_dfr_dfr fr2,fr4 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr8,fr2 + test_dfr_dfr fr2,fr8 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr12,fr2 + test_dfr_dfr fr2,fr12 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr24,fr2 + test_dfr_dfr fr2,fr24 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr28,fr2 + test_dfr_dfr fr2,fr28 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr32,fr2 + test_dfr_dfr fr2,fr32 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr36,fr2 + test_dfr_dfr fr2,fr36 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr40,fr2 + test_dfr_dfr fr2,fr40 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr44,fr2 + test_dfr_dfr fr2,fr44 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr48,fr2 + test_dfr_dfr fr2,fr48 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr52,fr2 + test_dfr_dfr fr2,fr52 + + set_dfr_dfr fr36,fr2 + fmaddd fr28,fr8,fr2 + test_dfr_dfr fr2,fr32 + fmaddd fr8,fr28,fr2 + test_dfr_dfr fr2,fr28 + + set_dfr_dfr fr36,fr2 + fmaddd fr32,fr36,fr2 + test_dfr_dfr fr2,fr44 + + pass diff --git a/sim/testsuite/sim/frv/fmadds.cgs b/sim/testsuite/sim/frv/fmadds.cgs new file mode 100644 index 00000000000..128c82a9b56 --- /dev/null +++ b/sim/testsuite/sim/frv/fmadds.cgs @@ -0,0 +1,143 @@ +# frv testcase for fmadds $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fmadds +fmadds: + set_fr_fr fr16,fr1 + fmadds fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fmadds fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + fmadds fr28,fr0,fr1 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + fmadds fr28,fr4,fr1 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + fmadds fr28,fr8,fr1 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + fmadds fr28,fr12,fr1 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + fmadds fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + fmadds fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + fmadds fr28,fr24,fr1 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + fmadds fr28,fr28,fr1 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + fmadds fr28,fr32,fr1 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + fmadds fr28,fr36,fr1 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + fmadds fr28,fr40,fr1 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + fmadds fr28,fr44,fr1 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + fmadds fr28,fr48,fr1 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + fmadds fr28,fr52,fr1 + test_fr_fr fr1,fr52 + + set_fr_fr fr36,fr1 + fmadds fr28,fr8,fr1 + test_fr_fr fr1,fr32 + fmadds fr8,fr28,fr1 + test_fr_fr fr1,fr28 + + set_fr_fr fr36,fr1 + fmadds fr32,fr36,fr1 + test_fr_fr fr1,fr44 + + pass diff --git a/sim/testsuite/sim/frv/fmas.cgs b/sim/testsuite/sim/frv/fmas.cgs new file mode 100644 index 00000000000..bc2e14fcd63 --- /dev/null +++ b/sim/testsuite/sim/frv/fmas.cgs @@ -0,0 +1,161 @@ +# frv testcase for fmas $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fmas +fmas: + fmas fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + fmas fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmas fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + fmas fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + fmas fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmas fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + fmas fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + fmas fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + fmas fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + fmas fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + fmas fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + fmas fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmas fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + fmas fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + fmas fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmas fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + fmas fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + fmas fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + fmas fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + fmas fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + fmas fr28,fr0,fr2 + test_fr_fr fr2,fr0 + fmas fr28,fr4,fr2 + test_fr_fr fr2,fr4 + fmas fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr28,fr12,fr2 + test_fr_fr fr2,fr12 + fmas fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmas fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmas fr28,fr24,fr2 + test_fr_fr fr2,fr24 + fmas fr28,fr28,fr2 + test_fr_fr fr2,fr28 + fmas fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr36 + fmas fr28,fr36,fr2 + test_fr_fr fr2,fr36 + fmas fr28,fr40,fr2 + test_fr_fr fr2,fr40 + fmas fr28,fr44,fr2 + test_fr_fr fr2,fr44 + fmas fr28,fr48,fr2 + test_fr_fr fr2,fr48 + fmas fr28,fr52,fr2 + test_fr_fr fr2,fr52 + + fmas fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fmas fr32,fr36,fr2 + test_fr_fr fr2,fr40 + + pass diff --git a/sim/testsuite/sim/frv/fmovd.cgs b/sim/testsuite/sim/frv/fmovd.cgs new file mode 100644 index 00000000000..938faa2adf6 --- /dev/null +++ b/sim/testsuite/sim/frv/fmovd.cgs @@ -0,0 +1,48 @@ +# frv testcase for fmovd $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fmovd +fmovd: + fmovd fr0,fr2 + test_dfr_dfr fr0,fr2 + fmovd fr4,fr2 + test_dfr_dfr fr4,fr2 + fmovd fr8,fr2 + test_dfr_dfr fr8,fr2 + fmovd fr12,fr2 + test_dfr_dfr fr12,fr2 + fmovd fr16,fr2 + test_dfr_dfr fr16,fr2 + fmovd fr20,fr2 + test_dfr_dfr fr20,fr2 + fmovd fr24,fr2 + test_dfr_dfr fr24,fr2 + fmovd fr28,fr2 + test_dfr_dfr fr28,fr2 + fmovd fr32,fr2 + test_dfr_dfr fr32,fr2 + fmovd fr36,fr2 + test_dfr_dfr fr36,fr2 + fmovd fr40,fr2 + test_dfr_dfr fr40,fr2 + fmovd fr44,fr2 + test_dfr_dfr fr44,fr2 + fmovd fr48,fr2 + test_dfr_dfr fr48,fr2 + fmovd fr52,fr2 + test_dfr_dfr fr52,fr2 + fmovd fr56,fr2 + test_fr_iimmed 0x7ff80000,fr2 + test_fr_iimmed 0x00000000,fr3 + fmovd fr60,fr2 + test_fr_iimmed 0x7ff00000,fr2 + test_fr_iimmed 0x00000001,fr3 + + pass diff --git a/sim/testsuite/sim/frv/fmovs.cgs b/sim/testsuite/sim/frv/fmovs.cgs new file mode 100644 index 00000000000..46521b209f7 --- /dev/null +++ b/sim/testsuite/sim/frv/fmovs.cgs @@ -0,0 +1,45 @@ +# frv testcase for fmovs $FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fmovs +fmovs: + fmovs fr0,fr1 + test_fr_fr fr0,fr1 + fmovs fr4,fr1 + test_fr_fr fr4,fr1 + fmovs fr8,fr1 + test_fr_fr fr8,fr1 + fmovs fr12,fr1 + test_fr_fr fr12,fr1 + fmovs fr16,fr1 + test_fr_fr fr16,fr1 + fmovs fr20,fr1 + test_fr_fr fr20,fr1 + fmovs fr24,fr1 + test_fr_fr fr24,fr1 + fmovs fr28,fr1 + test_fr_fr fr28,fr1 + fmovs fr32,fr1 + test_fr_fr fr32,fr1 + fmovs fr36,fr1 + test_fr_fr fr36,fr1 + fmovs fr40,fr1 + test_fr_fr fr40,fr1 + fmovs fr44,fr1 + test_fr_fr fr44,fr1 + fmovs fr48,fr1 + test_fr_fr fr48,fr1 + fmovs fr52,fr1 + test_fr_fr fr52,fr1 + fmovs fr56,fr1 + test_fr_iimmed 0x7fc00000,fr1 + fmovs fr60,fr1 + test_fr_iimmed 0x7f800001,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fmsd.cgs b/sim/testsuite/sim/frv/fmsd.cgs new file mode 100644 index 00000000000..cd2efbd119e --- /dev/null +++ b/sim/testsuite/sim/frv/fmsd.cgs @@ -0,0 +1,146 @@ +# frv testcase for fmsd $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fmsd +fmsd: + fmsd fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmsd fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmsd fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmsd fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmsd fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + fmsd fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmsd fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmsd fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmsd fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmsd fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + fmsd fr28,fr0,fr2 + test_fr_fr fr2,fr0 + fmsd fr28,fr4,fr2 + test_fr_fr fr2,fr4 + fmsd fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + fmsd fr28,fr12,fr2 + test_fr_fr fr2,fr12 + fmsd fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmsd fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmsd fr28,fr24,fr2 + test_fr_fr fr2,fr24 + fmsd fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + fmsd fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr8 + fmsd fr28,fr36,fr2 + test_fr_fr fr2,fr36 + fmsd fr28,fr40,fr2 + test_fr_fr fr2,fr40 + fmsd fr28,fr44,fr2 + test_fr_fr fr2,fr44 + fmsd fr28,fr48,fr2 + test_fr_fr fr2,fr48 + fmsd fr28,fr52,fr2 + test_fr_fr fr2,fr52 + + fmsd fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + fmsd fr8,fr28,fr2 + test_fr_fr fr2,fr8 + + fmsd fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr8 + + pass diff --git a/sim/testsuite/sim/frv/fmss.cgs b/sim/testsuite/sim/frv/fmss.cgs new file mode 100644 index 00000000000..5c0a6459c32 --- /dev/null +++ b/sim/testsuite/sim/frv/fmss.cgs @@ -0,0 +1,146 @@ +# frv testcase for fmss $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fmss +fmss: + fmss fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmss fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmss fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmss fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmss fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + fmss fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmss fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmss fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmss fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmss fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + fmss fr28,fr0,fr2 + test_fr_fr fr2,fr0 + fmss fr28,fr4,fr2 + test_fr_fr fr2,fr4 + fmss fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + fmss fr28,fr12,fr2 + test_fr_fr fr2,fr12 + fmss fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmss fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmss fr28,fr24,fr2 + test_fr_fr fr2,fr24 + fmss fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + fmss fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr8 + fmss fr28,fr36,fr2 + test_fr_fr fr2,fr36 + fmss fr28,fr40,fr2 + test_fr_fr fr2,fr40 + fmss fr28,fr44,fr2 + test_fr_fr fr2,fr44 + fmss fr28,fr48,fr2 + test_fr_fr fr2,fr48 + fmss fr28,fr52,fr2 + test_fr_fr fr2,fr52 + + fmss fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + fmss fr8,fr28,fr2 + test_fr_fr fr2,fr8 + + fmss fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr8 + + pass diff --git a/sim/testsuite/sim/frv/fmsubd.cgs b/sim/testsuite/sim/frv/fmsubd.cgs new file mode 100644 index 00000000000..6b4c943c1bb --- /dev/null +++ b/sim/testsuite/sim/frv/fmsubd.cgs @@ -0,0 +1,144 @@ +# frv testcase for fmsubd $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fmsubd +fmsubd: + set_dfr_dfr fr16,fr2 + fmsubd fr16,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fmsubd fr20,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr0,fr2 + test_dfr_dfr fr2,fr0 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr4,fr2 + test_dfr_dfr fr2,fr4 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr8,fr2 + test_dfr_dfr fr2,fr8 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr12,fr2 + test_dfr_dfr fr2,fr12 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr24,fr2 + test_dfr_dfr fr2,fr24 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr28,fr2 + test_dfr_dfr fr2,fr28 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr32,fr2 + test_dfr_dfr fr2,fr32 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr36,fr2 + test_dfr_dfr fr2,fr36 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr40,fr2 + test_dfr_dfr fr2,fr40 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr44,fr2 + test_dfr_dfr fr2,fr44 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr48,fr2 + test_dfr_dfr fr2,fr48 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr52,fr2 + test_dfr_dfr fr2,fr52 + + set_dfr_dfr fr32,fr2 + fmsubd fr8,fr8,fr2 + test_dfr_dfr fr2,fr8 + set_dfr_dfr fr36,fr2 + fmsubd fr36,fr36,fr2 + test_dfr_dfr fr2,fr40 + + fmsubd fr32,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + pass diff --git a/sim/testsuite/sim/frv/fmsubs.cgs b/sim/testsuite/sim/frv/fmsubs.cgs new file mode 100644 index 00000000000..14a5bb355a3 --- /dev/null +++ b/sim/testsuite/sim/frv/fmsubs.cgs @@ -0,0 +1,144 @@ +# frv testcase for fmsubs $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fmsubs +fmsubs: + set_fr_fr fr16,fr1 + fmsubs fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fmsubs fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + fmsubs fr28,fr0,fr1 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + fmsubs fr28,fr4,fr1 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + fmsubs fr28,fr8,fr1 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + fmsubs fr28,fr12,fr1 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + fmsubs fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + fmsubs fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + fmsubs fr28,fr24,fr1 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + fmsubs fr28,fr28,fr1 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + fmsubs fr28,fr32,fr1 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + fmsubs fr28,fr36,fr1 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + fmsubs fr28,fr40,fr1 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + fmsubs fr28,fr44,fr1 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + fmsubs fr28,fr48,fr1 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + fmsubs fr28,fr52,fr1 + test_fr_fr fr1,fr52 + + set_fr_fr fr32,fr1 + fmsubs fr8,fr8,fr1 + test_fr_fr fr1,fr8 + set_fr_fr fr36,fr1 + fmsubs fr36,fr36,fr1 + test_fr_fr fr1,fr40 + + fmsubs fr32,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + pass diff --git a/sim/testsuite/sim/frv/fmuld.cgs b/sim/testsuite/sim/frv/fmuld.cgs new file mode 100644 index 00000000000..e06ca07675a --- /dev/null +++ b/sim/testsuite/sim/frv/fmuld.cgs @@ -0,0 +1,126 @@ +# frv testcase for fmuld $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fmuld +fmuld: + fmuld fr16,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fmuld fr20,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fmuld fr28,fr0,fr2 + test_dfr_dfr fr2,fr0 + fmuld fr28,fr4,fr2 + test_dfr_dfr fr2,fr4 + fmuld fr28,fr8,fr2 + test_dfr_dfr fr2,fr8 + fmuld fr28,fr12,fr2 + test_dfr_dfr fr2,fr12 + fmuld fr28,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr28,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr28,fr24,fr2 + test_dfr_dfr fr2,fr24 + fmuld fr28,fr28,fr2 + test_dfr_dfr fr2,fr28 + fmuld fr28,fr32,fr2 + test_dfr_dfr fr2,fr32 + fmuld fr28,fr36,fr2 + test_dfr_dfr fr2,fr36 + fmuld fr28,fr40,fr2 + test_dfr_dfr fr2,fr40 + fmuld fr28,fr44,fr2 + test_dfr_dfr fr2,fr44 + fmuld fr28,fr48,fr2 + test_dfr_dfr fr2,fr48 + fmuld fr28,fr52,fr2 + test_dfr_dfr fr2,fr52 + + fmuld fr28,fr8,fr2 + test_dfr_dfr fr2,fr8 + fmuld fr8,fr28,fr2 + test_dfr_dfr fr2,fr8 + + fmuld fr32,fr36,fr2 + test_dfr_dfr fr2,fr40 + + pass diff --git a/sim/testsuite/sim/frv/fmuls.cgs b/sim/testsuite/sim/frv/fmuls.cgs new file mode 100644 index 00000000000..2d21eccc114 --- /dev/null +++ b/sim/testsuite/sim/frv/fmuls.cgs @@ -0,0 +1,125 @@ +# frv testcase for fmuls $GRi,$GRj,$GRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fmuls +fmuls: + fmuls fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fmuls fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fmuls fr28,fr0,fr1 + test_fr_fr fr1,fr0 + fmuls fr28,fr4,fr1 + test_fr_fr fr1,fr4 + fmuls fr28,fr8,fr1 + test_fr_fr fr1,fr8 + fmuls fr28,fr12,fr1 + test_fr_fr fr1,fr12 + fmuls fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr28,fr24,fr1 + test_fr_fr fr1,fr24 + fmuls fr28,fr28,fr1 + test_fr_fr fr1,fr28 + fmuls fr28,fr32,fr1 + test_fr_fr fr1,fr32 + fmuls fr28,fr36,fr1 + test_fr_fr fr1,fr36 + fmuls fr28,fr40,fr1 + test_fr_fr fr1,fr40 + fmuls fr28,fr44,fr1 + test_fr_fr fr1,fr44 + fmuls fr28,fr48,fr1 + test_fr_fr fr1,fr48 + fmuls fr28,fr52,fr1 + test_fr_fr fr1,fr52 + + fmuls fr28,fr8,fr1 + test_fr_fr fr1,fr8 + fmuls fr8,fr28,fr1 + test_fr_fr fr1,fr8 + + fmuls fr32,fr36,fr1 + test_fr_fr fr1,fr40 + + pass diff --git a/sim/testsuite/sim/frv/fnegd.cgs b/sim/testsuite/sim/frv/fnegd.cgs new file mode 100644 index 00000000000..c18721b8e72 --- /dev/null +++ b/sim/testsuite/sim/frv/fnegd.cgs @@ -0,0 +1,26 @@ +# frv testcase for fnegd $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fnegd +fnegd: + fnegd fr0,fr2 + test_dfr_dfr fr2,fr52 + fnegd fr8,fr2 + test_dfr_dfr fr2,fr28 + fnegd fr12,fr2 + test_dfr_dfr fr2,fr24 + fnegd fr24,fr2 + test_dfr_dfr fr2,fr12 + fnegd fr28,fr2 + test_dfr_dfr fr2,fr8 + fnegd fr52,fr2 + test_dfr_dfr fr2,fr0 + + pass diff --git a/sim/testsuite/sim/frv/fnegs.cgs b/sim/testsuite/sim/frv/fnegs.cgs new file mode 100644 index 00000000000..645a9fc23f7 --- /dev/null +++ b/sim/testsuite/sim/frv/fnegs.cgs @@ -0,0 +1,25 @@ +# frv testcase for fnegs $FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fnegs +fnegs: + fnegs fr0,fr1 + test_fr_fr fr1,fr52 + fnegs fr8,fr1 + test_fr_fr fr1,fr28 + fnegs fr12,fr1 + test_fr_fr fr1,fr24 + fnegs fr24,fr1 + test_fr_fr fr1,fr12 + fnegs fr28,fr1 + test_fr_fr fr1,fr8 + fnegs fr52,fr1 + test_fr_fr fr1,fr0 + + pass diff --git a/sim/testsuite/sim/frv/fnop.cgs b/sim/testsuite/sim/frv/fnop.cgs new file mode 100644 index 00000000000..187bc392c38 --- /dev/null +++ b/sim/testsuite/sim/frv/fnop.cgs @@ -0,0 +1,12 @@ +# frv testcase for fnop +# mach: fr500 frv + + .include "testutils.inc" + + start + + .global fnop +fnop: + fnop + + pass diff --git a/sim/testsuite/sim/frv/fr400/allinsn.exp b/sim/testsuite/sim/frv/fr400/allinsn.exp new file mode 100644 index 00000000000..8f8b7c9d2f3 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/allinsn.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "fr400" + set cpu_option -mcpu + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/frv/fr400/csdiv.cgs b/sim/testsuite/sim/frv/fr400/csdiv.cgs new file mode 100644 index 00000000000..9fa6d8c6af9 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/csdiv.cgs @@ -0,0 +1,187 @@ +# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global csdiv +csdiv: + set_spr_immed 0x1b1b,cccr + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e1: csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e2: csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed 2,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/fr400/maveh.cgs b/sim/testsuite/sim/frv/fr400/maveh.cgs new file mode 100644 index 00000000000..445e121daf6 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/maveh.cgs @@ -0,0 +1,319 @@ +# frv testcase for maveh $FRi,$FRj,$FRj on fr400 machines +# mach: all + + .include "../testutils.inc" + + start + + .global maveh +maveh: + ; Test Rounding toward positive infinity via RDAV + or_spr_immed 0x20000000,msr0 + and_spr_immed 0xefffffff,msr0 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0002,0x0001,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0xffff,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef57,0xdf78,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf78,0xef57,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a3,0x33c5,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x091a,0x2b3c,fr12 + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x4000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + ; Test Rounding toward nearest via RD + or_spr_immed 0x10000000,msr0 + and_spr_immed 0x3fffffff,msr0 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0002,0x0001,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xffff,0xfffe,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef56,0xdf77,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf77,0xef56,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a3,0x33c5,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x091a,0x2b3c,fr12 + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x4000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xbfff,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xbfff,0xbfff,fr12 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + ; Test Rounding toward zero via RD + or_spr_immed 0x50000000,msr0 + and_spr_immed 0x7fffffff,msr0 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0001,0x0000,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0xffff,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef57,0xdf78,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf78,0xef57,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a2,0x33c4,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0919,0x2b3b,fr12 + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x3fff,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + ; Test Rounding toward positive infinity via RD + or_spr_immed 0x90000000,msr0 + and_spr_immed 0xbfffffff,msr0 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0002,0x0001,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0xffff,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef57,0xdf78,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf78,0xef57,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a3,0x33c5,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x091a,0x2b3c,fr12 + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x4000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + ; Test Rounding toward negative infinity via RD + or_spr_immed 0xd0000000,msr0 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0001,0x0000,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xffff,0xfffe,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef56,0xdf77,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf77,0xef56,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a2,0x33c4,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0919,0x2b3b,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x3fff,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xbfff,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xbfff,0xbfff,fr12 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + pass diff --git a/sim/testsuite/sim/frv/fr400/mclracc.cgs b/sim/testsuite/sim/frv/fr400/mclracc.cgs new file mode 100644 index 00000000000..02975446be4 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/mclracc.cgs @@ -0,0 +1,79 @@ +# frv testcase for mclracc $ACC40k,$A +# mach: all + + .include "../testutils.inc" + + start + + .global mclracc +mclracc: + set_accg_immed 0xff,accg0 + set_acc_immed -1,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed -1,acc1 + set_accg_immed 0xff,accg2 + set_acc_immed -1,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed -1,acc3 + + mclracc acc8,0 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -1,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -1,acc3 + + mclracc acc8,1 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -1,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -1,acc3 + + mclracc acc2,0 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -1,acc3 + + mclracc acc3,1 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + mclracc acc0,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + mclracc acc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + pass diff --git a/sim/testsuite/sim/frv/fr400/mhdseth.cgs b/sim/testsuite/sim/frv/fr400/mhdseth.cgs new file mode 100644 index 00000000000..b99c996f78b --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/mhdseth.cgs @@ -0,0 +1,22 @@ +# frv testcase for mhdseth $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhdseth +mhdseth: + set_fr_immed 0,fr1 + mhdseth 0,fr1 + test_fr_iimmed 0,fr1 + mhdseth 1,fr1 + test_fr_iimmed 0x08000800,fr1 + mhdseth 0xf,fr1 + test_fr_iimmed 0x78007800,fr1 + mhdseth -16,fr1 + test_fr_iimmed 0x80008000,fr1 + mhdseth -1,fr1 + test_fr_iimmed 0xf800f800,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fr400/mhdsets.cgs b/sim/testsuite/sim/frv/fr400/mhdsets.cgs new file mode 100644 index 00000000000..c495cb7130c --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/mhdsets.cgs @@ -0,0 +1,20 @@ +# frv testcase for mhdsets $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhdsets +mhdsets: + set_fr_immed 0,fr1 + mhdsets 0,fr1 + test_fr_iimmed 0,fr1 + mhdsets 1,fr1 + test_fr_iimmed 0x00010001,fr1 + mhdsets 0x7ff,fr1 + test_fr_iimmed 0x07ff07ff,fr1 + mhdsets -2048,fr1 + test_fr_iimmed 0xf800f800,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fr400/mhsethih.cgs b/sim/testsuite/sim/frv/fr400/mhsethih.cgs new file mode 100644 index 00000000000..fed9d2335e7 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/mhsethih.cgs @@ -0,0 +1,22 @@ +# frv testcase for mhsethih $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhsethih +mhsethih: + set_fr_immed 0,fr1 + mhsethih 0,fr1 + test_fr_iimmed 0,fr1 + mhsethih 1,fr1 + test_fr_iimmed 0x08000000,fr1 + mhsethih 0xf,fr1 + test_fr_iimmed 0x78000000,fr1 + mhsethih -16,fr1 + test_fr_iimmed 0x80000000,fr1 + mhsethih -1,fr1 + test_fr_iimmed 0xf8000000,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fr400/mhsethis.cgs b/sim/testsuite/sim/frv/fr400/mhsethis.cgs new file mode 100644 index 00000000000..ade9102a5e3 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/mhsethis.cgs @@ -0,0 +1,25 @@ +# frv testcase for mhsethis $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhsethis +mhsethis: + set_fr_immed 0,fr1 + mhsethis 0,fr1 + test_fr_iimmed 0,fr1 + mhsethis 1,fr1 + test_fr_iimmed 0x00010000,fr1 + mhsethis 0x7ff,fr1 + test_fr_iimmed 0x07ff0000,fr1 + mhsethis -2048,fr1 + test_fr_iimmed 0xf8000000,fr1 + + ; Try parallel set of hi and lo at the same time + mhsethis.p 1,fr1 + mhsetlos 2,fr1 + test_fr_iimmed 0x00010002,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fr400/mhsetloh.cgs b/sim/testsuite/sim/frv/fr400/mhsetloh.cgs new file mode 100644 index 00000000000..1dedb836eca --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/mhsetloh.cgs @@ -0,0 +1,27 @@ +# frv testcase for mhsetloh $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhsetloh +mhsetloh: + set_fr_immed 0,fr1 + mhsetloh 0,fr1 + test_fr_iimmed 0,fr1 + mhsetloh 1,fr1 + test_fr_iimmed 0x0000800,fr1 + mhsetloh 0xf,fr1 + test_fr_iimmed 0x00007800,fr1 + mhsetloh -16,fr1 + test_fr_iimmed 0x00008000,fr1 + mhsetloh -1,fr1 + test_fr_iimmed 0x0000f800,fr1 + + ; Try parallel write to both hi and lo + mhsetloh.p 1,fr1 + mhsethih 0xf,fr1 + test_fr_iimmed 0x78000800,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fr400/mhsetlos.cgs b/sim/testsuite/sim/frv/fr400/mhsetlos.cgs new file mode 100644 index 00000000000..8e8839ab6e9 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/mhsetlos.cgs @@ -0,0 +1,25 @@ +# frv testcase for mhsetlos $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhsetlos +mhsetlos: + set_fr_immed 0,fr1 + mhsetlos 0,fr1 + test_fr_iimmed 0,fr1 + mhsetlos 1,fr1 + test_fr_iimmed 0x00000001,fr1 + mhsetlos 0x7ff,fr1 + test_fr_iimmed 0x000007ff,fr1 + mhsetlos -2048,fr1 + test_fr_iimmed 0x0000f800,fr1 + + ; Try parallel set of hi and lo at the same time + mhsethis.p 1,fr1 + mhsetlos 2,fr1 + test_fr_iimmed 0x00010002,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fr400/sdiv.cgs b/sim/testsuite/sim/frv/fr400/sdiv.cgs new file mode 100644 index 00000000000..b9c03cfeea3 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/sdiv.cgs @@ -0,0 +1,71 @@ +# frv testcase for sdiv $GRi,$GRj,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global sdiv +sdiv: + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + sdiv gr1,gr3,gr2 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + sdiv gr1,gr3,gr2 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + sdiv gr1,gr3,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e1: sdiv gr1,gr3,gr2 ; overflow + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2; gr2 updated + + ; divide by zero + set_spr_addr ok2,lr + set_gr_immed 0xdeadbeef,gr2 +e2: sdiv gr1,gr0,gr2 ; divide by zero + test_gr_immed 2,gr15 ; handler called + test_gr_immed 0xdeadbeef,gr2 ; gr2 not updated. + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail + +ok2: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/fr400/sdivi.cgs b/sim/testsuite/sim/frv/fr400/sdivi.cgs new file mode 100644 index 00000000000..fda573e5842 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/sdivi.cgs @@ -0,0 +1,70 @@ +# frv testcase for sdivi $GRi,$s12,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global sdivi +sdivi: + ; simple division 12 / 3 + set_gr_immed 12,gr1 + sdivi gr1,3,gr2 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0xfedc,0xba98,gr1 + sdivi gr1,0x7ff,gr2 + test_gr_limmed 0xffff,0xdb93,gr2 + + ; Random negative example + set_gr_limmed 0xfedc,0xba98,gr1 + sdivi gr1,-2048,gr2 + test_gr_immed 0x2468,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_limmed 0x8000,0x0000,gr1 + sdivi gr1,-1,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_limmed 0x8000,0x0000,gr1 +e1: sdivi gr1,-1,gr2 + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; divide by zero + set_spr_addr ok2,lr +e2: sdivi gr1,0,gr2 ; divide by zero + test_gr_immed 2,gr15 + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail + +ok2: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/fr400/udiv.cgs b/sim/testsuite/sim/frv/fr400/udiv.cgs new file mode 100644 index 00000000000..25ae7b3bf6b --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/udiv.cgs @@ -0,0 +1,46 @@ +# frv testcase for udiv $GRi,$GRj,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global udiv +udiv: + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + udiv gr3,gr2,gr3 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + + ; example 1 from udiv in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + udiv gr3,gr2,gr3 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr +e1: udiv gr1,gr0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/fr400/udivi.cgs b/sim/testsuite/sim/frv/fr400/udivi.cgs new file mode 100644 index 00000000000..242952b90d4 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/udivi.cgs @@ -0,0 +1,47 @@ +# frv testcase for udivi $GRi,$s12,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global udivi +udivi: + ; simple division 12 / 3 + set_gr_immed 0x0000000c,gr3 + udivi gr3,3,gr3 + test_gr_immed 0x00000004,gr3 + + ; random example + set_gr_limmed 0xfedc,0xba98,gr3 + udivi gr3,0x7ff,gr3 + test_gr_limmed 0x001f,0xdf93,gr3 + + ; random example + set_gr_limmed 0xffff,0xffff,gr3 + udivi gr3,-2048,gr3 + test_gr_immed 1,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr +e1: udivi gr1,0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/fr500/allinsn.exp b/sim/testsuite/sim/frv/fr500/allinsn.exp new file mode 100644 index 00000000000..a5953fb1a28 --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/allinsn.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "frv fr500" + set cpu_option -mcpu + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs b/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs new file mode 100644 index 00000000000..42c4ee3d92d --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs @@ -0,0 +1,444 @@ +# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmqaddhss +cmqaddhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc4,1 + cmqaddhss fr12,fr12,fr16,cc4,1 + test_fr_limmed 0x0002,0x0002,fr14 + test_fr_limmed 0xfffe,0xfffe,fr15 + test_fr_limmed 0x7fff,0x0000,fr16 + test_fr_limmed 0x0000,0x8000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc5,0 + cmqaddhss fr12,fr12,fr16,cc5,0 + test_fr_limmed 0x0002,0x0002,fr14 + test_fr_limmed 0xfffe,0xfffe,fr15 + test_fr_limmed 0x7fff,0x0000,fr16 + test_fr_limmed 0x0000,0x8000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc4,0 + cmqaddhss fr12,fr12,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc5,1 + cmqaddhss fr12,fr12,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc6,1 + cmqaddhss fr12,fr12,fr16,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set +; + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc7,1 + cmqaddhss fr12,fr12,fr16,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs b/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs new file mode 100644 index 00000000000..325f5320aba --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs @@ -0,0 +1,360 @@ +# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmqaddhus +cmqaddhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x8000,0x7fff,fr14 + test_fr_limmed 0xffff,0xffff,fr15 + test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc4,1 + cmqaddhus fr12,fr12,fr16,cc4,1 + test_fr_limmed 0x0004,0x0002,fr14 + test_fr_limmed 0x0002,0x0002,fr15 + test_fr_limmed 0xffff,0xffff,fr16 + test_fr_limmed 0xffff,0xffff,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x8000,0x7fff,fr14 + test_fr_limmed 0xffff,0xffff,fr15 + test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc5,0 + cmqaddhus fr12,fr12,fr16,cc5,0 + test_fr_limmed 0x0004,0x0002,fr14 + test_fr_limmed 0x0002,0x0002,fr15 + test_fr_limmed 0xffff,0xffff,fr16 + test_fr_limmed 0xffff,0xffff,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc4,0 + cmqaddhus fr12,fr12,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc5,1 + cmqaddhus fr12,fr12,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc6,0 + cmqaddhus fr12,fr12,fr16,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc7,0 + cmqaddhus fr12,fr12,fr16,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs b/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs new file mode 100644 index 00000000000..3cfa2ef0ace --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs @@ -0,0 +1,448 @@ +# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global msubhss +msubhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0x4111,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x4111,0xdead,fr14 + test_fr_limmed 0x0123,0x4567,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x1235,0x5679,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc4,1 + cmqsubhss fr12,fr10,fr16,cc4,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x8000,0x8000,fr16 + test_fr_limmed 0x8001,0x8001,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0x4111,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x4111,0xdead,fr14 + test_fr_limmed 0x0123,0x4567,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x1235,0x5679,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc5,0 + cmqsubhss fr12,fr10,fr16,cc5,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x8000,0x8000,fr16 + test_fr_limmed 0x8001,0x8001,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc4,0 + cmqsubhss fr12,fr10,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc5,1 + cmqsubhss fr12,fr10,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc6,1 + cmqsubhss fr12,fr10,fr16,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc7,1 + cmqsubhss fr12,fr10,fr16,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs b/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs new file mode 100644 index 00000000000..646565dba83 --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs @@ -0,0 +1,370 @@ +# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmqsubhus +cmqsubhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0123,0x4567,fr14 + test_fr_limmed 0x7ffc,0x7ffd,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc4,1 + cmqsubhus fr10,fr12,fr16,cc4,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x0001,0x0000,fr16 + test_fr_limmed 0x0000,0x0000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x1,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0123,0x4567,fr14 + test_fr_limmed 0x7ffc,0x7ffd,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc5,0 + cmqsubhus fr10,fr12,fr16,cc5,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x0001,0x0000,fr16 + test_fr_limmed 0x0000,0x0000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x1,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc4,0 + cmqsubhus fr10,fr12,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_fr_limmed 0x4444,0x4444,fr17 + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc5,1 + cmqsubhus fr10,fr12,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_fr_limmed 0x4444,0x4444,fr17 + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc6,0 + cmqsubhus fr10,fr12,fr16,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_fr_limmed 0x4444,0x4444,fr17 +; + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc7,0 + cmqsubhus fr10,fr12,fr16,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_fr_limmed 0x4444,0x4444,fr17 + + pass diff --git a/sim/testsuite/sim/frv/fr500/dcpl.cgs b/sim/testsuite/sim/frv/fr500/dcpl.cgs new file mode 100644 index 00000000000..30ed7ff083c --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/dcpl.cgs @@ -0,0 +1,65 @@ +# FRV testcase for dcpl GRi,GRj,lock +# mach: all + + .include "../testutils.inc" + + start + + .global dcpl +dcpl: + or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode + + ; preload and lock all the lines in set 0 of the data cache + set_gr_immed 0x70000,gr10 + dcpl gr10,gr0,1 + set_mem_immed 0x11111111,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 1,gr11 + dcpl gr10,gr11,1 + set_mem_immed 0x22222222,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 63,gr11 + dcpl gr10,gr11,1 + set_mem_immed 0x33333333,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 64,gr11 + dcpl gr10,gr11,1 + set_mem_immed 0x44444444,gr10 + test_mem_immed 0x44444444,gr10 + + ; Now write to another address which should be in the same set + ; the write should go through to memory, since all the lines in the + ; set are locked + inc_gr_immed 0x1000,gr10 + set_mem_immed 0xdeadbeef,gr10 + test_mem_immed 0xdeadbeef,gr10 + + ; Invalidate the data cache. Only the last value stored should have made + ; it through to memory + set_gr_immed 0x70000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0xdeadbeef,gr10 + + pass diff --git a/sim/testsuite/sim/frv/fr500/dcul.cgs b/sim/testsuite/sim/frv/fr500/dcul.cgs new file mode 100644 index 00000000000..4fd46f291c7 --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/dcul.cgs @@ -0,0 +1,118 @@ +# FRV testcase for dcul GRi +# mach: all + + .include "../testutils.inc" + + start + + .global dcul +dcul: + or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode + + ; preload and lock all the lines in set 0 of the data cache + set_gr_immed 0x70000,gr10 + lock_data_cache gr10 + set_mem_immed 0x11111111,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 1,gr11 + lock_data_cache gr10 + set_mem_immed 0x22222222,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 63,gr11 + lock_data_cache gr10 + set_mem_immed 0x33333333,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 64,gr11 + lock_data_cache gr10 + set_mem_immed 0x44444444,gr10 + test_mem_immed 0x44444444,gr10 + + ; Now write to another address which should be in the same set + ; the write should go through to memory, since all the lines in the + ; set are locked + inc_gr_immed 0x1000,gr10 + set_mem_immed 0xdeadbeef,gr10 + test_mem_immed 0xdeadbeef,gr10 + + ; Invalidate the data cache. Only the last value stored should have made + ; it through to memory + set_gr_immed 0x70000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0xdeadbeef,gr10 + + ; Now preload load and lock all the lines in set 0 of the data cache + ; again + set_gr_immed 0x70000,gr10 + lock_data_cache gr10 + set_mem_immed 0x11111111,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 1,gr11 + lock_data_cache gr10 + set_mem_immed 0x22222222,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 63,gr11 + lock_data_cache gr10 + set_mem_immed 0x33333333,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 64,gr11 + lock_data_cache gr10 + set_mem_immed 0x44444444,gr10 + test_mem_immed 0x44444444,gr10 + + ; unlock one line + set_gr_immed 0x72000,gr10 + dcul gr10 + + ; Now write to another address which should be in the same set. + set_gr_immed 0x75000,gr10 + set_mem_immed 0xbeefdead,gr10 + + ; All of the stored values should be retrievable + + set_gr_immed 0x70000,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x1000,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x1000,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x1000,gr10 + test_mem_immed 0x44444444,gr10 + + inc_gr_immed 0x1000,gr10 + test_mem_immed 0xdeadbeef,gr10 + + inc_gr_immed 0x1000,gr10 + test_mem_immed 0xbeefdead,gr10 + + pass diff --git a/sim/testsuite/sim/frv/fr500/mclracc.cgs b/sim/testsuite/sim/frv/fr500/mclracc.cgs new file mode 100644 index 00000000000..c274d737f7e --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/mclracc.cgs @@ -0,0 +1,79 @@ +# frv testcase for mclracc $ACC40k,$A +# mach: fr500 + + .include "../testutils.inc" + + start + + .global mclracc +mclracc: + set_accg_immed 0xff,accg0 + set_acc_immed -1,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed -1,acc1 + set_accg_immed 0xff,accg3 + set_acc_immed -1,acc3 + set_accg_immed 0xff,accg7 + set_acc_immed -1,acc7 + + mclracc acc8,0 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0xff,accg3 + test_acc_immed -1,acc3 + test_accg_immed 0xff,accg7 + test_acc_immed -1,acc7 + + mclracc acc8,1 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0xff,accg3 + test_acc_immed -1,acc3 + test_accg_immed 0xff,accg7 + test_acc_immed -1,acc7 + + mclracc acc3,0 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0xff,accg7 + test_acc_immed -1,acc7 + + mclracc acc7,1 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0,accg7 + test_acc_immed 0,acc7 + + mclracc acc0,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0,accg7 + test_acc_immed 0,acc7 + + mclracc acc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0,accg7 + test_acc_immed 0,acc7 + + pass diff --git a/sim/testsuite/sim/frv/fr500/mqaddhss.cgs b/sim/testsuite/sim/frv/fr500/mqaddhss.cgs new file mode 100644 index 00000000000..23fb95a86a5 --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/mqaddhss.cgs @@ -0,0 +1,79 @@ +# frv testcase for mqaddhss $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global mqaddhss +mqaddhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + mqaddhss.p fr10,fr10,fr14 + mqaddhss fr12,fr12,fr16 + test_fr_limmed 0x0002,0x0002,fr14 + test_fr_limmed 0xfffe,0xfffe,fr15 + test_fr_limmed 0x7fff,0x0000,fr16 + test_fr_limmed 0x0000,0x8000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr500/mqaddhus.cgs b/sim/testsuite/sim/frv/fr500/mqaddhus.cgs new file mode 100644 index 00000000000..ff08bf5238d --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/mqaddhus.cgs @@ -0,0 +1,65 @@ +# frv testcase for mqaddhus $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global mqaddhus +mqaddhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + mqaddhus fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + mqaddhus fr10,fr12,fr14 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + mqaddhus fr10,fr12,fr14 + test_fr_limmed 0x8000,0x7fff,fr14 + test_fr_limmed 0xffff,0xffff,fr15 + test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + mqaddhus.p fr10,fr10,fr14 + mqaddhus fr12,fr12,fr16 + test_fr_limmed 0x0004,0x0002,fr14 + test_fr_limmed 0x0002,0x0002,fr15 + test_fr_limmed 0xffff,0xffff,fr16 + test_fr_limmed 0xffff,0xffff,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr500/mqsubhss.cgs b/sim/testsuite/sim/frv/fr500/mqsubhss.cgs new file mode 100644 index 00000000000..a84f1faef24 --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/mqsubhss.cgs @@ -0,0 +1,79 @@ +# frv testcase for mqsubhss $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global msubhss +msubhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0x4111,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x4111,0xdead,fr14 + test_fr_limmed 0x0123,0x4567,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x1235,0x5679,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + mqsubhss.p fr10,fr10,fr14 + mqsubhss fr12,fr10,fr16 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x8000,0x8000,fr16 + test_fr_limmed 0x8001,0x8001,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr500/mqsubhus.cgs b/sim/testsuite/sim/frv/fr500/mqsubhus.cgs new file mode 100644 index 00000000000..06dc01f496c --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/mqsubhus.cgs @@ -0,0 +1,66 @@ +# frv testcase for msubhus $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global msubhus +msubhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + mqsubhus fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqsubhus fr10,fr12,fr14 + test_fr_limmed 0x0123,0x4567,fr14 + test_fr_limmed 0x7ffc,0x7ffd,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqsubhus fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + mqsubhus.p fr10,fr10,fr14 + mqsubhus fr10,fr12,fr16 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x0001,0x0000,fr16 + test_fr_limmed 0x0000,0x0000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x1,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fsqrtd.cgs b/sim/testsuite/sim/frv/fsqrtd.cgs new file mode 100644 index 00000000000..a428b013b6e --- /dev/null +++ b/sim/testsuite/sim/frv/fsqrtd.cgs @@ -0,0 +1,22 @@ +# frv testcase for fsqrtd $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fsqrtd +fsqrtd: + fsqrtd fr44,fr2 ; 9.0 + test_dfr_dfr fr2,fr36 ; 3.0 + + set_fr_iimmed 0x4009,0x21fb,fr10 ; 3.141592654 + set_fr_iimmed 0x6000,0x0000,fr11 + fsqrtd fr10,fr10 + test_fr_iimmed 0x3ffc5bf8,fr10 ; 1.7724539 + test_fr_iimmed 0x9853a94d,fr11 + + pass diff --git a/sim/testsuite/sim/frv/fsqrts.cgs b/sim/testsuite/sim/frv/fsqrts.cgs new file mode 100644 index 00000000000..063156d105f --- /dev/null +++ b/sim/testsuite/sim/frv/fsqrts.cgs @@ -0,0 +1,19 @@ +# frv testcase for fsqrts $FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fsqrts +fsqrts: + fsqrts fr44,fr1 ; 9.0 + test_fr_fr fr1,fr36 ; 3.0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + fsqrts fr10,fr10 + test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 + + pass diff --git a/sim/testsuite/sim/frv/fstoi.cgs b/sim/testsuite/sim/frv/fstoi.cgs new file mode 100644 index 00000000000..56c60208948 --- /dev/null +++ b/sim/testsuite/sim/frv/fstoi.cgs @@ -0,0 +1,24 @@ +# frv testcase for fstoi $FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fstoi +fstoi: + fstoi fr16,fr1 + test_fr_iimmed 0,fr1 + fstoi fr20,fr1 + test_fr_iimmed 0,fr1 + + fstoi fr32,fr1 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xce05,0x4904,fr1 + fstoi fr1,fr1 + test_fr_iimmed 0xdeadbf00,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fsubd.cgs b/sim/testsuite/sim/frv/fsubd.cgs new file mode 100644 index 00000000000..fed2d04aaf7 --- /dev/null +++ b/sim/testsuite/sim/frv/fsubd.cgs @@ -0,0 +1,83 @@ +# frv testcase for fsubd $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fsubd +fsubd: + fsubd fr0,fr16,fr2 + test_dfr_dfr fr2,fr0 + fsubd fr4,fr16,fr2 + test_dfr_dfr fr2,fr4 + fsubd fr8,fr16,fr2 + test_dfr_dfr fr2,fr8 + fsubd fr12,fr16,fr2 + test_dfr_dfr fr2,fr12 + fsubd fr16,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fsubd fr20,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fsubd fr24,fr16,fr2 + test_dfr_dfr fr2,fr24 + fsubd fr28,fr16,fr2 + test_dfr_dfr fr2,fr28 + fsubd fr32,fr16,fr2 + test_dfr_dfr fr2,fr32 + fsubd fr36,fr16,fr2 + test_dfr_dfr fr2,fr36 + fsubd fr40,fr16,fr2 + test_dfr_dfr fr2,fr40 + fsubd fr44,fr16,fr2 + test_dfr_dfr fr2,fr44 + fsubd fr48,fr16,fr2 + test_dfr_dfr fr2,fr48 + fsubd fr52,fr16,fr2 + test_dfr_dfr fr2,fr52 + + fsubd fr0,fr20,fr2 + test_dfr_dfr fr2,fr0 + fsubd fr4,fr20,fr2 + test_dfr_dfr fr2,fr4 + fsubd fr8,fr20,fr2 + test_dfr_dfr fr2,fr8 + fsubd fr12,fr20,fr2 + test_dfr_dfr fr2,fr12 + fsubd fr16,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fsubd fr20,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fsubd fr24,fr20,fr2 + test_dfr_dfr fr2,fr24 + fsubd fr28,fr20,fr2 + test_dfr_dfr fr2,fr28 + fsubd fr32,fr20,fr2 + test_dfr_dfr fr2,fr32 + fsubd fr36,fr20,fr2 + test_dfr_dfr fr2,fr36 + fsubd fr40,fr20,fr2 + test_dfr_dfr fr2,fr40 + fsubd fr44,fr20,fr2 + test_dfr_dfr fr2,fr44 + fsubd fr48,fr20,fr2 + test_dfr_dfr fr2,fr48 + fsubd fr52,fr20,fr2 + test_dfr_dfr fr2,fr52 + + fsubd fr32,fr36,fr2 + test_dfr_dfr fr2,fr8 + + fsubd fr44,fr40,fr2 + test_dfr_dfr fr2,fr36 + + pass + + diff --git a/sim/testsuite/sim/frv/fsubs.cgs b/sim/testsuite/sim/frv/fsubs.cgs new file mode 100644 index 00000000000..ee054551977 --- /dev/null +++ b/sim/testsuite/sim/frv/fsubs.cgs @@ -0,0 +1,82 @@ +# frv testcase for fsubs $GRi,$GRj,$GRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fsubs +fsubs: + fsubs fr0,fr16,fr1 + test_fr_fr fr1,fr0 + fsubs fr4,fr16,fr1 + test_fr_fr fr1,fr4 + fsubs fr8,fr16,fr1 + test_fr_fr fr1,fr8 + fsubs fr12,fr16,fr1 + test_fr_fr fr1,fr12 + fsubs fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fsubs fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fsubs fr24,fr16,fr1 + test_fr_fr fr1,fr24 + fsubs fr28,fr16,fr1 + test_fr_fr fr1,fr28 + fsubs fr32,fr16,fr1 + test_fr_fr fr1,fr32 + fsubs fr36,fr16,fr1 + test_fr_fr fr1,fr36 + fsubs fr40,fr16,fr1 + test_fr_fr fr1,fr40 + fsubs fr44,fr16,fr1 + test_fr_fr fr1,fr44 + fsubs fr48,fr16,fr1 + test_fr_fr fr1,fr48 + fsubs fr52,fr16,fr1 + test_fr_fr fr1,fr52 + + fsubs fr0,fr20,fr1 + test_fr_fr fr1,fr0 + fsubs fr4,fr20,fr1 + test_fr_fr fr1,fr4 + fsubs fr8,fr20,fr1 + test_fr_fr fr1,fr8 + fsubs fr12,fr20,fr1 + test_fr_fr fr1,fr12 + fsubs fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fsubs fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fsubs fr24,fr20,fr1 + test_fr_fr fr1,fr24 + fsubs fr28,fr20,fr1 + test_fr_fr fr1,fr28 + fsubs fr32,fr20,fr1 + test_fr_fr fr1,fr32 + fsubs fr36,fr20,fr1 + test_fr_fr fr1,fr36 + fsubs fr40,fr20,fr1 + test_fr_fr fr1,fr40 + fsubs fr44,fr20,fr1 + test_fr_fr fr1,fr44 + fsubs fr48,fr20,fr1 + test_fr_fr fr1,fr48 + fsubs fr52,fr20,fr1 + test_fr_fr fr1,fr52 + + fsubs fr32,fr36,fr1 + test_fr_fr fr1,fr8 + + fsubs fr44,fr40,fr1 + test_fr_fr fr1,fr36 + + pass + + diff --git a/sim/testsuite/sim/frv/fteq.cgs b/sim/testsuite/sim/frv/fteq.cgs new file mode 100644 index 00000000000..020a88712ee --- /dev/null +++ b/sim/testsuite/sim/frv/fteq.cgs @@ -0,0 +1,101 @@ +# frv testcase for fteq $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global fteq +fteq: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x4 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x6 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x7 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftge.cgs b/sim/testsuite/sim/frv/ftge.cgs new file mode 100644 index 00000000000..eab7a061701 --- /dev/null +++ b/sim/testsuite/sim/frv/ftge.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftge $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftge +ftge: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftgt.cgs b/sim/testsuite/sim/frv/ftgt.cgs new file mode 100644 index 00000000000..9035fbc8773 --- /dev/null +++ b/sim/testsuite/sim/frv/ftgt.cgs @@ -0,0 +1,101 @@ +# frv testcase for ftgt $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftgt +ftgt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xd 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftieq.cgs b/sim/testsuite/sim/frv/ftieq.cgs new file mode 100644 index 00000000000..a5710ad10dc --- /dev/null +++ b/sim/testsuite/sim/frv/ftieq.cgs @@ -0,0 +1,100 @@ +# frv testcase for ftieq $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftieq +ftieq: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x4 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x6 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x7 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftige.cgs b/sim/testsuite/sim/frv/ftige.cgs new file mode 100644 index 00000000000..5b58ce0c390 --- /dev/null +++ b/sim/testsuite/sim/frv/ftige.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftige $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftige +ftige: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftigt.cgs b/sim/testsuite/sim/frv/ftigt.cgs new file mode 100644 index 00000000000..e31ead4cfe3 --- /dev/null +++ b/sim/testsuite/sim/frv/ftigt.cgs @@ -0,0 +1,100 @@ +# frv testcase for ftigt $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftigt +ftigt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xd 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftile.cgs b/sim/testsuite/sim/frv/ftile.cgs new file mode 100644 index 00000000000..d13eeee67de --- /dev/null +++ b/sim/testsuite/sim/frv/ftile.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftile $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftile +ftile: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftilg.cgs b/sim/testsuite/sim/frv/ftilg.cgs new file mode 100644 index 00000000000..26127d25aa7 --- /dev/null +++ b/sim/testsuite/sim/frv/ftilg.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftilg $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftilg +ftilg: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftilt.cgs b/sim/testsuite/sim/frv/ftilt.cgs new file mode 100644 index 00000000000..7a74d5b6c20 --- /dev/null +++ b/sim/testsuite/sim/frv/ftilt.cgs @@ -0,0 +1,100 @@ +# frv testcase for ftilt $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftilt +ftilt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xa 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xb 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftine.cgs b/sim/testsuite/sim/frv/ftine.cgs new file mode 100644 index 00000000000..89aa5a6302d --- /dev/null +++ b/sim/testsuite/sim/frv/ftine.cgs @@ -0,0 +1,112 @@ +# frv testcase for ftine $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftine +ftine: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftino.cgs b/sim/testsuite/sim/frv/ftino.cgs new file mode 100644 index 00000000000..b08a571a356 --- /dev/null +++ b/sim/testsuite/sim/frv/ftino.cgs @@ -0,0 +1,53 @@ +# frv testcase for ftino +# mach: all + + .include "testutils.inc" + + start + + .global ftinev +ftinev: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_gr_immed 0,gr7 + + set_fcc 0x0 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x1 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x2 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x3 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x4 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x5 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x6 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x7 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x8 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x9 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xa 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xb 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xc 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xd 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xe 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xf 0 + ftino ; should branch to tbr + (128 + 4)*16 + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftio.cgs b/sim/testsuite/sim/frv/ftio.cgs new file mode 100644 index 00000000000..083c17064f5 --- /dev/null +++ b/sim/testsuite/sim/frv/ftio.cgs @@ -0,0 +1,112 @@ +# frv testcase for ftio $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftio +ftio: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftira.cgs b/sim/testsuite/sim/frv/ftira.cgs new file mode 100644 index 00000000000..9382b2b84ae --- /dev/null +++ b/sim/testsuite/sim/frv/ftira.cgs @@ -0,0 +1,114 @@ +# frv testcase for ftira $GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftira +ftira: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_fcc 0x0 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass diff --git a/sim/testsuite/sim/frv/ftiu.cgs b/sim/testsuite/sim/frv/ftiu.cgs new file mode 100644 index 00000000000..adc40bead17 --- /dev/null +++ b/sim/testsuite/sim/frv/ftiu.cgs @@ -0,0 +1,100 @@ +# frv testcase for ftiu $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftiu +ftiu: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_fcc 0x6 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_fcc 0xa 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_fcc 0xe 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftiue.cgs b/sim/testsuite/sim/frv/ftiue.cgs new file mode 100644 index 00000000000..311143430cf --- /dev/null +++ b/sim/testsuite/sim/frv/ftiue.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftiue $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftiue +ftiue: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_fcc 0x6 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftiug.cgs b/sim/testsuite/sim/frv/ftiug.cgs new file mode 100644 index 00000000000..9e16f89480e --- /dev/null +++ b/sim/testsuite/sim/frv/ftiug.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftiug $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftiug +ftiug: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftiuge.cgs b/sim/testsuite/sim/frv/ftiuge.cgs new file mode 100644 index 00000000000..bda587e7879 --- /dev/null +++ b/sim/testsuite/sim/frv/ftiuge.cgs @@ -0,0 +1,112 @@ +# frv testcase for ftiuge $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftiuge +ftiuge: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftiul.cgs b/sim/testsuite/sim/frv/ftiul.cgs new file mode 100644 index 00000000000..ee5e2ba60aa --- /dev/null +++ b/sim/testsuite/sim/frv/ftiul.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftiul $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftiul +ftiul: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_fcc 0xa 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftle.cgs b/sim/testsuite/sim/frv/ftle.cgs new file mode 100644 index 00000000000..4ffa760577c --- /dev/null +++ b/sim/testsuite/sim/frv/ftle.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftle $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftle +ftle: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftlg.cgs b/sim/testsuite/sim/frv/ftlg.cgs new file mode 100644 index 00000000000..a72f5026d27 --- /dev/null +++ b/sim/testsuite/sim/frv/ftlg.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftlg $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftlg +ftlg: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftlt.cgs b/sim/testsuite/sim/frv/ftlt.cgs new file mode 100644 index 00000000000..c9343139d4a --- /dev/null +++ b/sim/testsuite/sim/frv/ftlt.cgs @@ -0,0 +1,101 @@ +# frv testcase for ftlt $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftlt +ftlt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xa 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xb 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftne.cgs b/sim/testsuite/sim/frv/ftne.cgs new file mode 100644 index 00000000000..03b9857eb99 --- /dev/null +++ b/sim/testsuite/sim/frv/ftne.cgs @@ -0,0 +1,113 @@ +# frv testcase for ftne $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftne +ftne: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftno.cgs b/sim/testsuite/sim/frv/ftno.cgs new file mode 100644 index 00000000000..bada522a6a8 --- /dev/null +++ b/sim/testsuite/sim/frv/ftno.cgs @@ -0,0 +1,54 @@ +# frv testcase for ftno +# mach: all + + .include "testutils.inc" + + start + + .global ftnev +ftnev: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_fcc 0x0 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x1 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x2 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x3 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x4 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x5 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x6 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x7 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x8 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x9 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xa 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xb 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xc 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xd 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xe 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xf 0 + ftno ; should branch to tbr + (128 + 4)*16 + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fto.cgs b/sim/testsuite/sim/frv/fto.cgs new file mode 100644 index 00000000000..82035f4bec0 --- /dev/null +++ b/sim/testsuite/sim/frv/fto.cgs @@ -0,0 +1,113 @@ +# frv testcase for fto $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global fto +fto: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftra.cgs b/sim/testsuite/sim/frv/ftra.cgs new file mode 100644 index 00000000000..7754f697640 --- /dev/null +++ b/sim/testsuite/sim/frv/ftra.cgs @@ -0,0 +1,115 @@ +# frv testcase for ftra $GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftra +ftra: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_fcc 0x0 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass diff --git a/sim/testsuite/sim/frv/ftu.cgs b/sim/testsuite/sim/frv/ftu.cgs new file mode 100644 index 00000000000..354423baa36 --- /dev/null +++ b/sim/testsuite/sim/frv/ftu.cgs @@ -0,0 +1,101 @@ +# frv testcase for ftu $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftu +ftu: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_fcc 0x6 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_fcc 0xa 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_fcc 0xe 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftue.cgs b/sim/testsuite/sim/frv/ftue.cgs new file mode 100644 index 00000000000..564bb30265a --- /dev/null +++ b/sim/testsuite/sim/frv/ftue.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftue $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftue +ftue: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_fcc 0x6 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftug.cgs b/sim/testsuite/sim/frv/ftug.cgs new file mode 100644 index 00000000000..cc6a405a596 --- /dev/null +++ b/sim/testsuite/sim/frv/ftug.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftug $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftug +ftug: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftuge.cgs b/sim/testsuite/sim/frv/ftuge.cgs new file mode 100644 index 00000000000..7c04eaf29a4 --- /dev/null +++ b/sim/testsuite/sim/frv/ftuge.cgs @@ -0,0 +1,113 @@ +# frv testcase for ftuge $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftuge +ftuge: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftul.cgs b/sim/testsuite/sim/frv/ftul.cgs new file mode 100644 index 00000000000..b45ebb35bed --- /dev/null +++ b/sim/testsuite/sim/frv/ftul.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftul $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftul +ftul: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_fcc 0xa 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftule.cgs b/sim/testsuite/sim/frv/ftule.cgs new file mode 100644 index 00000000000..4a93260d3d6 --- /dev/null +++ b/sim/testsuite/sim/frv/ftule.cgs @@ -0,0 +1,113 @@ +# frv testcase for ftule $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftule +ftule: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/icei.cgs b/sim/testsuite/sim/frv/icei.cgs new file mode 100644 index 00000000000..3322fa4d2b0 --- /dev/null +++ b/sim/testsuite/sim/frv/icei.cgs @@ -0,0 +1,15 @@ +# frv testcase for icei @(GRi,GRj),a +# mach: fr400 + + .include "testutils.inc" + + start + + .global icei +icei: + ; Can't really test this because of SCACHE implementation + set_gr_addr icei,gr10 + icei @(gr10,gr0),1 + icei @(gr10,gr0),1 + + pass diff --git a/sim/testsuite/sim/frv/ici.cgs b/sim/testsuite/sim/frv/ici.cgs new file mode 100644 index 00000000000..8aeacae33a9 --- /dev/null +++ b/sim/testsuite/sim/frv/ici.cgs @@ -0,0 +1,39 @@ +# FRV testcase for ici @(GRi,GRj) +# mach: all + + .include "testutils.inc" + + start + + .global ici +ici: + set_gr_immed 1234,gr2 + set_spr_addr ok1,lr + bra testit + +ok1: + ; Change the first insn to set gr1 to 1235 + ; but don't invalidate the insn cache + ; should have no effect + set_gr_mem testit,gr10 + ori gr10,1,gr10 + set_mem_gr gr10,testit + set_gr_addr testit,gr10 + dcf @(gr10,gr0) ; flush data cache + set_spr_addr ok2,lr + bra testit + +ok2: ; Now invalidate the insn cache. The new insn should take effect + ici @(gr10,gr0) + set_gr_immed 1235,gr2 + set_spr_addr ok3,lr + bra testit + +ok3: + pass + +testit: + setlos 1234,gr1 + test_gr_gr gr1,gr2 + bralr + fail diff --git a/sim/testsuite/sim/frv/icpl.cgs b/sim/testsuite/sim/frv/icpl.cgs new file mode 100644 index 00000000000..b86ba352796 --- /dev/null +++ b/sim/testsuite/sim/frv/icpl.cgs @@ -0,0 +1,39 @@ +# FRV testcase for icpl GRi,GRj,lock +# mach: all + + .include "testutils.inc" + + start + + .global icpl + ; keep this at least 64 bytes away from doit2 + bra icpl +doit1: add gr11,gr12,gr11 + bralr + +icpl: + or_spr_immed 0x80000000,hsr0 ; insn cache: enable + and_spr_immed 0xbfffffff,hsr0 ; data cache: disable + set_gr_immed 0,gr11 + set_gr_immed 1,gr12 + set_gr_immed 2,gr13 + + set_gr_addr doit1,gr10 + icpl gr10,gr0,0 ; preload insns at doit1 + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 + + set_gr_addr doit2,gr10 + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 + + set_spr_addr ok1,lr + bra doit1 +ok1: test_gr_immed 1,gr11 ; used preloaded add of 1 + + set_spr_addr ok2,lr + bra doit2 +ok2: test_gr_immed 3,gr11 ; used changed add of 2 + + pass + +doit2: add gr11,gr12,gr11 + bralr diff --git a/sim/testsuite/sim/frv/icul.cgs b/sim/testsuite/sim/frv/icul.cgs new file mode 100644 index 00000000000..b112f41f5ea --- /dev/null +++ b/sim/testsuite/sim/frv/icul.cgs @@ -0,0 +1,53 @@ +# FRV testcase for icul $GRi +# mach: all + + .include "testutils.inc" + + start + + .global icul +icul: + or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode + + ; preload and lock all the lines in set 0 of the insn cache + set_gr_immed 0x70000,gr10 + set_bctrlr_0_0 gr10 + lock_insn_cache gr10 + + inc_gr_immed 0x1000,gr10 + set_bctrlr_0_0 gr10 + lock_insn_cache gr10 + + inc_gr_immed 0x1000,gr10 + set_bctrlr_0_0 gr10 + lock_insn_cache gr10 + + inc_gr_immed 0x1000,gr10 + set_bctrlr_0_0 gr10 + lock_insn_cache gr10 + + ; execute the pre-loaded insn + set_gr_immed 0x70000,gr10 + calll @(gr10,gr0) ; should come right back + inc_gr_immed 0x1000,gr10 + calll @(gr10,gr0) ; should come right back + inc_gr_immed 0x1000,gr10 + calll @(gr10,gr0) ; should come right back + inc_gr_immed 0x1000,gr10 + calll @(gr10,gr0) ; should come right back + + ; Now execute another insn which would have gone into set 0. + inc_gr_immed 0x1000,gr10 + set_bctrlr_0_0 gr10 + set_spr_immed 128,lcr + calll @(gr10,gr0) ; should come right back + + ; Now unlock one of the lines and do it again + set_gr_immed 0x71000,gr10 + icul gr10 + calll @(gr10,gr0) ; should come right back + + inc_gr_immed 0x3000,gr10 + calll @(gr10,gr0) ; should come right back + + pass diff --git a/sim/testsuite/sim/frv/interrupts.exp b/sim/testsuite/sim/frv/interrupts.exp new file mode 100644 index 00000000000..b411c5ca716 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "frv fr500 fr400" + set cpu_option -mcpu + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/interrupts/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/frv/interrupts/Ipipe.cgs b/sim/testsuite/sim/frv/interrupts/Ipipe.cgs new file mode 100644 index 00000000000..aeeabd986d2 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/Ipipe.cgs @@ -0,0 +1,35 @@ +# FRV testcase +# mach: fr400,fr500 + + .include "testutils.inc" + + start + + .global Ipipe +Ipipe: + ; clear the packing bit if the insn at 'pack:'. We can't simply use + ; '.p' because the assembler will catch the error. + set_gr_mem pack,gr10 + and_gr_immed 0x7fffffff,gr10 + set_mem_gr gr10,pack + set_gr_addr pack,gr10 + flush_data_cache gr10 + + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 0x070,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + set_spr_addr ok0,lr + set_psr_et 1 + + add.p gr1,gr1,gr1 +pack: add gr2,gr2,gr2 +bad: add gr3,gr3,gr3 + fail +ok0: + test_spr_immed 1,esfr1 + test_spr_bits 0x3f,0,0xb,esr0 + test_spr_addr bad,epcr0 + + pass diff --git a/sim/testsuite/sim/frv/interrupts/badalign.cgs b/sim/testsuite/sim/frv/interrupts/badalign.cgs new file mode 100644 index 00000000000..b8660219da8 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/badalign.cgs @@ -0,0 +1,73 @@ +# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) +# mach: fr500 frv + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x100,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + set_gr_immed 0xdeadbeef,gr17 + set_gr_immed 0,gr15 + inc_gr_immed 2,sp ; out of alignment + + test_spr_bits 1,0,1,isr ; mem_address_not_aligned is masked + sti gr17,@(sp,0) ; no exception + ldi @(sp,-2),gr18 ; stored at aligned address + test_gr_immed 0xdeadbeef,gr18 + ldi @(sp,0),gr19 ; no exception + test_gr_immed 0xdeadbeef,gr19 + + and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM + set_gr_addr bad1,gr16 +bad1: sti gr17,@(sp,0) ; misaligned write in slot I1 + test_gr_immed 1,gr15 + + set_gr_addr bad3,gr16 + set_gr_gr sp,gr20 + set_gr_immed 1,gr21 + set_gr_immed 0x10101010,gr10 +bad2: nop.p +bad3: ldu @(sp,gr21),gr10 ; misaligned read in slot I2 + test_gr_immed 2,gr15 ; handler was called + test_gr_immed 0x10101010,gr10 ; gr10 not updated + test_gr_immed 1,gr21 ; gr21 not updated + inc_gr_immed 1,gr20 + test_gr_gr gr20,sp ; sp updated + + pass + +; exception handler +ok1: + cmpi gr15,0,icc0 + bne icc0,0,load + ; handle interrupt on store + test_spr_immed 0x100,esfr1 ; esr8 is active + test_spr_gr epcr8,gr16 + test_spr_bits 0x0001,0,0x1,esr8 ; esr8 is valid + test_spr_bits 0x003e,1,0xb,esr8 ; esr8.ec is set + test_spr_bits 0x0800,11,0x1,esr8 ; esr8.eav is set + test_spr_gr ear8,sp + test_spr_bits 0x01000,12,0x1,esr8 ; esr8.edv is set + test_spr_bits 0x1e000,13,0x3,esr8 ; esr8.edn is 3 + test_spr_gr edr3,gr17 ; edr3 is set + bra ret +load: + ; handle interrupt on load + test_spr_immed 0x200,esfr1 ; esr9 is active + test_spr_gr epcr9,gr16 + test_spr_bits 0x0001,0,0x1,esr9 ; esr9 is valid + test_spr_bits 0x003e,1,0xb,esr9 ; esr9.ec is set + test_spr_bits 0x0800,11,0x1,esr9 ; esr9.eav is set + test_spr_gr ear9,sp + test_spr_bits 0x1000,12,0x0,esr9 ; esr9.edv is not set +ret: + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/compound.cgs b/sim/testsuite/sim/frv/interrupts/compound.cgs new file mode 100644 index 00000000000..2fd928eeee5 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/compound.cgs @@ -0,0 +1,66 @@ +# frv testcase to generate compound exception +# mach: fr500 frv + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x200,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + or_spr_immed 0x04000000,fsr0 ; enabled div/0 fp_exception + set_psr_et 1 + + set_gr_immed 0,gr15 + set_fr_iimmed 0x7f7f,0xffff,fr0 + set_fr_iimmed 0x0000,0x0000,fr1 + + and_spr_immed 0xfffffffe,isr ; enable mem_address_not_aligned + set_gr_addr store,gr16 + set_gr_addr dividei,gr17 + set_gr_immed 0xdeadbeef,gr8 + inc_gr_immed 2,sp ; misalign +store: sti.p gr8,@(sp,0) ; misaligned write +dividef:fdivs.p fr0,fr1,fr2 ; fp_exception +dividei:sdiv gr1,gr0,gr1 ; division exception + test_gr_immed 1,gr15 + + pass + +; exception handler +ok1: + ; check interrupt on store + test_spr_immed 0x102,esfr1 ; esr8 and esr1 are active + test_spr_gr epcr8,gr16 + test_spr_bits 0x0001,0,0x1,esr8 ; esr8 is valid + test_spr_bits 0x003e,1,0xb,esr8 ; esr8.ec is set + test_spr_bits 0x0800,11,0x1,esr8 ; esr8.eav is set + test_spr_gr ear8,sp + test_spr_bits 0x01000,12,0x1,esr8 ; esr8.edv is set + test_spr_bits 0x1e000,13,0x3,esr8 ; esr8.edn is 3 + test_spr_gr edr3,gr8 ; edr3 is set + + ; check on fp_exception + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear + + test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set + test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set + test_spr_bits 0x380,7,0x1,fqst2 ; fq2.ftt is set + test_spr_bits 0x7e,1,0x4,fqst2 ; fq2.cexc is set + test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set + test_spr_immed 0x05e40241,fqop2 ; fq2.opc + + ; check interrupt on dividei + test_spr_gr epcr1,gr17 + test_spr_bits 0x0001,0,0x1,esr1 ; esr1 is valid + test_spr_bits 0x003e,1,0x13,esr1 ; esr1.ec is set + + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/data_store_error.cgs b/sim/testsuite/sim/frv/interrupts/data_store_error.cgs new file mode 100644 index 00000000000..b967d0a0525 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/data_store_error.cgs @@ -0,0 +1,53 @@ +# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) +# mach: fr500 +# sim(fr500): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010 + .include "testutils.inc" + + start + + .global dsr +dsr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x140,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + + set_spr_addr ok0,lr + set_gr_immed 0,gr16 + + set_gr_immed 0xdeadbeef,gr15 + set_gr_addr 0xfeff0600,gr17 +bad1: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 1,gr16 + + set_gr_immed 0xbeefdead,gr15 + set_gr_addr 0xfeff7ffc,gr17 +bad2: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 2,gr16 + + set_gr_immed 0xbeefbeef,gr15 + set_gr_addr 0xfe800000,gr17 +bad3: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 3,gr16 + + set_gr_immed 0xdeaddead,gr15 + set_gr_addr 0xfefefffc,gr17 +bad4: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 4,gr16 + + sti gr0,@(sp,0) ; no interrupt + test_gr_immed 4,gr16 + + pass +ok0: + ; check interrupts + test_spr_immed 0x4000,esfr1 ; esr14 is active + test_spr_bits 0x0001,0,0x1,esr14 ; esr14 is valid + test_spr_bits 0x003e,1,0x0,esr14 ; esr14.ec is set + test_spr_bits 0x0800,11,0x0,esr14 ; esr14.eav is not set + + addi gr16,1,gr16 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception.cgs new file mode 100644 index 00000000000..710b5baa129 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/fp_exception.cgs @@ -0,0 +1,191 @@ +# frv testcase to generate fp_exception +# mach: fr500 + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global align +align: + ; clear the packing bit if the insn at 'pack:'. We can't simply use + ; '.p' because the assembler will catch the error. + set_gr_mem pack,gr10 + and_gr_immed 0x7fffffff,gr10 + set_mem_gr gr10,pack + set_gr_addr pack,gr10 + flush_data_cache gr10 + + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x070,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + inc_gr_immed 0x060,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + inc_gr_immed -4,sp ; for alignment + + set_gr_immed 0,gr20 ; PC increment + set_gr_immed 0,gr15 + + set_spr_addr ok3,lr + stdfi fr1,@(sp,0) ; misaligned reg -- slot I0 + test_gr_immed 1,gr15 + + set_spr_addr ok4,lr + nop.p + lddfi @(sp,0),fr9 ; misaligned reg -- slot I1 + test_gr_immed 2,gr15 + + set_spr_addr ok5,lr + fnegs.p fr9,fr9 +pack: fnegs fr10,fr10 + fnegs fr10,fr11 ; packing violation + test_gr_immed 3,gr15 + + set_spr_addr ok1,lr + set_gr_immed 4,gr20 ; PC increment +bad: fmadds fr16,fr4,fr1 ; unimplemented + test_gr_immed 4,gr15 + + and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception + set_fr_iimmed 0x7f7f,0xffff,fr0 + set_fr_iimmed 0x0000,0x0000,fr1 + fdivs fr0,fr1,fr2 ; div/0 -- no exception + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is still set + test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set + test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear + and_spr_immed 0xffefffff,fsr0 ; Clear fsr0.qne + + set_spr_addr ok2,lr + set_gr_immed 0,gr20 ; PC increment + or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception + set_fr_iimmed 0xdead,0xbeef,fr2 + fdivs fr0,fr1,fr2 ; fp_exception - div/0 + test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated + test_gr_immed 5,gr15 + + and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception + fsqrts fr32,fr2 ; inexact -- no exception + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is still set + test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set + test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear + + set_fr_fr fr2,fr3 ; sqrt 2 + set_fr_iimmed 0xdead,0xbeef,fr2 + set_spr_addr ok6,lr + or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception + fsqrts fr32,fr2 ; fp_exception - inexact + test_gr_immed 6,gr15 ; handler called + test_fr_fr fr2,fr3 ; fr2 updated + + set_fr_iimmed 0xdead,0xbeef,fr2 + set_spr_addr ok7,lr + fsqrts fr32,fr2 ; fp_exception - inexact again + test_gr_immed 7,gr15 ; handler called + test_fr_fr fr2,fr3 ; fr2 updated + + pass + +; exception handler 1 -- bad insn +ok1: + test_spr_immed 1,esfr1 ; esr0 active + test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set + test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set + test_spr_addr bad,epcr0 + bra ret + +; exception handler 2 - fp_exception: divide by 0 +ok2: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set + + test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set + test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set + test_spr_bits 0x380,7,0x1,fqst2 ; fq2.ftt is set + test_spr_bits 0x7e,1,0x4,fqst2 ; fq2.cexc is set + test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set + test_spr_immed 0x85e40241,fqop2 ; fq2.opc + bra ret + +; exception handler 3 - fp_exception: register exception +ok3: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x6,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear + + test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set + test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set + test_spr_bits 0x380,7,0x6,fqst2 ; fq2.ftt is set + test_spr_bits 0x7e,1,0x0,fqst2 ; fq2.cexc is set + test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set + test_spr_immed 0x83581000,fqop2 ; fq2.opc + bra ret + +; exception handler 4 - fp_exception: another register exception +ok4: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x6,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is still clear + + test_spr_bits 0x80000000,31,0x0,fqst3 ; fq3.miv is set + test_spr_bits 0x18000,15,0x0,fqst3 ; fq3.sie is set + test_spr_bits 0x380,7,0x6,fqst3 ; fq3.ftt is set + test_spr_bits 0x7e,1,0x0,fqst3 ; fq3.cexc is set + test_spr_bits 0x1,0,0x1,fqst3 ; fq3.valid is set + test_spr_immed 0x92ec1000,fqop3 ; fq3.opc + bra ret + +; exception handler 5 - fp_exception: sequence violation +ok5: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x4,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is still clear + + test_spr_bits 0x80000000,31,0x0,fqst3 ; fq3.miv is set + test_spr_bits 0x18000,15,0x0,fqst3 ; fq3.sie is set + test_spr_bits 0x380,7,0x4,fqst3 ; fq3.ftt is set + test_spr_bits 0x7e,1,0x0,fqst3 ; fq3.cexc is set + test_spr_bits 0x1,0,0x1,fqst3 ; fq3.valid is set + test_spr_immed 0x97e400ca,fqop3 ; fq3.opc + bra ret + +; exception handler 6 - fp_exception: inexact +ok6: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set + + test_spr_bits 0x80000000,31,0x0,fqst0 ; fq0.miv is set + test_spr_bits 0x18000,15,0x0,fqst0 ; fq0.sie is set + test_spr_bits 0x380,7,0x1,fqst0 ; fq0.ftt is set + test_spr_bits 0x7e,1,0x2,fqst0 ; fq0.cexc is set + test_spr_bits 0x1,0,0x1,fqst0 ; fq0.valid is set + test_spr_immed 0x85e40160,fqop0 ; fq0.opc + bra ret + +; exception handler 7 - fp_exception: inexact again +ok7: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set + + test_spr_bits 0x80000000,31,0x0,fqst1 ; fq1.miv is set + test_spr_bits 0x18000,15,0x0,fqst1 ; fq1.sie is set + test_spr_bits 0x380,7,0x1,fqst1 ; fq1.ftt is set + test_spr_bits 0x7e,1,0x2,fqst1 ; fq1.cexc is set + test_spr_bits 0x1,0,0x1,fqst1 ; fq1.valid is set + test_spr_immed 0x85e40160,fqop1 ; fq1.opc + bra ret + +ret: + inc_gr_immed 1,gr15 + movsg pcsr,gr60 + add gr60,gr20,gr60 + movgs gr60,pcsr + rett 0 + fail + diff --git a/sim/testsuite/sim/frv/interrupts/illinsn.cgs b/sim/testsuite/sim/frv/interrupts/illinsn.cgs new file mode 100644 index 00000000000..175709e5b00 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/illinsn.cgs @@ -0,0 +1,34 @@ +# FRV testcase +# mach: fr500 fr400 + + .include "testutils.inc" + + start + + .global tra +tra: + and_spr_immed 0x3fffffff,hsr0 ; no caches enabled + + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 0x070,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + inc_gr_immed 0x790,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + set_psr_et 1 + set_spr_addr ok0,lr + + set_gr_addr ill1,gr7 + set_mem_immed 0x81f80000,gr7 ; unknown opcode: 7E +ill1: tira gr0,0 ; should be overridden +ill2: nop ; also illegal, but prev has priority +bad0: fail + + ; check interrupt +ok0: test_spr_addr ill1,pcsr + test_spr_immed 1,esfr1 ; esr0 active + test_spr_bits 0x3f,0,0xb,esr0 + test_spr_addr ill1,epcr0 + + pass diff --git a/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs b/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs new file mode 100644 index 00000000000..11a9eaf5355 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs @@ -0,0 +1,56 @@ +# frv testcase to generate insn_access_error interrupt +# mach: fr500 fr400 +# sim: --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0040 + .include "testutils.inc" + + start + + .global dsr +dsr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x020,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + + set_spr_addr handler,lr + set_gr_immed 0,gr16 + + set_gr_addr ok0,gr8 + set_gr_addr 0xfeff0600,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok0: + test_gr_immed 1,gr16 + + set_gr_addr ok1,gr8 + set_gr_addr 0xfeff7ffc,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok1: + test_gr_immed 2,gr16 + + set_gr_addr ok2,gr8 + set_gr_addr 0xfe800000,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok2: + test_gr_immed 3,gr16 + + set_gr_addr ok3,gr8 + set_gr_addr 0xfefefffc,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok3: + test_gr_immed 4,gr16 + + pass +handler: + ; check interrupts + test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr17 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x2,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set + + addi gr16,1,gr16 + movgs gr8,pcsr + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/mp_exception.cgs b/sim/testsuite/sim/frv/interrupts/mp_exception.cgs new file mode 100644 index 00000000000..8d4efed7669 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/mp_exception.cgs @@ -0,0 +1,289 @@ +# frv testcase for mp_exception +# mach: fr500 frv +# xerror: + +# This program no longer assembles because the assembler +# now detects the unaligned registers. For this reason +# this test is now marked as "xerror" and prints the +# expected message "fail" + + .include "testutils.inc" + + start + + .global mp_exception +mpx: +.if 1 + fail +.else + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mcmpsh fr10,fr11,fcc1 ; mp_exception: cr-not-aligned + test_spr_bits 0x7000,12,3,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf is set + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mcmpsh.p fr10,fr11,fcc0 ; no exception + mcmpsh fr10,fr11,fcc2 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mmulhs.p fr10,fr11,acc3 ; no exception + mmulhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mmulhu fr10,fr11,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mmulxhs.p fr10,fr11,acc3 ; no exception + mmulxhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mmulxhu fr10,fr11,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mmachs.p fr10,fr11,acc3 ; no exception + mmachs fr10,fr11,acc1 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mmachu fr10,fr11,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqaddhss.p fr10,fr12,fr17 ; mp_exception: register-not-aligned + mqaddhss fr10,fr12,fr14 ; no exception + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqaddhss.p fr10,fr12,fr14 ; no exception + mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqaddhss.p fr19,fr12,fr14 ; mp_exception: register-not-aligned + mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqaddhss fr10,fr12,fr14 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqmulhs.p fr10,fr11,acc3 ; no exception + mqmulhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmulhu fr10,fr11,acc0 ; mp_exception: register_not_aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmulhu fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqmulxhs.p fr10,fr11,acc3 ; no exception + mqmulxhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmulxhu fr10,fr11,acc0 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmulxhu fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqmachs.p fr10,fr12,acc3 ; no exception + mqmachs fr10,fr12,acc2 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned + mqmachu fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmachu.p fr10,fr12,acc0 ; no exception + mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned + mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmachu fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqcpxrs.p fr10,fr12,acc0 ; no exception + mqcpxrs fr10,fr12,acc1 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned + mqcpxru fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqcpxru.p fr10,fr12,acc0 ; no exception + mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned + mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqcpxru fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + pass +.endif diff --git a/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs b/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs new file mode 100644 index 00000000000..9996236b333 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs @@ -0,0 +1,54 @@ +# frv testcase to generate privileged_instruction interrupt +# mach: frv + + .include "testutils.inc" + + start + + .global dsr +dsr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x060,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + and_spr_immed 0xfffffffb,psr ; clear psr.s + + set_spr_addr handler,lr + set_gr_immed 0,gr16 + + set_gr_addr bad1,gr17 +bad1: rett 0 ; cause interrupt + test_gr_immed 1,gr16 + set_gr_addr bad2,gr17 +bad2: rei 0 ; cause interrupt + test_gr_immed 2,gr16 + set_gr_addr bad3,gr17 +bad3: witlb gr0,@(gr0,gr0) ; cause interrupt + test_gr_immed 3,gr16 + set_gr_addr bad4,gr17 +bad4: wdtlb gr0,@(gr0,gr0) ; cause interrupt + test_gr_immed 4,gr16 + set_gr_addr bad5,gr17 +bad5: itlbi @(gr0,gr0) ; cause interrupt + test_gr_immed 5,gr16 + set_gr_addr bad6,gr17 +bad6: dtlbi @(gr0,gr0) ; cause interrupt + test_gr_immed 6,gr16 + + pass +handler: + ; check interrupts + test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr17 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x4,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set + + addi gr16,1,gr16 + movsg pcsr,gr8 + addi gr8,4,gr8 + movgs gr8,pcsr + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/regalign.cgs b/sim/testsuite/sim/frv/interrupts/regalign.cgs new file mode 100644 index 00000000000..e1137539551 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/regalign.cgs @@ -0,0 +1,96 @@ +# frv testcase to generate interrupts for bad register alignment +# mach: frv + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x080,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + inc_gr_immed 0x050,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + + set_gr_immed 4,gr20 ; PC increment + set_gr_immed 0,gr15 + inc_gr_immed -12,sp ; for memory alignment + + set_gr_addr bad1,gr17 +bad1: stdi gr1,@(sp,0) ; misaligned reg + test_gr_immed 1,gr15 + + set_gr_addr bad2,gr17 +bad2: lddi @(sp,0),gr9 ; misaligned reg + test_gr_immed 2,gr15 + + set_gr_addr bad3,gr17 +bad3: stdc cpr1,@(sp,gr0) ; misaligned reg + test_gr_immed 3,gr15 + + set_gr_addr bad4,gr17 +bad4: lddc @(sp,gr0),cpr9 ; misaligned reg + test_gr_immed 4,gr15 + + set_gr_addr bad5,gr17 +bad5: stqi gr2,@(sp,0) ; misaligned reg + test_gr_immed 5,gr15 + + set_gr_addr bad6,gr17 +bad6: ldqi @(sp,0),gr10 ; misaligned reg + test_gr_immed 6,gr15 + + set_gr_addr bad7,gr17 +bad7: stqc cpr2,@(sp,gr0) ; misaligned reg + test_gr_immed 7,gr15 + + set_gr_addr bad8,gr17 +bad8: ldqc @(sp,gr0),cpr10 ; misaligned reg + test_gr_immed 8,gr15 + + set_gr_immed 0,gr20 ; PC increment + set_gr_addr bad9,gr17 +bad9: stdfi fr1,@(sp,0) ; misaligned reg + test_gr_immed 9,gr15 + + set_gr_addr bada,gr17 +bada: lddfi @(sp,0),fr9 ; misaligned reg + test_gr_immed 10,gr15 + + set_gr_addr badb,gr17 +badb: stqfi fr2,@(sp,0) ; misaligned reg + test_gr_immed 11,gr15 + + set_gr_addr badc,gr17 +badc: ldqfi @(sp,0),fr10 ; misaligned reg + test_gr_immed 12,gr15 + + pass + +; exception handler +ok1: + cmpi gr20,0,icc0 + beq icc0,0,float + + ; check register_exception + test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr17 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0xc,esr0 ; esr0.ec is set + test_spr_bits 0x00c0,6,0x1,esr0 ; esr0.rec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set + movsg pcsr,gr60 + add gr60,gr20,gr60 + movgs gr60,pcsr + bra ret +float: + ; check fp_exception + test_spr_immed 0,esfr1 ; no esr's active +ret: + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/reset.cgs b/sim/testsuite/sim/frv/interrupts/reset.cgs new file mode 100644 index 00000000000..ef8307c6210 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/reset.cgs @@ -0,0 +1,81 @@ +# frv testcase to generate reset interrupts +# mach: fr500 fr400 +# sim: --memory-region 0xff000000,64 + + .include "testutils.inc" + + start + + .global reset +reset: + and_spr_immed 0xfffffffb,psr ; turn off PSR.S + set_gr_immed 0xfeff0500,gr10 ; address of reset register + set_spr_immed 0x7fffffff,lcr + set_bctrlr_0_0 gr0 + +; Can't recover from hardware interrupt with enough state intact to verify it +; set_spr_addr ok1,lr +; set_mem_immed 0x3,gr10 ; cause hardware reset +; dcf @(gr10,gr0) ; Wait for store to happen +; fail +; +;ok1: ; reset should branch to reset address which should then branch here +; test_mem_immed 0x00000200,gr10 +; set_spr_addr ok2,lr +; set_mem_immed 0x2,gr10 ; cause hardware reset +; dcf @(gr10,gr0) ; Wait for store to happen +; fail +; +ok2: ; reset should branch to reset address which should then branch here +; test_mem_immed 0x00000200,gr10 + set_spr_addr ok3,lr + set_mem_immed 0x1,gr10 ; cause software reset + dcf @(gr10,gr0) ; Wait for store to happen + fail + +ok3: ; reset should branch to reset address which should then branch here + test_mem_immed 0x00000100,gr10 + test_spr_bits 0x4,2,1,psr ; psr.s is set + test_spr_bits 0x2,1,0,psr ; psr.ps not set + set_spr_addr bad,lr + set_mem_immed 0x0,gr10 ; no reset + test_mem_immed 0x0,gr10 + + ; now retest with HSR0.SA set + set_mem_immed 0,gr0 + set_gr_addr 0xff000000,gr11 + set_bctrlr_0_0 gr11 + or_spr_immed 0x00001000,hsr0 ; set HSR0.SA + +; Can't recover from hardware interrupt with enough state intact to verify it +; set_spr_addr ok4,lr +; dcf @(gr10,gr0) ; Wait for store to happen +; set_mem_immed 0x3,gr10 ; cause hardware reset +; fail +; +;ok4: ; reset should branch to reset address which should then branch here +; test_mem_immed 0x00000200,gr10 +; set_spr_addr ok5,lr +; set_mem_immed 0x2,gr10 ; cause hardware reset +; dcf @(gr10,gr0) ; Wait for store to happen +; fail +; +ok5: ; reset should branch to reset address which should then branch here +; test_mem_immed 0x00000200,gr10 + set_spr_addr ok6,lr + set_mem_immed 0x1,gr10 ; cause software reset + dcf @(gr10,gr0) ; Wait for store to happen + fail + +ok6: ; reset should branch to reset address which should then branch here + test_mem_immed 0x00000100,gr10 + test_spr_bits 0x4,2,1,psr ; psr.s is set + test_spr_bits 0x2,1,1,psr ; psr.ps is set + set_spr_addr bad,lr + set_mem_immed 0x0,gr10 ; no reset + test_mem_immed 0x0,gr10 + + pass + +bad: ; Should never get here + fail diff --git a/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs b/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs new file mode 100644 index 00000000000..ee6bea45e71 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs @@ -0,0 +1,205 @@ +# FRV testcase for handling of shadow registers SR0-SR4 +# mach: frv + + .include "testutils.inc" + + start + + .global tra +tra: + test_spr_bits 0x800,11,1,psr ; PSR.ESR set + test_spr_bits 0x4,2,1,psr ; PSR.S set + + ; Set up exception handler for later + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + set_spr_immed 128,lcr + set_psr_et 1 + + set_gr_immed 0x11111111,gr4 ; SGR4-7 + set_gr_immed 0x22222222,gr5 + set_gr_immed 0x33333333,gr6 + set_gr_immed 0x44444444,gr7 + set_spr_immed 0x55555555,sr0 ; UGR4-7 + set_spr_immed 0x66666666,sr1 + set_spr_immed 0x77777777,sr2 + set_spr_immed 0x88888888,sr3 + + and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + + set_spr_immed 0x55555555,sr0 ; SGR4-7 + set_spr_immed 0x66666666,sr1 + set_spr_immed 0x77777777,sr2 + set_spr_immed 0x88888888,sr3 + test_gr_immed 0x55555555,gr4 ; SGR4-7 + test_gr_immed 0x66666666,gr5 + test_gr_immed 0x77777777,gr6 + test_gr_immed 0x88888888,gr7 + test_spr_immed 0x55555555,sr0 ; SGR4-7 + test_spr_immed 0x66666666,sr1 + test_spr_immed 0x77777777,sr2 + test_spr_immed 0x88888888,sr3 + + set_gr_immed 0x11111111,gr4 ; SGR4-7 + set_gr_immed 0x22222222,gr5 + set_gr_immed 0x33333333,gr6 + set_gr_immed 0x44444444,gr7 + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + + or_spr_immed 0x00000800,psr ; turn on PSR.ESR + test_gr_immed 0x11111111,gr4 ; SGR4-7 -- SR0-3 (UGR4-7) are undefined + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + + set_spr_immed 0x55555555,sr0 ; UGR4-7 + set_spr_immed 0x66666666,sr1 + set_spr_immed 0x77777777,sr2 + set_spr_immed 0x88888888,sr3 + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x55555555,sr0 ; UGR4-7 + test_spr_immed 0x66666666,sr1 + test_spr_immed 0x77777777,sr2 + test_spr_immed 0x88888888,sr3 + + and_spr_immed 0xfffffffb,psr ; turn off PSR.S + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + test_gr_immed 0x55555555,gr4 ; UGR4-7 + test_gr_immed 0x66666666,gr5 + test_gr_immed 0x77777777,gr6 + test_gr_immed 0x88888888,gr7 + + ; need to generate a trap to return to supervisor mode + set_spr_addr ok0,lr + tira gr0,4 ; should branch to tbr + (128 + 4)*16 + + test_spr_bits 0x800,11,0,psr ; PSR.ESR clear + test_spr_bits 0x4,2,0,psr ; PSR.S clear + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + + set_gr_immed 0x55555555,gr4 ; SGR4-7 + set_gr_immed 0x66666666,gr5 + set_gr_immed 0x77777777,gr6 + set_gr_immed 0x88888888,gr7 + test_gr_immed 0x55555555,gr4 ; SGR4-7 + test_gr_immed 0x66666666,gr5 + test_gr_immed 0x77777777,gr6 + test_gr_immed 0x88888888,gr7 + test_spr_immed 0x55555555,sr0 ; SGR4-7 + test_spr_immed 0x66666666,sr1 + test_spr_immed 0x77777777,sr2 + test_spr_immed 0x88888888,sr3 + + set_gr_immed 0x11111111,gr4 ; SGR4-7 + set_gr_immed 0x22222222,gr5 + set_gr_immed 0x33333333,gr6 + set_gr_immed 0x44444444,gr7 + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + + ; need to generate a trap to return to supervisor mode + set_spr_addr ok1,lr + tira gr0,4 ; should branch to tbr + (128 + 4)*16 + + pass + +ok0: ; exception handler should branch here the first time + test_spr_bits 0x800,11,1,psr ; PSR.ESR set + test_spr_bits 0x4,2,1,psr ; PSR.S set + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x55555555,sr0 ; UGR4-7 + test_spr_immed 0x66666666,sr1 + test_spr_immed 0x77777777,sr2 + test_spr_immed 0x88888888,sr3 + + and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + rett 0 + fail + +ok1: ; exception handler should branch here the second time + test_spr_bits 0x800,11,0,psr ; PSR.ESR clear + test_spr_bits 0x4,2,1,psr ; PSR.S set + + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + + set_spr_immed 0x55555555,sr0 ; SGR4-7 + set_spr_immed 0x66666666,sr1 + set_spr_immed 0x77777777,sr2 + set_spr_immed 0x88888888,sr3 + test_gr_immed 0x55555555,gr4 ; SGR4-7 + test_gr_immed 0x66666666,gr5 + test_gr_immed 0x77777777,gr6 + test_gr_immed 0x88888888,gr7 + test_spr_immed 0x55555555,sr0 ; SGR4-7 + test_spr_immed 0x66666666,sr1 + test_spr_immed 0x77777777,sr2 + test_spr_immed 0x88888888,sr3 + + set_gr_immed 0x11111111,gr4 ; SGR4-7 + set_gr_immed 0x22222222,gr5 + set_gr_immed 0x33333333,gr6 + set_gr_immed 0x44444444,gr7 + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/timer.cgs b/sim/testsuite/sim/frv/interrupts/timer.cgs new file mode 100644 index 00000000000..7295695b417 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/timer.cgs @@ -0,0 +1,31 @@ +# frv testcase to generate timer interrupt for st $GRk,@($GRi,$GRj) +# mach: fr500 fr400 +# sim: --timer 200,14 + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x2e0,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 0x7fffffff,lcr + set_spr_addr ok1,lr + and_spr_immed 0xffffff87,psr ; enable external interrupts + or_spr_immed 0x00000069,psr ; enable external interrupts + + set_gr_immed 10,gr16 + set_gr_immed 0,gr15 + +again: cmp gr15,gr16,icc0 + blt icc0,0,again + + pass + +; exception handler +ok1: + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/jmpil.cgs b/sim/testsuite/sim/frv/jmpil.cgs new file mode 100644 index 00000000000..1d11067f224 --- /dev/null +++ b/sim/testsuite/sim/frv/jmpil.cgs @@ -0,0 +1,17 @@ +# frv testcase for jmpil @($GRi,$d12) +# mach: all + + .include "testutils.inc" + + start + + .global jmpil +jmpil: + set_spr_immed 0,lr + set_gr_addr ok1,gr8 + jmpil @(gr8,2) ; target gets aligned down + fail +ok1: + test_spr_immed 0,lr + + pass diff --git a/sim/testsuite/sim/frv/jmpl.cgs b/sim/testsuite/sim/frv/jmpl.cgs new file mode 100644 index 00000000000..9a58e606614 --- /dev/null +++ b/sim/testsuite/sim/frv/jmpl.cgs @@ -0,0 +1,18 @@ +# frv testcase for jmpl @($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global jmpl +jmpl: + set_spr_immed 0,lr + set_gr_addr ok1,gr8 + set_gr_immed 1,gr9 ; target gets aligned down + jmpl @(gr8,gr9) + fail +ok1: + test_spr_immed 0,lr + + pass diff --git a/sim/testsuite/sim/frv/jmpl.pcgs b/sim/testsuite/sim/frv/jmpl.pcgs new file mode 100644 index 00000000000..2126820a697 --- /dev/null +++ b/sim/testsuite/sim/frv/jmpl.pcgs @@ -0,0 +1,42 @@ +# frv parallel testcase for jmpl @($GRi,$GRj),$LI +# mach: all + + .include "testutils.inc" + + start + + .global jmpl +jmpl: + set_spr_immed 0,lr + set_gr_addr ok1,gr8 + set_gr_immed 0,gr9 + jmpl.p @(gr8,gr9) + setlos 10,gr10 + fail +ok1: + test_spr_immed 0,lr + test_gr_immed 10,gr10 + + set_gr_addr ok2,gr8 + inc_gr_immed -4,gr8 + inc_gr_immed 4,gr9 + calll.p @(gr8,gr9) + setlos 11,gr11 +bad2: + fail +ok2: + test_spr_addr bad2,lr + test_gr_immed 11,gr11 + + set_gr_addr ok3,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + setlos 12,gr12 + calll @(gr8,gr9) +bad3: + fail +ok3: + test_spr_addr bad3,lr + test_gr_immed 12,gr12 + + pass diff --git a/sim/testsuite/sim/frv/ld.cgs b/sim/testsuite/sim/frv/ld.cgs new file mode 100644 index 00000000000..35206c2ad57 --- /dev/null +++ b/sim/testsuite/sim/frv/ld.cgs @@ -0,0 +1,29 @@ +# frv testcase for ld @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ld +ld: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + ld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + ld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldbf.cgs b/sim/testsuite/sim/frv/ldbf.cgs new file mode 100644 index 00000000000..52ac0775b45 --- /dev/null +++ b/sim/testsuite/sim/frv/ldbf.cgs @@ -0,0 +1,27 @@ +# frv testcase for ldbf @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldbf +ldbf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + + set_gr_immed 1,gr7 + ldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + + pass diff --git a/sim/testsuite/sim/frv/ldbfi.cgs b/sim/testsuite/sim/frv/ldbfi.cgs new file mode 100644 index 00000000000..7e918069df9 --- /dev/null +++ b/sim/testsuite/sim/frv/ldbfi.cgs @@ -0,0 +1,24 @@ +# frv testcase for ldbfi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldbfi +ldbfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + ldbfi @(sp,0),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + + ldbfi @(sp,1),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + ldbfi @(sp,-1),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + + pass diff --git a/sim/testsuite/sim/frv/ldbfu.cgs b/sim/testsuite/sim/frv/ldbfu.cgs new file mode 100644 index 00000000000..3cbfb91d959 --- /dev/null +++ b/sim/testsuite/sim/frv/ldbfu.cgs @@ -0,0 +1,34 @@ +# frv testcase for ldbfu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldbfu +ldbfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + ldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/ldc.cgs b/sim/testsuite/sim/frv/ldc.cgs new file mode 100644 index 00000000000..4593c31d118 --- /dev/null +++ b/sim/testsuite/sim/frv/ldc.cgs @@ -0,0 +1,30 @@ +# frv testcase for ldc @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldc +ldc: + set_mem_limmed 0xdead,0xbeef,sp + set_cpr_limmed 0xbeef,0xdead,cpr8 + + set_gr_immed 0,gr7 + ldc @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + + set_cpr_limmed 0xbeef,0xdead,cpr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldc @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + + set_cpr_limmed 0xbeef,0xdead,cpr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + ldc @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + + pass diff --git a/sim/testsuite/sim/frv/ldcu.cgs b/sim/testsuite/sim/frv/ldcu.cgs new file mode 100644 index 00000000000..69890a8f6a4 --- /dev/null +++ b/sim/testsuite/sim/frv/ldcu.cgs @@ -0,0 +1,34 @@ +# frv testcase for ldcu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldcu +ldcu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_cpr_limmed 0xbeef,0xdead,cpr8 + + set_gr_immed 0,gr7 + ldcu @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xbeef,0xdead,cpr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldcu @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xbeef,0xdead,cpr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + ldcu @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/ldd.cgs b/sim/testsuite/sim/frv/ldd.cgs new file mode 100644 index 00000000000..fa09d31d963 --- /dev/null +++ b/sim/testsuite/sim/frv/ldd.cgs @@ -0,0 +1,43 @@ +# frv testcase for ldd @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldd +ldd: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + ldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + ldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + ldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + ; loading into gr0 should have no effect + ; gr1 is sp + set_gr_gr gr1,gr8 + ldd @(sp,gr7),gr0 + test_gr_immed 0,gr0 + test_gr_gr gr1,gr8 + pass diff --git a/sim/testsuite/sim/frv/lddc.cgs b/sim/testsuite/sim/frv/lddc.cgs new file mode 100644 index 00000000000..e01a2146ef1 --- /dev/null +++ b/sim/testsuite/sim/frv/lddc.cgs @@ -0,0 +1,45 @@ +# frv testcase for lddc @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global lddc +lddc: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + + set_gr_immed 0,gr7 + ; loading into cpr0 is business as usual + set_cpr_limmed 0xdead,0xbeef,cpr0 + set_cpr_limmed 0xbeef,0xdead,cpr1 + lddc @(sp,gr7),cpr0 + test_cpr_limmed 0xbeef,0xdead,cpr0 + test_cpr_limmed 0xdead,0xbeef,cpr1 + + lddc @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + lddc @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + lddc @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + + pass diff --git a/sim/testsuite/sim/frv/lddcu.cgs b/sim/testsuite/sim/frv/lddcu.cgs new file mode 100644 index 00000000000..b4ed485fa27 --- /dev/null +++ b/sim/testsuite/sim/frv/lddcu.cgs @@ -0,0 +1,42 @@ +# frv testcase for lddcu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global lddcu +lddcu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + + set_gr_immed 0,gr7 + lddcu @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + lddcu @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + lddcu @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/lddf.cgs b/sim/testsuite/sim/frv/lddf.cgs new file mode 100644 index 00000000000..f7bae78935d --- /dev/null +++ b/sim/testsuite/sim/frv/lddf.cgs @@ -0,0 +1,46 @@ +# frv testcase for lddf @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lddf +lddf: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + ; loading into fr0 is business as usual + set_fr_iimmed 0xdead,0xbeef,fr0 + set_fr_iimmed 0xbeef,0xdead,fr1 + lddf @(sp,gr7),fr0 + test_fr_limmed 0xbeef,0xdead,fr0 + test_fr_limmed 0xdead,0xbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + lddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + lddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + lddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + pass diff --git a/sim/testsuite/sim/frv/lddfi.cgs b/sim/testsuite/sim/frv/lddfi.cgs new file mode 100644 index 00000000000..1eac91632f4 --- /dev/null +++ b/sim/testsuite/sim/frv/lddfi.cgs @@ -0,0 +1,34 @@ +# frv testcase for lddfi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lddfi +lddfi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + lddfi @(sp,0),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + lddfi @(sp,8),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + lddfi @(sp,-8),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + pass diff --git a/sim/testsuite/sim/frv/lddfu.cgs b/sim/testsuite/sim/frv/lddfu.cgs new file mode 100644 index 00000000000..cb4c86eed02 --- /dev/null +++ b/sim/testsuite/sim/frv/lddfu.cgs @@ -0,0 +1,41 @@ +# frv testcase for lddfu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lddfu +lddfu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + lddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + lddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + lddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/lddi.cgs b/sim/testsuite/sim/frv/lddi.cgs new file mode 100644 index 00000000000..38ef2b4f728 --- /dev/null +++ b/sim/testsuite/sim/frv/lddi.cgs @@ -0,0 +1,34 @@ +# frv testcase for lddi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lddi +lddi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + lddi @(sp,0),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + lddi @(sp,8),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + lddi @(sp,-8),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + pass diff --git a/sim/testsuite/sim/frv/lddu.cgs b/sim/testsuite/sim/frv/lddu.cgs new file mode 100644 index 00000000000..5b2ead17720 --- /dev/null +++ b/sim/testsuite/sim/frv/lddu.cgs @@ -0,0 +1,50 @@ +# frv testcase for lddu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lddu +lddu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + lddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + lddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + lddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_gr_gr sp,gr8 + lddu @(gr8,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + pass diff --git a/sim/testsuite/sim/frv/ldf.cgs b/sim/testsuite/sim/frv/ldf.cgs new file mode 100644 index 00000000000..996d72c9e89 --- /dev/null +++ b/sim/testsuite/sim/frv/ldf.cgs @@ -0,0 +1,29 @@ +# frv testcase for ldf @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldf +ldf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + ldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/ldfi.cgs b/sim/testsuite/sim/frv/ldfi.cgs new file mode 100644 index 00000000000..e5ea94dbda4 --- /dev/null +++ b/sim/testsuite/sim/frv/ldfi.cgs @@ -0,0 +1,26 @@ +# frv testcase for ldfi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldfi +ldfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + ldfi @(sp,0),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + ldfi @(sp,4),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + ldfi @(sp,-4),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/ldfu.cgs b/sim/testsuite/sim/frv/ldfu.cgs new file mode 100644 index 00000000000..08f67db4375 --- /dev/null +++ b/sim/testsuite/sim/frv/ldfu.cgs @@ -0,0 +1,33 @@ +# frv testcase for ldfu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldfu +ldfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + ldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/ldhf.cgs b/sim/testsuite/sim/frv/ldhf.cgs new file mode 100644 index 00000000000..8935ac7fd61 --- /dev/null +++ b/sim/testsuite/sim/frv/ldhf.cgs @@ -0,0 +1,27 @@ +# frv testcase for ldhf @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldhf +ldhf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + + set_gr_immed 2,gr7 + ldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + ldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + + pass diff --git a/sim/testsuite/sim/frv/ldhfi.cgs b/sim/testsuite/sim/frv/ldhfi.cgs new file mode 100644 index 00000000000..362ec504854 --- /dev/null +++ b/sim/testsuite/sim/frv/ldhfi.cgs @@ -0,0 +1,24 @@ +# frv testcase for ldhfi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldhfi +ldhfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + ldhfi @(sp,0),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + + ldhfi @(sp,2),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + ldhfi @(sp,-2),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + + pass diff --git a/sim/testsuite/sim/frv/ldhfu.cgs b/sim/testsuite/sim/frv/ldhfu.cgs new file mode 100644 index 00000000000..0b342e1e7dc --- /dev/null +++ b/sim/testsuite/sim/frv/ldhfu.cgs @@ -0,0 +1,33 @@ +# frv testcase for ldhfu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldhfu +ldhfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + ldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + ldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/ldi.cgs b/sim/testsuite/sim/frv/ldi.cgs new file mode 100644 index 00000000000..f36b95d9f58 --- /dev/null +++ b/sim/testsuite/sim/frv/ldi.cgs @@ -0,0 +1,26 @@ +# frv testcase for ldi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldi +ldi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + ldi @(sp,0),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + ldi @(sp,4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + ldi @(sp,-4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldq.cgs b/sim/testsuite/sim/frv/ldq.cgs new file mode 100644 index 00000000000..e61f1de1c7b --- /dev/null +++ b/sim/testsuite/sim/frv/ldq.cgs @@ -0,0 +1,64 @@ +# frv testcase for ldq @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global ldq +ldq: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + ldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + ldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + ; loading into gr0 has no effect + ; gr1 is sp + set_gr_gr gr1,gr8 + set_gr_limmed 0x1234,0x5678,gr2 + set_gr_limmed 0x9abc,0xdef0,gr3 + ldq @(sp,gr7),gr0 + test_gr_immed 0,gr0 + test_gr_gr gr1,gr8 + set_gr_immed 0x12345678,gr2 + set_gr_immed 0x9abcdef0,gr3 + + pass diff --git a/sim/testsuite/sim/frv/ldqc.cgs b/sim/testsuite/sim/frv/ldqc.cgs new file mode 100644 index 00000000000..64b6a6afa61 --- /dev/null +++ b/sim/testsuite/sim/frv/ldqc.cgs @@ -0,0 +1,60 @@ +# frv testcase for ldqc @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global ldqc +ldqc: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + + set_gr_immed 0,gr7 + ;loading into cpr0 is business as usual + ldqc @(sp,gr7),cpr0 + test_cpr_limmed 0x9abc,0xdef0,cpr0 + test_cpr_limmed 0x1234,0x5678,cpr1 + test_cpr_limmed 0xbeef,0xdead,cpr2 + test_cpr_limmed 0xdead,0xbeef,cpr3 + + ldqc @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldqc @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + ldqc @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + + pass diff --git a/sim/testsuite/sim/frv/ldqcu.cgs b/sim/testsuite/sim/frv/ldqcu.cgs new file mode 100644 index 00000000000..18d9246c542 --- /dev/null +++ b/sim/testsuite/sim/frv/ldqcu.cgs @@ -0,0 +1,57 @@ +# frv testcase for ldqcu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global ldqcu +ldqcu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + + set_gr_immed 0,gr7 + ldqcu @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldqcu @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + ldqcu @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/ldqf.cgs b/sim/testsuite/sim/frv/ldqf.cgs new file mode 100644 index 00000000000..66fb65c130f --- /dev/null +++ b/sim/testsuite/sim/frv/ldqf.cgs @@ -0,0 +1,61 @@ +# frv testcase for ldqf @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldqf +ldqf: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + set_gr_immed 0,gr7 + ; loading into fr0 is business as usual + ldqf @(sp,gr7),fr0 + test_fr_limmed 0x9abc,0xdef0,fr0 + test_fr_limmed 0x1234,0x5678,fr1 + test_fr_limmed 0xbeef,0xdead,fr2 + test_fr_limmed 0xdead,0xbeef,fr3 + + ldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + ldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + pass diff --git a/sim/testsuite/sim/frv/ldqfi.cgs b/sim/testsuite/sim/frv/ldqfi.cgs new file mode 100644 index 00000000000..28c3b1f3247 --- /dev/null +++ b/sim/testsuite/sim/frv/ldqfi.cgs @@ -0,0 +1,51 @@ +# frv testcase for ldqfi @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldqfi +ldqfi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + ldqfi @(sp,0),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + ldqfi @(sp,16),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 32,sp + ldqfi @(sp,-16),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + pass diff --git a/sim/testsuite/sim/frv/ldqfu.cgs b/sim/testsuite/sim/frv/ldqfu.cgs new file mode 100644 index 00000000000..7287958166d --- /dev/null +++ b/sim/testsuite/sim/frv/ldqfu.cgs @@ -0,0 +1,58 @@ +# frv testcase for ldqfu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldqfu +ldqfu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + set_gr_immed 0,gr7 + ldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + ldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/ldqi.cgs b/sim/testsuite/sim/frv/ldqi.cgs new file mode 100644 index 00000000000..64d66f2f766 --- /dev/null +++ b/sim/testsuite/sim/frv/ldqi.cgs @@ -0,0 +1,51 @@ +# frv testcase for ldqi @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldqi +ldqi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + ldqi @(sp,0),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + ldqi @(sp,16),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + ldqi @(sp,-16),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + pass diff --git a/sim/testsuite/sim/frv/ldqu.cgs b/sim/testsuite/sim/frv/ldqu.cgs new file mode 100644 index 00000000000..263eae1b60f --- /dev/null +++ b/sim/testsuite/sim/frv/ldqu.cgs @@ -0,0 +1,71 @@ +# frv testcase for ldqu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldqu +ldqu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + ldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + ldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + set_gr_gr sp,gr8 + ldqu @(gr8,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + pass diff --git a/sim/testsuite/sim/frv/ldsb.cgs b/sim/testsuite/sim/frv/ldsb.cgs new file mode 100644 index 00000000000..4b10639ca9f --- /dev/null +++ b/sim/testsuite/sim/frv/ldsb.cgs @@ -0,0 +1,27 @@ +# frv testcase for ldsb @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldsb +ldsb: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + ldsb @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + + set_gr_immed 1,gr7 + ldsb @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldsb @(sp,gr7),gr8 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldsbi.cgs b/sim/testsuite/sim/frv/ldsbi.cgs new file mode 100644 index 00000000000..c90a129f317 --- /dev/null +++ b/sim/testsuite/sim/frv/ldsbi.cgs @@ -0,0 +1,24 @@ +# frv testcase for ldsbi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldsbi +ldsbi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + ldsbi @(sp,0),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + + ldsbi @(sp,1),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + ldsbi @(sp,-1),gr8 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldsbu.cgs b/sim/testsuite/sim/frv/ldsbu.cgs new file mode 100644 index 00000000000..976cee8204c --- /dev/null +++ b/sim/testsuite/sim/frv/ldsbu.cgs @@ -0,0 +1,40 @@ +# frv testcase for ldsbu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldsbu +ldsbu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + ldsbu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + ldsbu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldsbu @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -3,sp + set_mem_limmed 0x0000,0x00da,sp + set_gr_immed 3,gr7 + ldsbu @(sp,gr7),sp + test_gr_limmed 0xffff,0xffda,sp + + pass diff --git a/sim/testsuite/sim/frv/ldsh.cgs b/sim/testsuite/sim/frv/ldsh.cgs new file mode 100644 index 00000000000..c526f39c71d --- /dev/null +++ b/sim/testsuite/sim/frv/ldsh.cgs @@ -0,0 +1,27 @@ +# frv testcase for ldsh @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldsh +ldsh: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + ldsh @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + + set_gr_immed 2,gr7 + ldsh @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + ldsh @(sp,gr7),gr8 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldshi.cgs b/sim/testsuite/sim/frv/ldshi.cgs new file mode 100644 index 00000000000..69f99f13e83 --- /dev/null +++ b/sim/testsuite/sim/frv/ldshi.cgs @@ -0,0 +1,24 @@ +# frv testcase for ldshi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldshi +ldshi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + ldshi @(sp,0),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + + ldshi @(sp,2),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + ldshi @(sp,-2),gr8 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldshu.cgs b/sim/testsuite/sim/frv/ldshu.cgs new file mode 100644 index 00000000000..f1b8c23c5ea --- /dev/null +++ b/sim/testsuite/sim/frv/ldshu.cgs @@ -0,0 +1,39 @@ +# frv testcase for ldshu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldshu +ldshu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + ldshu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + ldshu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + ldshu @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0x0000,0xdead,sp + set_gr_immed 2,gr7 + ldshu @(sp,gr7),sp + test_gr_limmed 0xffff,0xdead,sp + + pass diff --git a/sim/testsuite/sim/frv/ldu.cgs b/sim/testsuite/sim/frv/ldu.cgs new file mode 100644 index 00000000000..b7f2e34aaaf --- /dev/null +++ b/sim/testsuite/sim/frv/ldu.cgs @@ -0,0 +1,39 @@ +# frv testcase for ldu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldu +ldu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + ldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + ldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldu @(sp,gr7),sp + test_gr_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/ldub.cgs b/sim/testsuite/sim/frv/ldub.cgs new file mode 100644 index 00000000000..1e192542a22 --- /dev/null +++ b/sim/testsuite/sim/frv/ldub.cgs @@ -0,0 +1,27 @@ +# frv testcase for ldub @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldub +ldub: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + ldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + + set_gr_immed 1,gr7 + ldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldubi.cgs b/sim/testsuite/sim/frv/ldubi.cgs new file mode 100644 index 00000000000..4c40beebc5e --- /dev/null +++ b/sim/testsuite/sim/frv/ldubi.cgs @@ -0,0 +1,24 @@ +# frv testcase for ldubi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldubi +ldubi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + ldubi @(sp,0),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + + ldubi @(sp,1),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + ldubi @(sp,-1),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldubu.cgs b/sim/testsuite/sim/frv/ldubu.cgs new file mode 100644 index 00000000000..8c99ab072a5 --- /dev/null +++ b/sim/testsuite/sim/frv/ldubu.cgs @@ -0,0 +1,39 @@ +# frv testcase for ldubu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldubu +ldubu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + ldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + ldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + + inc_gr_immed -3,sp + set_mem_limmed 0xffff,0xffda,sp + set_gr_immed 3,gr7 + ldubu @(sp,gr7),sp + test_gr_limmed 0x0000,0x00da,sp + + pass diff --git a/sim/testsuite/sim/frv/lduh.cgs b/sim/testsuite/sim/frv/lduh.cgs new file mode 100644 index 00000000000..24c3bac4b40 --- /dev/null +++ b/sim/testsuite/sim/frv/lduh.cgs @@ -0,0 +1,27 @@ +# frv testcase for lduh @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lduh +lduh: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + lduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + + set_gr_immed 2,gr7 + lduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + lduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/lduhi.cgs b/sim/testsuite/sim/frv/lduhi.cgs new file mode 100644 index 00000000000..b9896d62f58 --- /dev/null +++ b/sim/testsuite/sim/frv/lduhi.cgs @@ -0,0 +1,24 @@ +# frv testcase for lduhi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lduhi +lduhi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + lduhi @(sp,0),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + + lduhi @(sp,2),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + lduhi @(sp,-2),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/lduhu.cgs b/sim/testsuite/sim/frv/lduhu.cgs new file mode 100644 index 00000000000..52faecf6234 --- /dev/null +++ b/sim/testsuite/sim/frv/lduhu.cgs @@ -0,0 +1,39 @@ +# frv testcase for lduhu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lduhu +lduhu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + lduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + lduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + lduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0xdead,sp + set_gr_immed 2,gr7 + lduhu @(sp,gr7),sp + test_gr_limmed 0x0000,0xdead,sp + + pass diff --git a/sim/testsuite/sim/frv/lrbranch.pcgs b/sim/testsuite/sim/frv/lrbranch.pcgs new file mode 100644 index 00000000000..a3d1c2e9529 --- /dev/null +++ b/sim/testsuite/sim/frv/lrbranch.pcgs @@ -0,0 +1,51 @@ +# frv parallel testcase for lr branching +# mach: fr500 frv + + .include "testutils.inc" + + start + + .global lrbranch +lrbranch: + ; Both conditions true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x4 0 + bcgelr.p icc0,0,0 + bra ok4 + fail +ok1: + test_spr_immed 127,LCR + + ; Only first condition true + set_spr_immed 128,lcr + set_spr_addr ok2,lr + set_icc 0x0 0 + bcgelr.p icc0,0,0 + bno + fail +ok2: + test_spr_immed 127,LCR + + ; Only second condition true + set_spr_immed 128,lcr + set_spr_addr ok3,lr + set_icc 0x8 0 + bcgelr.p icc0,0,0 + bra ok3 + fail +ok3: + test_spr_immed 127,LCR + + ; Both conditions false + set_spr_immed 128,lcr + set_spr_addr ok4,lr + set_icc 0x0 0 + bceqlr.p icc0,0,0 + bno + test_spr_immed 127,LCR + + pass + +ok4: + fail diff --git a/sim/testsuite/sim/frv/mabshs.cgs b/sim/testsuite/sim/frv/mabshs.cgs new file mode 100644 index 00000000000..29b25328732 --- /dev/null +++ b/sim/testsuite/sim/frv/mabshs.cgs @@ -0,0 +1,67 @@ +# frv testcase for mabshs $FRj,$FRk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mabshs +mabshs: + set_fr_iimmed 0x0000,0x0000,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x0000,0x0000,fr11 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0xffff,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x0001,0x0001,fr11 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7fff,0x8001,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x7fff,0x7fff,fr11 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7fff,0x8000,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x7fff,0x7fff,fr11 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8000,0x7fff,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x7fff,0x7fff,fr11 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + mabshs.p fr10,fr12 + mabshs fr11,fr13 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/maddaccs.cgs b/sim/testsuite/sim/frv/maddaccs.cgs new file mode 100644 index 00000000000..aa178fedb4f --- /dev/null +++ b/sim/testsuite/sim/frv/maddaccs.cgs @@ -0,0 +1,131 @@ +# frv testcase for maddaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "testutils.inc" + + start + + .global maddaccs +maddaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0xdead,0xbeef,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0xbeef,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x2345,0x6789,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + maddaccs.p acc0,acc1 + maddaccs acc2,acc3 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/maddhss.cgs b/sim/testsuite/sim/frv/maddhss.cgs new file mode 100644 index 00000000000..c07c35f4ed8 --- /dev/null +++ b/sim/testsuite/sim/frv/maddhss.cgs @@ -0,0 +1,100 @@ +# frv testcase for maddhss $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global maddhss +maddhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x1233,0x5677,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maddhss fr10,fr11,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maddhss.p fr10,fr10,fr12 + maddhss fr11,fr11,fr13 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/maddhus.cgs b/sim/testsuite/sim/frv/maddhus.cgs new file mode 100644 index 00000000000..455d3e8e21d --- /dev/null +++ b/sim/testsuite/sim/frv/maddhus.cgs @@ -0,0 +1,89 @@ +# frv testcase for maddhus $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global maddhus +maddhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0x8000,0x7fff,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + maddhus.p fr10,fr10,fr12 + maddhus fr11,fr11,fr13 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0xffff,0xffff,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/mand.cgs b/sim/testsuite/sim/frv/mand.cgs new file mode 100644 index 00000000000..c6aa993fa0a --- /dev/null +++ b/sim/testsuite/sim/frv/mand.cgs @@ -0,0 +1,23 @@ +# frv testcase for mand $FRinti,$FRintj,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mand +mand: + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + mand fr7,fr8,fr8 + test_fr_iimmed 0,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + mand fr7,fr8,fr8 + test_fr_iimmed 0xaaaa0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + mand fr7,fr8,fr8 + test_fr_iimmed 0x0000aaaa,fr8 + + pass diff --git a/sim/testsuite/sim/frv/masaccs.cgs b/sim/testsuite/sim/frv/masaccs.cgs new file mode 100644 index 00000000000..7369a71192f --- /dev/null +++ b/sim/testsuite/sim/frv/masaccs.cgs @@ -0,0 +1,151 @@ +# frv testcase for masaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "testutils.inc" + + start + + .global masaccs +masaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0xdead,0xbeef,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0xbeef,0xdead,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0x4111,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x2345,0x6789,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xfffc,0x7ffd,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0003,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + masaccs.p acc0,acc0 + masaccs acc2,acc2 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + + pass diff --git a/sim/testsuite/sim/frv/maveh.cgs b/sim/testsuite/sim/frv/maveh.cgs new file mode 100644 index 00000000000..d48ad72553b --- /dev/null +++ b/sim/testsuite/sim/frv/maveh.cgs @@ -0,0 +1,72 @@ +# frv testcase for maveh $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global maveh +maveh: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0001,0x0000,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xffff,0xfffe,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef56,0xdf77,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf77,0xef56,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a2,0x33c4,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0919,0x2b3b,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x3fff,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xbfff,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xbfff,0xbfff,fr12 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + pass diff --git a/sim/testsuite/sim/frv/mbtoh.cgs b/sim/testsuite/sim/frv/mbtoh.cgs new file mode 100644 index 00000000000..52895ad4a21 --- /dev/null +++ b/sim/testsuite/sim/frv/mbtoh.cgs @@ -0,0 +1,20 @@ +# frv testcase for mbtoh $FRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mbtoh +mbtoh: + set_fr_iimmed 0xdead,0xbeef,fr10 + mbtoh fr10,fr12 + test_fr_limmed 0x00de,0x00ad,fr12 + test_fr_limmed 0x00be,0x00ef,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + mbtoh fr10,fr12 + test_fr_limmed 0x0012,0x0034,fr12 + test_fr_limmed 0x0056,0x0078,fr13 + + pass diff --git a/sim/testsuite/sim/frv/mbtohe.cgs b/sim/testsuite/sim/frv/mbtohe.cgs new file mode 100644 index 00000000000..1e978ec59e4 --- /dev/null +++ b/sim/testsuite/sim/frv/mbtohe.cgs @@ -0,0 +1,24 @@ +# frv testcase for mbtohe $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + start + + .global mbtohe +mbtohe: + set_fr_iimmed 0xdead,0xbeef,fr10 + mbtohe fr10,fr12 + test_fr_limmed 0x00de,0x00de,fr12 + test_fr_limmed 0x00ad,0x00ad,fr13 + test_fr_limmed 0x00be,0x00be,fr14 + test_fr_limmed 0x00ef,0x00ef,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + mbtohe fr10,fr12 + test_fr_limmed 0x0012,0x0012,fr12 + test_fr_limmed 0x0034,0x0034,fr13 + test_fr_limmed 0x0056,0x0056,fr14 + test_fr_limmed 0x0078,0x0078,fr15 + + pass diff --git a/sim/testsuite/sim/frv/mclracc.cgs b/sim/testsuite/sim/frv/mclracc.cgs new file mode 100644 index 00000000000..7972b9a9cfc --- /dev/null +++ b/sim/testsuite/sim/frv/mclracc.cgs @@ -0,0 +1,79 @@ +# frv testcase for mclracc $ACC40k,$A +# mach: frv + + .include "testutils.inc" + + start + + .global mclracc +mclracc: + set_accg_immed 0xff,accg0 + set_acc_immed -1,acc0 + set_accg_immed 0xff,accg8 + set_acc_immed -1,acc8 + set_accg_immed 0xff,accg31 + set_acc_immed -1,acc31 + set_accg_immed 0xff,accg62 + set_acc_immed -1,acc62 + + mclracc acc63,0 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg8 + test_acc_immed -1,acc8 + test_accg_immed 0xff,accg31 + test_acc_immed -1,acc31 + test_accg_immed 0xff,accg62 + test_acc_immed -1,acc62 + + mclracc acc63,1 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg8 + test_acc_immed -1,acc8 + test_accg_immed 0xff,accg31 + test_acc_immed -1,acc31 + test_accg_immed 0xff,accg62 + test_acc_immed -1,acc62 + + mclracc acc31,0 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg8 + test_acc_immed -1,acc8 + test_accg_immed 0,accg31 + test_acc_immed 0,acc31 + test_accg_immed 0xff,accg62 + test_acc_immed -1,acc62 + + mclracc acc62,1 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg8 + test_acc_immed -1,acc8 + test_accg_immed 0,accg31 + test_acc_immed 0,acc31 + test_accg_immed 0,accg62 + test_acc_immed 0,acc62 + + mclracc acc0,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0xff,accg8 + test_acc_immed -1,acc8 + test_accg_immed 0,accg31 + test_acc_immed 0,acc31 + test_accg_immed 0,accg62 + test_acc_immed 0,acc62 + + mclracc acc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg8 + test_acc_immed 0,acc8 + test_accg_immed 0,accg31 + test_acc_immed 0,acc31 + test_accg_immed 0,accg62 + test_acc_immed 0,acc62 + + pass diff --git a/sim/testsuite/sim/frv/mcmpsh.cgs b/sim/testsuite/sim/frv/mcmpsh.cgs new file mode 100644 index 00000000000..50e986d0406 --- /dev/null +++ b/sim/testsuite/sim/frv/mcmpsh.cgs @@ -0,0 +1,138 @@ +# frv testcase for mcmpsh $FRi,$FRj,$FCCk +# mach: all + + .include "testutils.inc" + + start + + .global mcmpsh +mcmpsh: + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + pass diff --git a/sim/testsuite/sim/frv/mcmpuh.cgs b/sim/testsuite/sim/frv/mcmpuh.cgs new file mode 100644 index 00000000000..a6670b736f7 --- /dev/null +++ b/sim/testsuite/sim/frv/mcmpuh.cgs @@ -0,0 +1,138 @@ +# frv testcase for mcmpuh $FRi,$FRj,$FCCk +# mach: all + + .include "testutils.inc" + + start + + .global mcmpuh +mcmpuh: + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + pass diff --git a/sim/testsuite/sim/frv/mcop1.cgs b/sim/testsuite/sim/frv/mcop1.cgs new file mode 100644 index 00000000000..5405456f51f --- /dev/null +++ b/sim/testsuite/sim/frv/mcop1.cgs @@ -0,0 +1,40 @@ +# frv testcase for mcop1 $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + start + + .global mcop1 +mcop1: + mcop1.p fr19,fr12,fr13 ; mp_exception: not-implemented + mcop1 fr20,fr14,fr18 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop1.p fr19,fr12,fr13 ; mp_exception: not-implemented + mcop1 fr20,fr14,fr18 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop1 fr19,fr12,fr13 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop1 fr19,fr12,fr13 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + pass diff --git a/sim/testsuite/sim/frv/mcop2.cgs b/sim/testsuite/sim/frv/mcop2.cgs new file mode 100644 index 00000000000..f423a3ef7f7 --- /dev/null +++ b/sim/testsuite/sim/frv/mcop2.cgs @@ -0,0 +1,40 @@ +# frv testcase for mcop2 $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + start + + .global mcop2 +mcop2: + mcop2.p fr19,fr12,fr13 ; mp_exception: not-implemented + mcop2 fr20,fr14,fr18 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop2.p fr19,fr12,fr13 ; mp_exception: not-implemented + mcop2 fr20,fr14,fr18 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop2 fr19,fr12,fr13 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop2 fr19,fr12,fr13 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + pass diff --git a/sim/testsuite/sim/frv/mcplhi.cgs b/sim/testsuite/sim/frv/mcplhi.cgs new file mode 100644 index 00000000000..172946d72ad --- /dev/null +++ b/sim/testsuite/sim/frv/mcplhi.cgs @@ -0,0 +1,53 @@ +# frv testcase for mcplhi $FRi,$s6,$FRk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mcplhi +mcplhi: + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x0,fr10 ; Shift by 0 + test_fr_iimmed 0xdead5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x1,fr10 ; Shift by 1 + test_fr_iimmed 0xbd5b5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x4,fr10 ; Shift by 4 + test_fr_iimmed 0xeadf5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0xc,fr10 ; Shift by 12 + test_fr_iimmed 0xdeef5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0xf,fr10 ; Shift by 15 + test_fr_iimmed 0xbeef5678,fr10 + + ; test again with truncated shift values + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x10,fr10 ; Shift by 0 + test_fr_iimmed 0xdead5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x21,fr10 ; Shift by 1 + test_fr_iimmed 0xbd5b5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x34,fr10 ; Shift by 4 + test_fr_iimmed 0xeadf5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x1c,fr10 ; Shift by 12 + test_fr_iimmed 0xdeef5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x2f,fr10 ; Shift by 15 + test_fr_iimmed 0xbeef5678,fr10 + + pass diff --git a/sim/testsuite/sim/frv/mcpli.cgs b/sim/testsuite/sim/frv/mcpli.cgs new file mode 100644 index 00000000000..3bf7e60f886 --- /dev/null +++ b/sim/testsuite/sim/frv/mcpli.cgs @@ -0,0 +1,61 @@ +# frv testcase for mcpli $FRi,$s6,$FRk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mcpli +mcpli: + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x0,fr10 ; Shift by 0 + test_fr_iimmed 0xdeadbeef,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x1,fr10 ; Shift by 1 + test_fr_iimmed 0xbd5b7ddf,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x4,fr10 ; Shift by 4 + test_fr_iimmed 0xeadbeefd,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0xc,fr10 ; Shift by 12 + test_fr_iimmed 0xdbeefead,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x1c,fr10 ; Shift by 28 + test_fr_iimmed 0xfeefdead,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x1f,fr10 ; Shift by 31 + test_fr_iimmed 0xbeefdead,fr10 + + ; test again with truncated shift values + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x20,fr10 ; Shift by 0 + test_fr_iimmed 0xdeadbeef,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x21,fr10 ; Shift by 1 + test_fr_iimmed 0xbd5b7ddf,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x24,fr10 ; Shift by 4 + test_fr_iimmed 0xeadbeefd,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x2c,fr10 ; Shift by 12 + test_fr_iimmed 0xdbeefead,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x3c,fr10 ; Shift by 28 + test_fr_iimmed 0xfeefdead,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x3f,fr10 ; Shift by 31 + test_fr_iimmed 0xbeefdead,fr10 + + pass diff --git a/sim/testsuite/sim/frv/mcpxis.cgs b/sim/testsuite/sim/frv/mcpxis.cgs new file mode 100644 index 00000000000..c3dad019c90 --- /dev/null +++ b/sim/testsuite/sim/frv/mcpxis.cgs @@ -0,0 +1,115 @@ +# frv testcase for mcpxis $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mcpxis +mcpxis: + ; Positive operands + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x3ff8,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xc000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -9,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xffff,fr7 ; 15 bit result + set_fr_iimmed 0xffff,0xfffe,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbfff,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8001,0x0000,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x8000,0x0000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + pass diff --git a/sim/testsuite/sim/frv/mcpxiu.cgs b/sim/testsuite/sim/frv/mcpxiu.cgs new file mode 100644 index 00000000000..198f0568c40 --- /dev/null +++ b/sim/testsuite/sim/frv/mcpxiu.cgs @@ -0,0 +1,76 @@ +# frv testcase for mcpxiu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mcpxiu +mcpxiu: + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 5,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7fff,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,2,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010001,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffb0003,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffc0002,acc0 + + pass diff --git a/sim/testsuite/sim/frv/mcpxrs.cgs b/sim/testsuite/sim/frv/mcpxrs.cgs new file mode 100644 index 00000000000..1d62a96e7dc --- /dev/null +++ b/sim/testsuite/sim/frv/mcpxrs.cgs @@ -0,0 +1,115 @@ +# frv testcase for mcpxrs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mcpxrs +mcpxrs: + ; Positive operands + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ff0,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -3,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbff0,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8006,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8000,0x8000,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x7fff,0x8000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + pass diff --git a/sim/testsuite/sim/frv/mcpxru.cgs b/sim/testsuite/sim/frv/mcpxru.cgs new file mode 100644 index 00000000000..8a543926e69 --- /dev/null +++ b/sim/testsuite/sim/frv/mcpxru.cgs @@ -0,0 +1,94 @@ +# frv testcase for mcpxru $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mcpxru +mcpxru: + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffd,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x0001ffff,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + mcpxru fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxru fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxru fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + pass diff --git a/sim/testsuite/sim/frv/mcut.cgs b/sim/testsuite/sim/frv/mcut.cgs new file mode 100644 index 00000000000..d6211ab7593 --- /dev/null +++ b/sim/testsuite/sim/frv/mcut.cgs @@ -0,0 +1,509 @@ +# frv testcase for mcut $ACC40i,$FRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mcut +mcut: + set_accg_immed 0xffffffe7,accg0 + set_acc_immed 0x89abcdef,acc0 + + set_fr_iimmed 0,0,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + set_fr_iimmed 0,1,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + set_fr_iimmed 0,2,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + set_fr_iimmed 0,3,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x3c4d5e6f,fr11 + + set_fr_iimmed 0,4,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x789abcde,fr11 + + set_fr_iimmed 0,5,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf13579bd,fr11 + + set_fr_iimmed 0,6,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe26af37b,fr11 + + set_fr_iimmed 0,7,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xc4d5e6f7,fr11 + + set_fr_iimmed 0,8,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x89abcdef,fr11 + + set_fr_iimmed 0,9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x13579bde,fr11 + + set_fr_iimmed 0,10,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x26af37bc,fr11 + + set_fr_iimmed 0,11,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x4d5e6f78,fr11 + + set_fr_iimmed 0,12,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x9abcdef0,fr11 + + set_fr_iimmed 0,13,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x3579bde0,fr11 + + set_fr_iimmed 0,14,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x6af37bc0,fr11 + + set_fr_iimmed 0,15,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xd5e6f780,fr11 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xabcdef00,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x579bde00,fr11 + + set_fr_iimmed 0,18,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xaf37bc00,fr11 + + set_fr_iimmed 0,19,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x5e6f7800,fr11 + + set_fr_iimmed 0,20,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xbcdef000,fr11 + + set_fr_iimmed 0,21,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x79bde000,fr11 + + set_fr_iimmed 0,22,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf37bc000,fr11 + + set_fr_iimmed 0,23,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe6f78000,fr11 + + set_fr_iimmed 0,24,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xcdef0000,fr11 + + set_fr_iimmed 0,25,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x9bde0000,fr11 + + set_fr_iimmed 0,26,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x37bc0000,fr11 + + set_fr_iimmed 0,27,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x6f780000,fr11 + + set_fr_iimmed 0,28,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xdef00000,fr11 + + set_fr_iimmed 0,29,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xbde00000,fr11 + + set_fr_iimmed 0,30,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x7bc00000,fr11 + + set_fr_iimmed 0,31,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf7800000,fr11 + + set_fr_iimmed 0,31,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf7800000,fr11 + + set_fr_iimmed 0,64,fr10 ; same as 0 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + set_fr_iimmed 0xffff,0xffff,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf3c4d5e6,fr11 + + set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf9e26af3,fr11 + + set_fr_iimmed 0xffff,0xfffd,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfcf13579,fr11 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfe789abc,fr11 + + set_fr_iimmed 0xffff,0xfffb,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xff3c4d5e,fr11 + + set_fr_iimmed 0xffff,0xfffa,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xff9e26af,fr11 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffcf1357,fr11 + + set_fr_iimmed 0xffff,0xfff8,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffe789ab,fr11 + + set_fr_iimmed 0xffff,0xfff7,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfff3c4d5,fr11 + + set_fr_iimmed 0xffff,0xfff6,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfff9e26a,fr11 + + set_fr_iimmed 0xffff,0xfff5,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffcf135,fr11 + + set_fr_iimmed 0xffff,0xfff4,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffe789a,fr11 + + set_fr_iimmed 0xffff,0xfff3,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffff3c4d,fr11 + + set_fr_iimmed 0xffff,0xfff2,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffff9e26,fr11 + + set_fr_iimmed 0xffff,0xfff1,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffcf13,fr11 + + set_fr_iimmed 0xffff,0xfff0,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffe789,fr11 + + set_fr_iimmed 0xffff,0xffef,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffff3c4,fr11 + + set_fr_iimmed 0xffff,0xffee,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffff9e2,fr11 + + set_fr_iimmed 0xffff,0xffed,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffcf1,fr11 + + set_fr_iimmed 0xffff,0xffec,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffe78,fr11 + + set_fr_iimmed 0xffff,0xffeb,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffff3c,fr11 + + set_fr_iimmed 0xffff,0xffea,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffff9e,fr11 + + set_fr_iimmed 0xffff,0xffe9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffcf,fr11 + + set_fr_iimmed 0xffff,0xffe8,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffe7,fr11 + + set_fr_iimmed 0xffff,0xffe7,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffff3,fr11 + + set_fr_iimmed 0xffff,0xffe6,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffff9,fr11 + + set_fr_iimmed 0xffff,0xffe5,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffffc,fr11 + + set_fr_iimmed 0xffff,0xffe4,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffffe,fr11 + + set_fr_iimmed 0xffff,0xffe3,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe2,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe1,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe0,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0,32,fr10 ; same as -32 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_accg_immed 0xffffff67,accg0 + set_acc_immed 0x89abcdef,acc0 + + set_fr_iimmed 0xffff,0xffff,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x33c4d5e6,fr11 + + set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter + mcut acc0,fr10,fr11 + test_fr_iimmed 0x19e26af3,fr11 + + set_fr_iimmed 0xffff,0xfffd,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0cf13579,fr11 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x06789abc,fr11 + + set_fr_iimmed 0xffff,0xfffb,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x033c4d5e,fr11 + + set_fr_iimmed 0xffff,0xfffa,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x019e26af,fr11 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00cf1357,fr11 + + set_fr_iimmed 0xffff,0xfff8,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x006789ab,fr11 + + set_fr_iimmed 0xffff,0xfff7,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0033c4d5,fr11 + + set_fr_iimmed 0xffff,0xfff6,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0019e26a,fr11 + + set_fr_iimmed 0xffff,0xfff5,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x000cf135,fr11 + + set_fr_iimmed 0xffff,0xfff4,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0006789a,fr11 + + set_fr_iimmed 0xffff,0xfff3,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00033c4d,fr11 + + set_fr_iimmed 0xffff,0xfff2,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00019e26,fr11 + + set_fr_iimmed 0xffff,0xfff1,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0000cf13,fr11 + + set_fr_iimmed 0xffff,0xfff0,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00006789,fr11 + + set_fr_iimmed 0xffff,0xffef,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x000033c4,fr11 + + set_fr_iimmed 0xffff,0xffee,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x000019e2,fr11 + + set_fr_iimmed 0xffff,0xffed,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000cf1,fr11 + + set_fr_iimmed 0xffff,0xffec,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000678,fr11 + + set_fr_iimmed 0xffff,0xffeb,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0000033c,fr11 + + set_fr_iimmed 0xffff,0xffea,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0000019e,fr11 + + set_fr_iimmed 0xffff,0xffe9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x000000cf,fr11 + + set_fr_iimmed 0xffff,0xffe8,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000067,fr11 + + set_fr_iimmed 0xffff,0xffe7,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000033,fr11 + + set_fr_iimmed 0xffff,0xffe6,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000019,fr11 + + set_fr_iimmed 0xffff,0xffe5,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0000000c,fr11 + + set_fr_iimmed 0xffff,0xffe4,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000006,fr11 + + set_fr_iimmed 0xffff,0xffe3,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000003,fr11 + + set_fr_iimmed 0xffff,0xffe2,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000001,fr11 + + set_fr_iimmed 0xffff,0xffe1,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + set_fr_iimmed 0xffff,0xffe0,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + set_fr_iimmed 0,32,fr10 ; same as -32 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + ; Examples from the customer + set_accg_immed 0xffffffff,accg0 + set_acc_immed 0xffe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe0000000,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xc0000000,fr11 + + set_fr_iimmed 0,18,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0x7f,accg0 + set_acc_immed 0xffe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe0000000,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xc0000000,fr11 + + set_fr_iimmed 0,18,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0x08,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0xff,accg0 + set_acc_immed 0xefe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe0000000,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xc0000000,fr11 + + set_fr_iimmed 0,18,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0x80,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0xffffffaf,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfaf5a5a5,fr11 + + set_accg_immed 0x0000002f,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x005eb4b4,fr11 + + pass diff --git a/sim/testsuite/sim/frv/mcuti.cgs b/sim/testsuite/sim/frv/mcuti.cgs new file mode 100644 index 00000000000..e2e702fd79d --- /dev/null +++ b/sim/testsuite/sim/frv/mcuti.cgs @@ -0,0 +1,381 @@ +# frv testcase for mcuti $ACC40i,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mcuti +mcuti: + set_accg_immed 0xffffffe7,accg0 + set_acc_immed 0x89abcdef,acc0 + + mcuti acc0,0,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + mcuti acc0,1,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + mcuti acc0,2,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + set_fr_iimmed 0,3,fr10 + mcuti acc0,3,fr11 + test_fr_iimmed 0x3c4d5e6f,fr11 + + mcuti acc0,4,fr11 + test_fr_iimmed 0x789abcde,fr11 + + mcuti acc0,5,fr11 + test_fr_iimmed 0xf13579bd,fr11 + + mcuti acc0,6,fr11 + test_fr_iimmed 0xe26af37b,fr11 + + mcuti acc0,7,fr11 + test_fr_iimmed 0xc4d5e6f7,fr11 + + mcuti acc0,8,fr11 + test_fr_iimmed 0x89abcdef,fr11 + + mcuti acc0,9,fr11 + test_fr_iimmed 0x13579bde,fr11 + + mcuti acc0,10,fr11 + test_fr_iimmed 0x26af37bc,fr11 + + mcuti acc0,11,fr11 + test_fr_iimmed 0x4d5e6f78,fr11 + + mcuti acc0,12,fr11 + test_fr_iimmed 0x9abcdef0,fr11 + + mcuti acc0,13,fr11 + test_fr_iimmed 0x3579bde0,fr11 + + mcuti acc0,14,fr11 + test_fr_iimmed 0x6af37bc0,fr11 + + mcuti acc0,15,fr11 + test_fr_iimmed 0xd5e6f780,fr11 + + mcuti acc0,16,fr11 + test_fr_iimmed 0xabcdef00,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0x579bde00,fr11 + + mcuti acc0,18,fr11 + test_fr_iimmed 0xaf37bc00,fr11 + + mcuti acc0,19,fr11 + test_fr_iimmed 0x5e6f7800,fr11 + + mcuti acc0,20,fr11 + test_fr_iimmed 0xbcdef000,fr11 + + mcuti acc0,21,fr11 + test_fr_iimmed 0x79bde000,fr11 + + mcuti acc0,22,fr11 + test_fr_iimmed 0xf37bc000,fr11 + + mcuti acc0,23,fr11 + test_fr_iimmed 0xe6f78000,fr11 + + mcuti acc0,24,fr11 + test_fr_iimmed 0xcdef0000,fr11 + + mcuti acc0,25,fr11 + test_fr_iimmed 0x9bde0000,fr11 + + mcuti acc0,26,fr11 + test_fr_iimmed 0x37bc0000,fr11 + + mcuti acc0,27,fr11 + test_fr_iimmed 0x6f780000,fr11 + + mcuti acc0,28,fr11 + test_fr_iimmed 0xdef00000,fr11 + + mcuti acc0,29,fr11 + test_fr_iimmed 0xbde00000,fr11 + + mcuti acc0,30,fr11 + test_fr_iimmed 0x7bc00000,fr11 + + mcuti acc0,31,fr11 + test_fr_iimmed 0xf7800000,fr11 + + mcuti acc0,-1,fr11 + test_fr_iimmed 0xf3c4d5e6,fr11 + + mcuti acc0,-2,fr11 + test_fr_iimmed 0xf9e26af3,fr11 + + mcuti acc0,-3,fr11 + test_fr_iimmed 0xfcf13579,fr11 + + mcuti acc0,-4,fr11 + test_fr_iimmed 0xfe789abc,fr11 + + mcuti acc0,-5,fr11 + test_fr_iimmed 0xff3c4d5e,fr11 + + mcuti acc0,-6,fr11 + test_fr_iimmed 0xff9e26af,fr11 + + mcuti acc0,-7,fr11 + test_fr_iimmed 0xffcf1357,fr11 + + mcuti acc0,-8,fr11 + test_fr_iimmed 0xffe789ab,fr11 + + mcuti acc0,-9,fr11 + test_fr_iimmed 0xfff3c4d5,fr11 + + mcuti acc0,-10,fr11 + test_fr_iimmed 0xfff9e26a,fr11 + + mcuti acc0,-11,fr11 + test_fr_iimmed 0xfffcf135,fr11 + + mcuti acc0,-12,fr11 + test_fr_iimmed 0xfffe789a,fr11 + + mcuti acc0,-13,fr11 + test_fr_iimmed 0xffff3c4d,fr11 + + mcuti acc0,-14,fr11 + test_fr_iimmed 0xffff9e26,fr11 + + mcuti acc0,-15,fr11 + test_fr_iimmed 0xffffcf13,fr11 + + mcuti acc0,-16,fr11 + test_fr_iimmed 0xffffe789,fr11 + + mcuti acc0,-17,fr11 + test_fr_iimmed 0xfffff3c4,fr11 + + mcuti acc0,-18,fr11 + test_fr_iimmed 0xfffff9e2,fr11 + + mcuti acc0,-19,fr11 + test_fr_iimmed 0xfffffcf1,fr11 + + mcuti acc0,-20,fr11 + test_fr_iimmed 0xfffffe78,fr11 + + mcuti acc0,-21,fr11 + test_fr_iimmed 0xffffff3c,fr11 + + mcuti acc0,-22,fr11 + test_fr_iimmed 0xffffff9e,fr11 + + mcuti acc0,-23,fr11 + test_fr_iimmed 0xffffffcf,fr11 + + mcuti acc0,-24,fr11 + test_fr_iimmed 0xffffffe7,fr11 + + mcuti acc0,-25,fr11 + test_fr_iimmed 0xfffffff3,fr11 + + mcuti acc0,-26,fr11 + test_fr_iimmed 0xfffffff9,fr11 + + mcuti acc0,-27,fr11 + test_fr_iimmed 0xfffffffc,fr11 + + mcuti acc0,-28,fr11 + test_fr_iimmed 0xfffffffe,fr11 + + mcuti acc0,-29,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcuti acc0,-30,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcuti acc0,-31,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcuti acc0,-32,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_accg_immed 0xffffff67,accg0 + set_acc_immed 0x89abcdef,acc0 + + mcuti acc0,-1,fr11 + test_fr_iimmed 0x33c4d5e6,fr11 + + mcuti acc0,-2,fr11 + test_fr_iimmed 0x19e26af3,fr11 + + mcuti acc0,-3,fr11 + test_fr_iimmed 0x0cf13579,fr11 + + mcuti acc0,-4,fr11 + test_fr_iimmed 0x06789abc,fr11 + + mcuti acc0,-5,fr11 + test_fr_iimmed 0x033c4d5e,fr11 + + mcuti acc0,-6,fr11 + test_fr_iimmed 0x019e26af,fr11 + + mcuti acc0,-7,fr11 + test_fr_iimmed 0x00cf1357,fr11 + + mcuti acc0,-8,fr11 + test_fr_iimmed 0x006789ab,fr11 + + mcuti acc0,-9,fr11 + test_fr_iimmed 0x0033c4d5,fr11 + + mcuti acc0,-10,fr11 + test_fr_iimmed 0x0019e26a,fr11 + + mcuti acc0,-11,fr11 + test_fr_iimmed 0x000cf135,fr11 + + mcuti acc0,-12,fr11 + test_fr_iimmed 0x0006789a,fr11 + + mcuti acc0,-13,fr11 + test_fr_iimmed 0x00033c4d,fr11 + + mcuti acc0,-14,fr11 + test_fr_iimmed 0x00019e26,fr11 + + mcuti acc0,-15,fr11 + test_fr_iimmed 0x0000cf13,fr11 + + mcuti acc0,-16,fr11 + test_fr_iimmed 0x00006789,fr11 + + mcuti acc0,-17,fr11 + test_fr_iimmed 0x000033c4,fr11 + + mcuti acc0,-18,fr11 + test_fr_iimmed 0x000019e2,fr11 + + mcuti acc0,-19,fr11 + test_fr_iimmed 0x00000cf1,fr11 + + mcuti acc0,-20,fr11 + test_fr_iimmed 0x00000678,fr11 + + mcuti acc0,-21,fr11 + test_fr_iimmed 0x0000033c,fr11 + + mcuti acc0,-22,fr11 + test_fr_iimmed 0x0000019e,fr11 + + mcuti acc0,-23,fr11 + test_fr_iimmed 0x000000cf,fr11 + + mcuti acc0,-24,fr11 + test_fr_iimmed 0x00000067,fr11 + + mcuti acc0,-25,fr11 + test_fr_iimmed 0x00000033,fr11 + + mcuti acc0,-26,fr11 + test_fr_iimmed 0x00000019,fr11 + + mcuti acc0,-27,fr11 + test_fr_iimmed 0x0000000c,fr11 + + mcuti acc0,-28,fr11 + test_fr_iimmed 0x00000006,fr11 + + mcuti acc0,-29,fr11 + test_fr_iimmed 0x00000003,fr11 + + mcuti acc0,-30,fr11 + test_fr_iimmed 0x00000001,fr11 + + mcuti acc0,-31,fr11 + test_fr_iimmed 0x00000000,fr11 + + mcuti acc0,-32,fr11 + test_fr_iimmed 0x00000000,fr11 + + ; Examples from the customer + set_accg_immed 0xffffffff,accg0 + set_acc_immed 0xffe00000,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0xe0000000,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0xc0000000,fr11 + + mcuti acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0,accg0 + set_acc_immed 0x003fffff,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0x7f,accg0 + set_acc_immed 0xffe00000,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0xe0000000,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0xc0000000,fr11 + + mcuti acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0x08,accg0 + set_acc_immed 0x003fffff,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0xff,accg0 + set_acc_immed 0xefe00000,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0xe0000000,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0xc0000000,fr11 + + mcuti acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0x80,accg0 + set_acc_immed 0x003fffff,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0xffffffaf,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + mcuti acc0,-4,fr11 + test_fr_iimmed 0xfaf5a5a5,fr11 + + set_accg_immed 0x0000002f,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + mcuti acc0,-7,fr11 + test_fr_iimmed 0x005eb4b4,fr11 + + pass diff --git a/sim/testsuite/sim/frv/mcutss.cgs b/sim/testsuite/sim/frv/mcutss.cgs new file mode 100644 index 00000000000..efe3278864c --- /dev/null +++ b/sim/testsuite/sim/frv/mcutss.cgs @@ -0,0 +1,505 @@ +# frv testcase for mcutss $ACC40i,$FRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mcutss +mcutss: + set_accg_immed 0xffffffe7,accg0 + set_acc_immed 0x89abcdef,acc0 + + set_fr_iimmed 0,0,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + set_fr_iimmed 0,1,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + set_fr_iimmed 0,2,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + set_fr_iimmed 0,3,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,4,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,5,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,6,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,7,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,8,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,10,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,11,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,12,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,13,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,14,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,15,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,18,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,19,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,20,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,21,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,22,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,23,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,24,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,25,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,26,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,27,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,28,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,29,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,30,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,31,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,64,fr10 ; same as 0 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + set_fr_iimmed 0xffff,0xffff,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xf3c4d5e6,fr11 + + set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xf9e26af3,fr11 + + set_fr_iimmed 0xffff,0xfffd,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfcf13579,fr11 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfe789abc,fr11 + + set_fr_iimmed 0xffff,0xfffb,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xff3c4d5e,fr11 + + set_fr_iimmed 0xffff,0xfffa,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xff9e26af,fr11 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffcf1357,fr11 + + set_fr_iimmed 0xffff,0xfff8,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffe789ab,fr11 + + set_fr_iimmed 0xffff,0xfff7,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfff3c4d5,fr11 + + set_fr_iimmed 0xffff,0xfff6,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfff9e26a,fr11 + + set_fr_iimmed 0xffff,0xfff5,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffcf135,fr11 + + set_fr_iimmed 0xffff,0xfff4,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffe789a,fr11 + + set_fr_iimmed 0xffff,0xfff3,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffff3c4d,fr11 + + set_fr_iimmed 0xffff,0xfff2,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffff9e26,fr11 + + set_fr_iimmed 0xffff,0xfff1,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffcf13,fr11 + + set_fr_iimmed 0xffff,0xfff0,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffe789,fr11 + + set_fr_iimmed 0xffff,0xffef,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffff3c4,fr11 + + set_fr_iimmed 0xffff,0xffee,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffff9e2,fr11 + + set_fr_iimmed 0xffff,0xffed,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffcf1,fr11 + + set_fr_iimmed 0xffff,0xffec,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffe78,fr11 + + set_fr_iimmed 0xffff,0xffeb,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffff3c,fr11 + + set_fr_iimmed 0xffff,0xffea,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffff9e,fr11 + + set_fr_iimmed 0xffff,0xffe9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffcf,fr11 + + set_fr_iimmed 0xffff,0xffe8,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffe7,fr11 + + set_fr_iimmed 0xffff,0xffe7,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffff3,fr11 + + set_fr_iimmed 0xffff,0xffe6,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffff9,fr11 + + set_fr_iimmed 0xffff,0xffe5,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffffc,fr11 + + set_fr_iimmed 0xffff,0xffe4,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffffe,fr11 + + set_fr_iimmed 0xffff,0xffe3,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe2,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe1,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe0,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0,32,fr10 ; same as -32 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_accg_immed 0xffffff67,accg0 + set_acc_immed 0x89abcdef,acc0 + + set_fr_iimmed 0xffff,0xffff,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x33c4d5e6,fr11 + + set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x19e26af3,fr11 + + set_fr_iimmed 0xffff,0xfffd,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0cf13579,fr11 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x06789abc,fr11 + + set_fr_iimmed 0xffff,0xfffb,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x033c4d5e,fr11 + + set_fr_iimmed 0xffff,0xfffa,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x019e26af,fr11 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00cf1357,fr11 + + set_fr_iimmed 0xffff,0xfff8,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x006789ab,fr11 + + set_fr_iimmed 0xffff,0xfff7,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0033c4d5,fr11 + + set_fr_iimmed 0xffff,0xfff6,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0019e26a,fr11 + + set_fr_iimmed 0xffff,0xfff5,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x000cf135,fr11 + + set_fr_iimmed 0xffff,0xfff4,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0006789a,fr11 + + set_fr_iimmed 0xffff,0xfff3,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00033c4d,fr11 + + set_fr_iimmed 0xffff,0xfff2,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00019e26,fr11 + + set_fr_iimmed 0xffff,0xfff1,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0000cf13,fr11 + + set_fr_iimmed 0xffff,0xfff0,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00006789,fr11 + + set_fr_iimmed 0xffff,0xffef,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x000033c4,fr11 + + set_fr_iimmed 0xffff,0xffee,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x000019e2,fr11 + + set_fr_iimmed 0xffff,0xffed,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000cf1,fr11 + + set_fr_iimmed 0xffff,0xffec,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000678,fr11 + + set_fr_iimmed 0xffff,0xffeb,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0000033c,fr11 + + set_fr_iimmed 0xffff,0xffea,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0000019e,fr11 + + set_fr_iimmed 0xffff,0xffe9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x000000cf,fr11 + + set_fr_iimmed 0xffff,0xffe8,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000067,fr11 + + set_fr_iimmed 0xffff,0xffe7,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000033,fr11 + + set_fr_iimmed 0xffff,0xffe6,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000019,fr11 + + set_fr_iimmed 0xffff,0xffe5,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0000000c,fr11 + + set_fr_iimmed 0xffff,0xffe4,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000006,fr11 + + set_fr_iimmed 0xffff,0xffe3,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000003,fr11 + + set_fr_iimmed 0xffff,0xffe2,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000001,fr11 + + set_fr_iimmed 0xffff,0xffe1,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + set_fr_iimmed 0xffff,0xffe0,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + set_fr_iimmed 0,32,fr10 ; same as -32 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + ; Examples from the customer + set_accg_immed 0xffffffff,accg0 + set_acc_immed 0xffe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xe0000000,fr11 + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xc0000000,fr11 + + set_fr_iimmed 0,18,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0x7f,accg0 + set_acc_immed 0xffe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_fr_iimmed 0,18,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0x08,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0xff,accg0 + set_acc_immed 0xefe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_fr_iimmed 0,18,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0x80,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0xffffffaf,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfaf5a5a5,fr11 + + set_accg_immed 0x0000002f,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x005eb4b4,fr11 + + pass diff --git a/sim/testsuite/sim/frv/mcutssi.cgs b/sim/testsuite/sim/frv/mcutssi.cgs new file mode 100644 index 00000000000..739912f5131 --- /dev/null +++ b/sim/testsuite/sim/frv/mcutssi.cgs @@ -0,0 +1,380 @@ +# frv testcase for mcutssi $ACC40i,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mcutssi +mcutssi: + set_accg_immed 0xffffffe7,accg0 + set_acc_immed 0x89abcdef,acc0 + + mcutssi acc0,0,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + mcutssi acc0,1,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + mcutssi acc0,2,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + mcutssi acc0,3,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,4,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,5,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,6,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,7,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,8,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,9,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,10,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,11,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,12,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,13,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,14,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,15,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,19,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,20,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,21,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,22,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,23,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,24,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,25,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,26,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,27,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,28,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,29,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,30,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,31,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,-1,fr11 + test_fr_iimmed 0xf3c4d5e6,fr11 + + mcutssi acc0,-2,fr11 + test_fr_iimmed 0xf9e26af3,fr11 + + mcutssi acc0,-3,fr11 + test_fr_iimmed 0xfcf13579,fr11 + + mcutssi acc0,-4,fr11 + test_fr_iimmed 0xfe789abc,fr11 + + mcutssi acc0,-5,fr11 + test_fr_iimmed 0xff3c4d5e,fr11 + + mcutssi acc0,-6,fr11 + test_fr_iimmed 0xff9e26af,fr11 + + mcutssi acc0,-7,fr11 + test_fr_iimmed 0xffcf1357,fr11 + + mcutssi acc0,-8,fr11 + test_fr_iimmed 0xffe789ab,fr11 + + mcutssi acc0,-9,fr11 + test_fr_iimmed 0xfff3c4d5,fr11 + + mcutssi acc0,-10,fr11 + test_fr_iimmed 0xfff9e26a,fr11 + + mcutssi acc0,-11,fr11 + test_fr_iimmed 0xfffcf135,fr11 + + mcutssi acc0,-12,fr11 + test_fr_iimmed 0xfffe789a,fr11 + + mcutssi acc0,-13,fr11 + test_fr_iimmed 0xffff3c4d,fr11 + + mcutssi acc0,-14,fr11 + test_fr_iimmed 0xffff9e26,fr11 + + mcutssi acc0,-15,fr11 + test_fr_iimmed 0xffffcf13,fr11 + + mcutssi acc0,-16,fr11 + test_fr_iimmed 0xffffe789,fr11 + + mcutssi acc0,-17,fr11 + test_fr_iimmed 0xfffff3c4,fr11 + + mcutssi acc0,-18,fr11 + test_fr_iimmed 0xfffff9e2,fr11 + + mcutssi acc0,-19,fr11 + test_fr_iimmed 0xfffffcf1,fr11 + + mcutssi acc0,-20,fr11 + test_fr_iimmed 0xfffffe78,fr11 + + mcutssi acc0,-21,fr11 + test_fr_iimmed 0xffffff3c,fr11 + + mcutssi acc0,-22,fr11 + test_fr_iimmed 0xffffff9e,fr11 + + mcutssi acc0,-23,fr11 + test_fr_iimmed 0xffffffcf,fr11 + + mcutssi acc0,-24,fr11 + test_fr_iimmed 0xffffffe7,fr11 + + mcutssi acc0,-25,fr11 + test_fr_iimmed 0xfffffff3,fr11 + + mcutssi acc0,-26,fr11 + test_fr_iimmed 0xfffffff9,fr11 + + mcutssi acc0,-27,fr11 + test_fr_iimmed 0xfffffffc,fr11 + + mcutssi acc0,-28,fr11 + test_fr_iimmed 0xfffffffe,fr11 + + mcutssi acc0,-29,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcutssi acc0,-30,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcutssi acc0,-31,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcutssi acc0,-32,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_accg_immed 0xffffff67,accg0 + set_acc_immed 0x89abcdef,acc0 + + mcutssi acc0,-1,fr11 + test_fr_iimmed 0x33c4d5e6,fr11 + + mcutssi acc0,-2,fr11 + test_fr_iimmed 0x19e26af3,fr11 + + mcutssi acc0,-3,fr11 + test_fr_iimmed 0x0cf13579,fr11 + + mcutssi acc0,-4,fr11 + test_fr_iimmed 0x06789abc,fr11 + + mcutssi acc0,-5,fr11 + test_fr_iimmed 0x033c4d5e,fr11 + + mcutssi acc0,-6,fr11 + test_fr_iimmed 0x019e26af,fr11 + + mcutssi acc0,-7,fr11 + test_fr_iimmed 0x00cf1357,fr11 + + mcutssi acc0,-8,fr11 + test_fr_iimmed 0x006789ab,fr11 + + mcutssi acc0,-9,fr11 + test_fr_iimmed 0x0033c4d5,fr11 + + mcutssi acc0,-10,fr11 + test_fr_iimmed 0x0019e26a,fr11 + + mcutssi acc0,-11,fr11 + test_fr_iimmed 0x000cf135,fr11 + + mcutssi acc0,-12,fr11 + test_fr_iimmed 0x0006789a,fr11 + + mcutssi acc0,-13,fr11 + test_fr_iimmed 0x00033c4d,fr11 + + mcutssi acc0,-14,fr11 + test_fr_iimmed 0x00019e26,fr11 + + mcutssi acc0,-15,fr11 + test_fr_iimmed 0x0000cf13,fr11 + + mcutssi acc0,-16,fr11 + test_fr_iimmed 0x00006789,fr11 + + mcutssi acc0,-17,fr11 + test_fr_iimmed 0x000033c4,fr11 + + mcutssi acc0,-18,fr11 + test_fr_iimmed 0x000019e2,fr11 + + mcutssi acc0,-19,fr11 + test_fr_iimmed 0x00000cf1,fr11 + + mcutssi acc0,-20,fr11 + test_fr_iimmed 0x00000678,fr11 + + mcutssi acc0,-21,fr11 + test_fr_iimmed 0x0000033c,fr11 + + mcutssi acc0,-22,fr11 + test_fr_iimmed 0x0000019e,fr11 + + mcutssi acc0,-23,fr11 + test_fr_iimmed 0x000000cf,fr11 + + mcutssi acc0,-24,fr11 + test_fr_iimmed 0x00000067,fr11 + + mcutssi acc0,-25,fr11 + test_fr_iimmed 0x00000033,fr11 + + mcutssi acc0,-26,fr11 + test_fr_iimmed 0x00000019,fr11 + + mcutssi acc0,-27,fr11 + test_fr_iimmed 0x0000000c,fr11 + + mcutssi acc0,-28,fr11 + test_fr_iimmed 0x00000006,fr11 + + mcutssi acc0,-29,fr11 + test_fr_iimmed 0x00000003,fr11 + + mcutssi acc0,-30,fr11 + test_fr_iimmed 0x00000001,fr11 + + mcutssi acc0,-31,fr11 + test_fr_iimmed 0x00000000,fr11 + + mcutssi acc0,-32,fr11 + test_fr_iimmed 0x00000000,fr11 + + ; Examples from the customer + set_accg_immed 0xffffffff,accg0 + set_acc_immed 0xffe00000,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0xe0000000,fr11 + + mcutssi acc0,17,fr11 + test_fr_iimmed 0xc0000000,fr11 + + mcutssi acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0,accg0 + set_acc_immed 0x003fffff,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0x7f,accg0 + set_acc_immed 0xffe00000,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mcutssi acc0,18,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0x08,accg0 + set_acc_immed 0x003fffff,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0xff,accg0 + set_acc_immed 0xefe00000,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + mcutssi acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0x80,accg0 + set_acc_immed 0x003fffff,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0xffffffaf,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + mcutssi acc0,-4,fr11 + test_fr_iimmed 0xfaf5a5a5,fr11 + + set_accg_immed 0x0000002f,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + mcutssi acc0,-7,fr11 + test_fr_iimmed 0x005eb4b4,fr11 + + pass diff --git a/sim/testsuite/sim/frv/mdaddaccs.cgs b/sim/testsuite/sim/frv/mdaddaccs.cgs new file mode 100644 index 00000000000..553c4a773c7 --- /dev/null +++ b/sim/testsuite/sim/frv/mdaddaccs.cgs @@ -0,0 +1,102 @@ +# frv testcase for mdaddaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mdaddaccs +mdaddaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdead,0xbeef,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0xbeef,0xdead,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x2345,0x6789,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xfffffffe,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0002,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mdasaccs.cgs b/sim/testsuite/sim/frv/mdasaccs.cgs new file mode 100644 index 00000000000..0535b6295b2 --- /dev/null +++ b/sim/testsuite/sim/frv/mdasaccs.cgs @@ -0,0 +1,122 @@ +# frv testcase for mdasaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mdasaccs +mdasaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xdead,0xbeef,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0xbeef,0xdead,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x4111,0xdead,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x2345,0x6789,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x1234,0x5677,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x1234,0x5679,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xfffffffe,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0xa,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xfffc,0x7ffd,acc1 + test_accg_immed 0x80,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0003,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mdcutssi.cgs b/sim/testsuite/sim/frv/mdcutssi.cgs new file mode 100644 index 00000000000..93ca6fe25b1 --- /dev/null +++ b/sim/testsuite/sim/frv/mdcutssi.cgs @@ -0,0 +1,513 @@ +# frv testcase for mdcutssi $ACC40i,$s6,$FRk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mdcutssi +mdcutssi: + set_accg_immed 0xffffffe7,accg0 + set_acc_immed 0x89abcdef,acc0 + set_accg_immed 0xffffffe7,accg1 + set_acc_immed 0x89abcdef,acc1 + + mdcutssi acc0,0,fr10 + test_fr_iimmed 0xe789abcd,fr10 + test_fr_iimmed 0xe789abcd,fr11 + + mdcutssi acc0,1,fr10 + test_fr_iimmed 0xcf13579b,fr10 + test_fr_iimmed 0xcf13579b,fr11 + + mdcutssi acc0,2,fr10 + test_fr_iimmed 0x9e26af37,fr10 + test_fr_iimmed 0x9e26af37,fr11 + + mdcutssi acc0,3,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,4,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,5,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,6,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,7,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,8,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,9,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,10,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,11,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,12,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,13,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,14,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,15,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,18,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,19,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,20,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,21,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,22,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,23,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,24,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,25,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,26,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,27,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,28,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,29,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,30,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,31,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,-1,fr10 + test_fr_iimmed 0xf3c4d5e6,fr10 + test_fr_iimmed 0xf3c4d5e6,fr11 + + mdcutssi acc0,-2,fr10 + test_fr_iimmed 0xf9e26af3,fr10 + test_fr_iimmed 0xf9e26af3,fr11 + + mdcutssi acc0,-3,fr10 + test_fr_iimmed 0xfcf13579,fr10 + test_fr_iimmed 0xfcf13579,fr11 + + mdcutssi acc0,-4,fr10 + test_fr_iimmed 0xfe789abc,fr10 + test_fr_iimmed 0xfe789abc,fr11 + + mdcutssi acc0,-5,fr10 + test_fr_iimmed 0xff3c4d5e,fr10 + test_fr_iimmed 0xff3c4d5e,fr11 + + mdcutssi acc0,-6,fr10 + test_fr_iimmed 0xff9e26af,fr10 + test_fr_iimmed 0xff9e26af,fr11 + + mdcutssi acc0,-7,fr10 + test_fr_iimmed 0xffcf1357,fr10 + test_fr_iimmed 0xffcf1357,fr11 + + mdcutssi acc0,-8,fr10 + test_fr_iimmed 0xffe789ab,fr10 + test_fr_iimmed 0xffe789ab,fr11 + + mdcutssi acc0,-9,fr10 + test_fr_iimmed 0xfff3c4d5,fr10 + test_fr_iimmed 0xfff3c4d5,fr11 + + mdcutssi acc0,-10,fr10 + test_fr_iimmed 0xfff9e26a,fr10 + test_fr_iimmed 0xfff9e26a,fr11 + + mdcutssi acc0,-11,fr10 + test_fr_iimmed 0xfffcf135,fr10 + test_fr_iimmed 0xfffcf135,fr11 + + mdcutssi acc0,-12,fr10 + test_fr_iimmed 0xfffe789a,fr10 + test_fr_iimmed 0xfffe789a,fr11 + + mdcutssi acc0,-13,fr10 + test_fr_iimmed 0xffff3c4d,fr10 + test_fr_iimmed 0xffff3c4d,fr11 + + mdcutssi acc0,-14,fr10 + test_fr_iimmed 0xffff9e26,fr10 + test_fr_iimmed 0xffff9e26,fr11 + + mdcutssi acc0,-15,fr10 + test_fr_iimmed 0xffffcf13,fr10 + test_fr_iimmed 0xffffcf13,fr11 + + mdcutssi acc0,-16,fr10 + test_fr_iimmed 0xffffe789,fr10 + test_fr_iimmed 0xffffe789,fr11 + + mdcutssi acc0,-17,fr10 + test_fr_iimmed 0xfffff3c4,fr10 + test_fr_iimmed 0xfffff3c4,fr11 + + mdcutssi acc0,-18,fr10 + test_fr_iimmed 0xfffff9e2,fr10 + test_fr_iimmed 0xfffff9e2,fr11 + + mdcutssi acc0,-19,fr10 + test_fr_iimmed 0xfffffcf1,fr10 + test_fr_iimmed 0xfffffcf1,fr11 + + mdcutssi acc0,-20,fr10 + test_fr_iimmed 0xfffffe78,fr10 + test_fr_iimmed 0xfffffe78,fr11 + + mdcutssi acc0,-21,fr10 + test_fr_iimmed 0xffffff3c,fr10 + test_fr_iimmed 0xffffff3c,fr11 + + mdcutssi acc0,-22,fr10 + test_fr_iimmed 0xffffff9e,fr10 + test_fr_iimmed 0xffffff9e,fr11 + + mdcutssi acc0,-23,fr10 + test_fr_iimmed 0xffffffcf,fr10 + test_fr_iimmed 0xffffffcf,fr11 + + mdcutssi acc0,-24,fr10 + test_fr_iimmed 0xffffffe7,fr10 + test_fr_iimmed 0xffffffe7,fr11 + + mdcutssi acc0,-25,fr10 + test_fr_iimmed 0xfffffff3,fr10 + test_fr_iimmed 0xfffffff3,fr11 + + mdcutssi acc0,-26,fr10 + test_fr_iimmed 0xfffffff9,fr10 + test_fr_iimmed 0xfffffff9,fr11 + + mdcutssi acc0,-27,fr10 + test_fr_iimmed 0xfffffffc,fr10 + test_fr_iimmed 0xfffffffc,fr11 + + mdcutssi acc0,-28,fr10 + test_fr_iimmed 0xfffffffe,fr10 + test_fr_iimmed 0xfffffffe,fr11 + + mdcutssi acc0,-29,fr10 + test_fr_iimmed 0xffffffff,fr10 + test_fr_iimmed 0xffffffff,fr11 + + mdcutssi acc0,-30,fr10 + test_fr_iimmed 0xffffffff,fr10 + test_fr_iimmed 0xffffffff,fr11 + + mdcutssi acc0,-31,fr10 + test_fr_iimmed 0xffffffff,fr10 + test_fr_iimmed 0xffffffff,fr11 + + mdcutssi acc0,-32,fr10 + test_fr_iimmed 0xffffffff,fr10 + test_fr_iimmed 0xffffffff,fr11 + + set_accg_immed 0xffffff67,accg0 + set_acc_immed 0x89abcdef,acc0 + set_accg_immed 0xffffff67,accg1 + set_acc_immed 0x89abcdef,acc1 + + mdcutssi acc0,-1,fr10 + test_fr_iimmed 0x33c4d5e6,fr10 + test_fr_iimmed 0x33c4d5e6,fr11 + + mdcutssi acc0,-2,fr10 + test_fr_iimmed 0x19e26af3,fr10 + test_fr_iimmed 0x19e26af3,fr11 + + mdcutssi acc0,-3,fr10 + test_fr_iimmed 0x0cf13579,fr10 + test_fr_iimmed 0x0cf13579,fr11 + + mdcutssi acc0,-4,fr10 + test_fr_iimmed 0x06789abc,fr10 + test_fr_iimmed 0x06789abc,fr11 + + mdcutssi acc0,-5,fr10 + test_fr_iimmed 0x033c4d5e,fr10 + test_fr_iimmed 0x033c4d5e,fr11 + + mdcutssi acc0,-6,fr10 + test_fr_iimmed 0x019e26af,fr10 + test_fr_iimmed 0x019e26af,fr11 + + mdcutssi acc0,-7,fr10 + test_fr_iimmed 0x00cf1357,fr10 + test_fr_iimmed 0x00cf1357,fr11 + + mdcutssi acc0,-8,fr10 + test_fr_iimmed 0x006789ab,fr10 + test_fr_iimmed 0x006789ab,fr11 + + mdcutssi acc0,-9,fr10 + test_fr_iimmed 0x0033c4d5,fr10 + test_fr_iimmed 0x0033c4d5,fr11 + + mdcutssi acc0,-10,fr10 + test_fr_iimmed 0x0019e26a,fr10 + test_fr_iimmed 0x0019e26a,fr11 + + mdcutssi acc0,-11,fr10 + test_fr_iimmed 0x000cf135,fr10 + test_fr_iimmed 0x000cf135,fr11 + + mdcutssi acc0,-12,fr10 + test_fr_iimmed 0x0006789a,fr10 + test_fr_iimmed 0x0006789a,fr11 + + mdcutssi acc0,-13,fr10 + test_fr_iimmed 0x00033c4d,fr10 + test_fr_iimmed 0x00033c4d,fr11 + + mdcutssi acc0,-14,fr10 + test_fr_iimmed 0x00019e26,fr10 + test_fr_iimmed 0x00019e26,fr11 + + mdcutssi acc0,-15,fr10 + test_fr_iimmed 0x0000cf13,fr10 + test_fr_iimmed 0x0000cf13,fr11 + + mdcutssi acc0,-16,fr10 + test_fr_iimmed 0x00006789,fr10 + test_fr_iimmed 0x00006789,fr11 + + mdcutssi acc0,-17,fr10 + test_fr_iimmed 0x000033c4,fr10 + test_fr_iimmed 0x000033c4,fr11 + + mdcutssi acc0,-18,fr10 + test_fr_iimmed 0x000019e2,fr10 + test_fr_iimmed 0x000019e2,fr11 + + mdcutssi acc0,-19,fr10 + test_fr_iimmed 0x00000cf1,fr10 + test_fr_iimmed 0x00000cf1,fr11 + + mdcutssi acc0,-20,fr10 + test_fr_iimmed 0x00000678,fr10 + test_fr_iimmed 0x00000678,fr11 + + mdcutssi acc0,-21,fr10 + test_fr_iimmed 0x0000033c,fr10 + test_fr_iimmed 0x0000033c,fr11 + + mdcutssi acc0,-22,fr10 + test_fr_iimmed 0x0000019e,fr10 + test_fr_iimmed 0x0000019e,fr11 + + mdcutssi acc0,-23,fr10 + test_fr_iimmed 0x000000cf,fr10 + test_fr_iimmed 0x000000cf,fr11 + + mdcutssi acc0,-24,fr10 + test_fr_iimmed 0x00000067,fr10 + test_fr_iimmed 0x00000067,fr11 + + mdcutssi acc0,-25,fr10 + test_fr_iimmed 0x00000033,fr10 + test_fr_iimmed 0x00000033,fr11 + + mdcutssi acc0,-26,fr10 + test_fr_iimmed 0x00000019,fr10 + test_fr_iimmed 0x00000019,fr11 + + mdcutssi acc0,-27,fr10 + test_fr_iimmed 0x0000000c,fr10 + test_fr_iimmed 0x0000000c,fr11 + + mdcutssi acc0,-28,fr10 + test_fr_iimmed 0x00000006,fr10 + test_fr_iimmed 0x00000006,fr11 + + mdcutssi acc0,-29,fr10 + test_fr_iimmed 0x00000003,fr10 + test_fr_iimmed 0x00000003,fr11 + + mdcutssi acc0,-30,fr10 + test_fr_iimmed 0x00000001,fr10 + test_fr_iimmed 0x00000001,fr11 + + mdcutssi acc0,-31,fr10 + test_fr_iimmed 0x00000000,fr10 + test_fr_iimmed 0x00000000,fr11 + + mdcutssi acc0,-32,fr10 + test_fr_iimmed 0x00000000,fr10 + test_fr_iimmed 0x00000000,fr11 + + ; Examples from the customer + set_accg_immed 0xffffffff,accg0 + set_acc_immed 0xffe00000,acc0 + set_accg_immed 0xffffffff,accg1 + set_acc_immed 0xffe00000,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0xe0000000,fr10 + test_fr_iimmed 0xe0000000,fr11 + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0xc0000000,fr10 + test_fr_iimmed 0xc0000000,fr11 + + mdcutssi acc0,18,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0,accg0 + set_acc_immed 0x003fffff,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x003fffff,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x3fffff00,fr10 + test_fr_iimmed 0x3fffff00,fr11 + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x7ffffe00,fr10 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0x7f,accg0 + set_acc_immed 0xffe00000,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffe00000,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x7fffffff,fr10 ; saturated + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x7fffffff,fr10 ; saturated + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mdcutssi acc0,18,fr10 + test_fr_iimmed 0x7fffffff,fr10 ; saturated + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0x08,accg0 + set_acc_immed 0x003fffff,acc0 + set_accg_immed 0x08,accg1 + set_acc_immed 0x003fffff,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x7fffffff,fr10 ; saturated + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x7fffffff,fr10 ; saturated + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0xff,accg0 + set_acc_immed 0xefe00000,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xefe00000,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x80000000,fr10 ; saturated + test_fr_iimmed 0x80000000,fr11 ; saturated + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x80000000,fr10 ; saturated + test_fr_iimmed 0x80000000,fr11 ; saturated + + mdcutssi acc0,18,fr10 + test_fr_iimmed 0x80000000,fr10 ; saturated + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0x80,accg0 + set_acc_immed 0x003fffff,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0x003fffff,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x80000000,fr10 ; saturated + test_fr_iimmed 0x80000000,fr11 ; saturated + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x80000000,fr10 ; saturated + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0xffffffaf,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + set_accg_immed 0xffffffaf,accg1 + set_acc_immed 0x5a5a5a5a,acc1 + + mdcutssi acc0,-4,fr10 + test_fr_iimmed 0xfaf5a5a5,fr10 + test_fr_iimmed 0xfaf5a5a5,fr11 + + set_accg_immed 0x0000002f,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + set_accg_immed 0x0000002f,accg1 + set_acc_immed 0x5a5a5a5a,acc1 + + mdcutssi acc0,-7,fr10 + test_fr_iimmed 0x005eb4b4,fr10 + test_fr_iimmed 0x005eb4b4,fr11 + + pass diff --git a/sim/testsuite/sim/frv/mdpackh.cgs b/sim/testsuite/sim/frv/mdpackh.cgs new file mode 100644 index 00000000000..cbd0bc80008 --- /dev/null +++ b/sim/testsuite/sim/frv/mdpackh.cgs @@ -0,0 +1,18 @@ +# frv testcase for mdpackh $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global mdpackh +mdpackh: + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0xaaaa,0xbbbb,fr11 + set_fr_iimmed 0x1234,0x5678,fr12 + set_fr_iimmed 0xcccc,0xdddd,fr13 + mdpackh fr10,fr12,fr14 + test_fr_limmed 0xbeef,0x5678,fr14 + test_fr_limmed 0xbbbb,0xdddd,fr15 + + pass diff --git a/sim/testsuite/sim/frv/mdrotli.cgs b/sim/testsuite/sim/frv/mdrotli.cgs new file mode 100644 index 00000000000..75cddc5d5df --- /dev/null +++ b/sim/testsuite/sim/frv/mdrotli.cgs @@ -0,0 +1,34 @@ +# frv testcase for mdrotli $FRi,$s6,$FRk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mdrotli +mdrotli: + set_fr_iimmed 0,2,fr8 + set_fr_iimmed 0,2,fr9 + mdrotli fr8,-32,fr8 ; Shift by 0 + test_fr_iimmed 2,fr8 + test_fr_iimmed 2,fr9 + + set_fr_iimmed 0,2,fr8 + set_fr_iimmed 0,2,fr9 + mdrotli fr8,1,fr8 ; Shift by 1 + test_fr_iimmed 4,fr8 + test_fr_iimmed 4,fr9 + + set_fr_iimmed 0,1,fr8 + set_fr_iimmed 0,2,fr9 + mdrotli fr8,31,fr8 ; Shift by 31 + test_fr_iimmed 0x80000000,fr8 + test_fr_iimmed 1,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + mdrotli fr8,16,fr8 + test_fr_iimmed 0xbeefdead,fr8 + test_fr_iimmed 0xdeadbeef,fr9 + + pass diff --git a/sim/testsuite/sim/frv/mdsubaccs.cgs b/sim/testsuite/sim/frv/mdsubaccs.cgs new file mode 100644 index 00000000000..73d2e2dc899 --- /dev/null +++ b/sim/testsuite/sim/frv/mdsubaccs.cgs @@ -0,0 +1,102 @@ +# frv testcase for mdsubaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mdsubaccs +mdsubaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg2 + test_acc_limmed 0x4111,0xdead,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg2 + test_acc_limmed 0x1234,0x5679,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffffffe,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x00000002,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0x00000000,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mdunpackh.cgs b/sim/testsuite/sim/frv/mdunpackh.cgs new file mode 100644 index 00000000000..02870c8c14d --- /dev/null +++ b/sim/testsuite/sim/frv/mdunpackh.cgs @@ -0,0 +1,26 @@ +# frv testcase for mdunpackh $FRi,$FRj +# mach: frv + + .include "testutils.inc" + + start + + .global mdunpackh +mdunpackh: + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + mdunpackh fr10,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + test_fr_limmed 0x1234,0x1234,fr14 + test_fr_limmed 0x5678,0x5678,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + mdunpackh fr10,fr12 + test_fr_limmed 0x1234,0x1234,fr12 + test_fr_limmed 0x5678,0x5678,fr13 + test_fr_limmed 0xdead,0xdead,fr14 + test_fr_limmed 0xbeef,0xbeef,fr15 + + pass diff --git a/sim/testsuite/sim/frv/membar.cgs b/sim/testsuite/sim/frv/membar.cgs new file mode 100644 index 00000000000..aae1d1a8e21 --- /dev/null +++ b/sim/testsuite/sim/frv/membar.cgs @@ -0,0 +1,12 @@ +# frv testcase for membar +# mach: all + + .include "testutils.inc" + + start + + .global membar +membar: + membar + + pass diff --git a/sim/testsuite/sim/frv/mexpdhd.cgs b/sim/testsuite/sim/frv/mexpdhd.cgs new file mode 100644 index 00000000000..d5f95ce98bd --- /dev/null +++ b/sim/testsuite/sim/frv/mexpdhd.cgs @@ -0,0 +1,27 @@ +# frv testcase for mexpdhd $FRi,$s6,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global mexpdhd +mexpdhd: + set_fr_iimmed 0xdead,0xbeef,fr10 + mexpdhd fr10,0,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + mexpdhd fr10,1,fr12 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + mexpdhd fr10,62,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + mexpdhd fr10,63,fr12 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + pass diff --git a/sim/testsuite/sim/frv/mexpdhw.cgs b/sim/testsuite/sim/frv/mexpdhw.cgs new file mode 100644 index 00000000000..a13b0f24ce0 --- /dev/null +++ b/sim/testsuite/sim/frv/mexpdhw.cgs @@ -0,0 +1,23 @@ +# frv testcase for mexpdhw $FRi,$s6,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global mexpdhw +mexpdhw: + set_fr_iimmed 0xdead,0xbeef,fr10 + mexpdhw fr10,0,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + + mexpdhw fr10,1,fr12 + test_fr_limmed 0xbeef,0xbeef,fr12 + + mexpdhw fr10,62,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + + mexpdhw fr10,63,fr12 + test_fr_limmed 0xbeef,0xbeef,fr12 + + pass diff --git a/sim/testsuite/sim/frv/mhdseth.cgs b/sim/testsuite/sim/frv/mhdseth.cgs new file mode 100644 index 00000000000..cf5b49ba5d4 --- /dev/null +++ b/sim/testsuite/sim/frv/mhdseth.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhdseth $s5,$FRk +# mach: fr400 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhdseth 0,fr1 + test_fr_limmed 0x06ad,0x06ef,fr1 + + mhdseth 1,fr1 + test_fr_limmed 0x0ead,0x0eef,fr1 + + mhdseth 0xf,fr1 + test_fr_limmed 0x7ead,0x7eef,fr1 + + mhdseth -16,fr1 + test_fr_limmed 0x86ad,0x86ef,fr1 + + mhdseth -1,fr1 + test_fr_limmed 0xfead,0xfeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/mhdsets.cgs b/sim/testsuite/sim/frv/mhdsets.cgs new file mode 100644 index 00000000000..e1bf48b7c50 --- /dev/null +++ b/sim/testsuite/sim/frv/mhdsets.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhdsets $u12,$FRk +# mach: fr400 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhdsets 0,fr1 + test_fr_limmed 0x0000,0x0000,fr1 + + mhdsets 1,fr1 + test_fr_limmed 0x0001,0x0001,fr1 + + mhdsets 0x07ff,fr1 + test_fr_limmed 0x07ff,0x07ff,fr1 + + mhdsets -2048,fr1 + test_fr_limmed 0xf800,0xf800,fr1 + + mhdsets -1,fr1 + test_fr_limmed 0xffff,0xffff,fr1 + + pass diff --git a/sim/testsuite/sim/frv/mhsethih.cgs b/sim/testsuite/sim/frv/mhsethih.cgs new file mode 100644 index 00000000000..dee64a50704 --- /dev/null +++ b/sim/testsuite/sim/frv/mhsethih.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhsethih $s5,$FRk +# mach: fr400 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhsethih 0,fr1 + test_fr_limmed 0x06ad,0xbeef,fr1 + + mhsethih 1,fr1 + test_fr_limmed 0x0ead,0xbeef,fr1 + + mhsethih 0xf,fr1 + test_fr_limmed 0x7ead,0xbeef,fr1 + + mhsethih -16,fr1 + test_fr_limmed 0x86ad,0xbeef,fr1 + + mhsethih -1,fr1 + test_fr_limmed 0xfead,0xbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/mhsethis.cgs b/sim/testsuite/sim/frv/mhsethis.cgs new file mode 100644 index 00000000000..2354163af45 --- /dev/null +++ b/sim/testsuite/sim/frv/mhsethis.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhsethis $u12,$FRk +# mach: fr400 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhsethis 0,fr1 + test_fr_limmed 0x0000,0xbeef,fr1 + + mhsethis 1,fr1 + test_fr_limmed 0x0001,0xbeef,fr1 + + mhsethis 0x07ff,fr1 + test_fr_limmed 0x07ff,0xbeef,fr1 + + mhsethis -2048,fr1 + test_fr_limmed 0xf800,0xbeef,fr1 + + mhsethis -1,fr1 + test_fr_limmed 0xffff,0xbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/mhsetloh.cgs b/sim/testsuite/sim/frv/mhsetloh.cgs new file mode 100644 index 00000000000..66a1f237df2 --- /dev/null +++ b/sim/testsuite/sim/frv/mhsetloh.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhsetloh $s5,$FRk +# mach: fr400 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhsetloh 0,fr1 + test_fr_limmed 0xdead,0x06ef,fr1 + + mhsetloh 1,fr1 + test_fr_limmed 0xdead,0x0eef,fr1 + + mhsetloh 0xf,fr1 + test_fr_limmed 0xdead,0x7eef,fr1 + + mhsetloh -16,fr1 + test_fr_limmed 0xdead,0x86ef,fr1 + + mhsetloh -1,fr1 + test_fr_limmed 0xdead,0xfeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/mhsetlos.cgs b/sim/testsuite/sim/frv/mhsetlos.cgs new file mode 100644 index 00000000000..640fae3e13f --- /dev/null +++ b/sim/testsuite/sim/frv/mhsetlos.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhsetlos $u12,$FRk +# mach: fr400 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhsetlos 0,fr1 + test_fr_limmed 0xdead,0x0000,fr1 + + mhsetlos 1,fr1 + test_fr_limmed 0xdead,0x0001,fr1 + + mhsetlos 0x07ff,fr1 + test_fr_limmed 0xdead,0x07ff,fr1 + + mhsetlos -2048,fr1 + test_fr_limmed 0xdead,0xf800,fr1 + + mhsetlos -1,fr1 + test_fr_limmed 0xdead,0xffff,fr1 + + pass diff --git a/sim/testsuite/sim/frv/mhtob.cgs b/sim/testsuite/sim/frv/mhtob.cgs new file mode 100644 index 00000000000..efd83d73bde --- /dev/null +++ b/sim/testsuite/sim/frv/mhtob.cgs @@ -0,0 +1,25 @@ +# frv testcase for mhtob $FRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mhtob +mhtob: + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + mhtob fr10,fr12 + test_fr_limmed 0xadef,0x3478,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 ; saturation + set_fr_iimmed 0x1234,0x5678,fr11 + mhtob fr10,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 ; saturation + set_fr_iimmed 0x10ad,0x80ef,fr11 + mhtob fr10,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + + pass diff --git a/sim/testsuite/sim/frv/mmachs.cgs b/sim/testsuite/sim/frv/mmachs.cgs new file mode 100644 index 00000000000..2d776617be8 --- /dev/null +++ b/sim/testsuite/sim/frv/mmachs.cgs @@ -0,0 +1,259 @@ +# frv testcase for mmachs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mmachs +mmachs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0007,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0001,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xbffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xbffd,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffd,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc003,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc005,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc005,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3ffec006,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x7ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x7ffec006,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + mmachs fr7,fr8,acc0 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/sim/frv/mmachu.cgs b/sim/testsuite/sim/frv/mmachu.cgs new file mode 100644 index 00000000000..90b66c6e4bf --- /dev/null +++ b/sim/testsuite/sim/frv/mmachu.cgs @@ -0,0 +1,146 @@ +# frv testcase for mmachu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mmachu +mmachu: + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x00020006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00020006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x40010007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40010007,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x8001,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x8001,0x0007,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x7fff,0x0008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x7fff,0x0008,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mmrdhs.cgs b/sim/testsuite/sim/frv/mmrdhs.cgs new file mode 100644 index 00000000000..7feea695b97 --- /dev/null +++ b/sim/testsuite/sim/frv/mmrdhs.cgs @@ -0,0 +1,263 @@ +# frv testcase for mmrdhs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mmrdhs +mmrdhs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_immed -8,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x7ffa,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xfffe,0xfffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xfffe,0xfffa,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xbfff,0xfff9,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xbfff,0xfff9,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xbfff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xbfff,0xffff,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x0001,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x0001,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x0001,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x0001,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x4003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x4003,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0xc003,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4003,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x4003,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x3ffd,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x3ffb,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x3ffb,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_immed 0xc0013ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xc0013ffa,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_immed 0x80013ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0x80013ffa,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 0xffff,1,fr7 + set_fr_iimmed 1,0xffff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x8000,0x0000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0,1,fr7 + set_fr_iimmed 1,1,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/sim/frv/mmrdhu.cgs b/sim/testsuite/sim/frv/mmrdhu.cgs new file mode 100644 index 00000000000..7200a5814a6 --- /dev/null +++ b/sim/testsuite/sim/frv/mmrdhu.cgs @@ -0,0 +1,151 @@ +# frv testcase for mmrdhu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mmrdhu +mmrdhu: + set_accg_immed 0x80,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_immed 0xfffffffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xfffffffa,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_immed 0xfffffff8,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xfffffff8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_immed 0xfffffff8,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xfffffff8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0x7ffa,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xfffe,0xfffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xfffe,0xfffa,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xfffd,0xfffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xfffd,0xfffa,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xbffe,0xfff9,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xbffe,0xfff9,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0x7ffe,0xfff9,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0x7ffe,0xfff9,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7e,accg0 + test_acc_limmed 0x8000,0xfff8,acc0 + test_accg_immed 0x7e,accg1 + test_acc_limmed 0x8000,0xfff8,acc1 + + set_accg_immed 0,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0xffff,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mmulhs.cgs b/sim/testsuite/sim/frv/mmulhs.cgs new file mode 100644 index 00000000000..21045006dab --- /dev/null +++ b/sim/testsuite/sim/frv/mmulhs.cgs @@ -0,0 +1,141 @@ +# frv testcase for mmulhs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mmulhs +mmulhs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -2,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffe,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffe,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x8000,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mmulhu.cgs b/sim/testsuite/sim/frv/mmulhu.cgs new file mode 100644 index 00000000000..53e9b7062f5 --- /dev/null +++ b/sim/testsuite/sim/frv/mmulhu.cgs @@ -0,0 +1,82 @@ +# frv testcase for mmulhu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mmulhu +mmulhu: + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00010000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mmulxhs.cgs b/sim/testsuite/sim/frv/mmulxhs.cgs new file mode 100644 index 00000000000..449becfb4d9 --- /dev/null +++ b/sim/testsuite/sim/frv/mmulxhs.cgs @@ -0,0 +1,141 @@ +# frv testcase for mmulxhs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mmulxhs +mmulxhs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 4,acc0 + test_accg_immed 0,accg1 + test_acc_immed 9,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x4000,2,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -2,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffe,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffe,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x8000,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mmulxhu.cgs b/sim/testsuite/sim/frv/mmulxhu.cgs new file mode 100644 index 00000000000..866b64e50f4 --- /dev/null +++ b/sim/testsuite/sim/frv/mmulxhu.cgs @@ -0,0 +1,82 @@ +# frv testcase for mmulxhu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mmulxhu +mmulxhu: + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x4000,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 0x8000,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00010000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mnop.cgs b/sim/testsuite/sim/frv/mnop.cgs new file mode 100644 index 00000000000..54dda66b94c --- /dev/null +++ b/sim/testsuite/sim/frv/mnop.cgs @@ -0,0 +1,12 @@ +# frv testcase for mnop +# mach: all + + .include "testutils.inc" + + start + + .global mnop +mnop: + mnop + + pass diff --git a/sim/testsuite/sim/frv/mnot.cgs b/sim/testsuite/sim/frv/mnot.cgs new file mode 100644 index 00000000000..3a90781a0e8 --- /dev/null +++ b/sim/testsuite/sim/frv/mnot.cgs @@ -0,0 +1,18 @@ +# frv testcase for mnot $FRintj,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mnot +mnot: + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + mnot fr7,fr7 + test_fr_iimmed 0x55555555,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + mnot fr7,fr7 + test_fr_iimmed 0x21524110,fr7 + + pass diff --git a/sim/testsuite/sim/frv/mor.cgs b/sim/testsuite/sim/frv/mor.cgs new file mode 100644 index 00000000000..72feaffb64d --- /dev/null +++ b/sim/testsuite/sim/frv/mor.cgs @@ -0,0 +1,25 @@ +# frv testcase for mor $FRinti,$FRintj,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mor +mor: + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + mor fr7,fr8,fr8 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + mor fr7,fr8,fr8 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + mor fr7,fr8,fr8 + test_fr_iimmed 0xdeadbeef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/mov.cgs b/sim/testsuite/sim/frv/mov.cgs new file mode 100644 index 00000000000..8a077eb5e54 --- /dev/null +++ b/sim/testsuite/sim/frv/mov.cgs @@ -0,0 +1,18 @@ +# frv testcase for mov $GRi,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ori +ori: + set_gr_immed 0xdeadbeef,gr7 + set_gr_immed 0xbeefdead,gr8 + set_icc 0x08,0 + mov gr7,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0xdeadbeef,gr7 + test_gr_immed 0xdeadbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/movfg.cgs b/sim/testsuite/sim/frv/movfg.cgs new file mode 100644 index 00000000000..c3da00ec16b --- /dev/null +++ b/sim/testsuite/sim/frv/movfg.cgs @@ -0,0 +1,16 @@ +# frv testcase for movfg $FRk,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global movfg +movfg: + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + movfg fr8,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/movfgd.cgs b/sim/testsuite/sim/frv/movfgd.cgs new file mode 100644 index 00000000000..cc2d60de0ff --- /dev/null +++ b/sim/testsuite/sim/frv/movfgd.cgs @@ -0,0 +1,20 @@ +# frv testcase for movfgd $FRk,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global movfgd +movfgd: + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + movfgd fr8,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + pass diff --git a/sim/testsuite/sim/frv/movfgq.cgs b/sim/testsuite/sim/frv/movfgq.cgs new file mode 100644 index 00000000000..b3a90e817ad --- /dev/null +++ b/sim/testsuite/sim/frv/movfgq.cgs @@ -0,0 +1,29 @@ +# frv testcase for movfgq $FRk,$GRj +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global movfgq +movfgq: + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + set_gr_limmed 0,0,gr10 + set_gr_limmed 0,0,gr11 + movfgq fr8,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_fr_limmed 0x1234,0x5678,fr10 + test_fr_limmed 0x9abc,0xdef0,fr11 + + pass diff --git a/sim/testsuite/sim/frv/movgf.cgs b/sim/testsuite/sim/frv/movgf.cgs new file mode 100644 index 00000000000..40fae33f072 --- /dev/null +++ b/sim/testsuite/sim/frv/movgf.cgs @@ -0,0 +1,16 @@ +# frv testcase for movgf $GRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global movgf +movgf: + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + movgf gr8,fr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/movgfd.cgs b/sim/testsuite/sim/frv/movgfd.cgs new file mode 100644 index 00000000000..df844ccf6cb --- /dev/null +++ b/sim/testsuite/sim/frv/movgfd.cgs @@ -0,0 +1,20 @@ +# frv testcase for movgfd $GRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global movgfd +movgfd: + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + movgfd gr8,fr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + pass diff --git a/sim/testsuite/sim/frv/movgfq.cgs b/sim/testsuite/sim/frv/movgfq.cgs new file mode 100644 index 00000000000..0196133496a --- /dev/null +++ b/sim/testsuite/sim/frv/movgfq.cgs @@ -0,0 +1,29 @@ +# frv testcase for movgfq $GRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global movgfq +movgfq: + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + set_fr_iimmed 0,0,fr10 + set_fr_iimmed 0,0,fr11 + movgfq gr8,fr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_fr_limmed 0x1234,0x5678,fr10 + test_fr_limmed 0x9abc,0xdef0,fr11 + + pass diff --git a/sim/testsuite/sim/frv/movgs.cgs b/sim/testsuite/sim/frv/movgs.cgs new file mode 100644 index 00000000000..b9f8a0af274 --- /dev/null +++ b/sim/testsuite/sim/frv/movgs.cgs @@ -0,0 +1,22 @@ +# frv testcase for movgs $GRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global movgs +movgs: + set_gr_limmed 0xdead,0xbeef,gr8 + and_spr_immed 0,lcr + movgs gr8,lcr + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,lcr + + ; try alternate names for lcr + and_spr_immed 0,273 + movgs gr8,lcr ; lcr is spr number 273 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[273] + + pass diff --git a/sim/testsuite/sim/frv/movsg.cgs b/sim/testsuite/sim/frv/movsg.cgs new file mode 100644 index 00000000000..b26dbc18a57 --- /dev/null +++ b/sim/testsuite/sim/frv/movsg.cgs @@ -0,0 +1,16 @@ +# frv testcase for movsg $FRk,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global movsg +movsg: + set_spr_limmed 0xdead,0xbeef,lcr + set_gr_limmed 0,0,gr8 + movsg lcr,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,lcr + + pass diff --git a/sim/testsuite/sim/frv/mpackh.cgs b/sim/testsuite/sim/frv/mpackh.cgs new file mode 100644 index 00000000000..5a87cc6b5d0 --- /dev/null +++ b/sim/testsuite/sim/frv/mpackh.cgs @@ -0,0 +1,15 @@ +# frv testcase for mpackh $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global mpackh +mpackh: + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + mpackh fr10,fr11,fr12 + test_fr_limmed 0xbeef,0x5678,fr12 + + pass diff --git a/sim/testsuite/sim/frv/mqcpxis.cgs b/sim/testsuite/sim/frv/mqcpxis.cgs new file mode 100644 index 00000000000..397f5335d21 --- /dev/null +++ b/sim/testsuite/sim/frv/mqcpxis.cgs @@ -0,0 +1,103 @@ +# frv testcase for mqcpxis $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mqcpxis +mqcpxis: + ; Positive operands + set_fr_iimmed 2,4,fr8 ; multiply small numbers + set_fr_iimmed 5,3,fr10 + set_fr_iimmed 3,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result + set_fr_iimmed 0x0001,2,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7fff,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x2000,2,fr10 + set_fr_iimmed 0x7fff,0x0000,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xc000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr10 + set_fr_iimmed 0xfffe,2,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -9,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr10 + set_fr_iimmed 0x2001,0xffff,fr9 ; 15 bit result + set_fr_iimmed 0xffff,0xfffe,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbfff,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x8001,0x0000,acc1 + + ; Negative operands + set_fr_iimmed 0x8000,0x8000,fr8 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0xfffe,0xfffc,fr9 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0x00,accg0 + test_acc_limmed 0x8000,0x0000,acc0 + test_accg_immed 0x00,accg1 + test_acc_immed 26,acc1 + + set_fr_iimmed 0xffff,0xffff,fr8 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x0000,fr9 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x0000,fr8 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x0000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mqcpxiu.cgs b/sim/testsuite/sim/frv/mqcpxiu.cgs new file mode 100644 index 00000000000..22d48f6333c --- /dev/null +++ b/sim/testsuite/sim/frv/mqcpxiu.cgs @@ -0,0 +1,60 @@ +# frv testcase for mqcpxiu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mqcpxiu +mqcpxiu: + set_fr_iimmed 4,2,fr8 ; multiply small numbers + set_fr_iimmed 3,5,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 1,3,fr11 + mqcpxiu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + test_accg_immed 0,accg1 + test_acc_immed 5,acc1 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 0,2,fr10 + set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result + set_fr_iimmed 0x0001,2,fr11 + mqcpxiu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7fff,acc1 + + set_fr_iimmed 0x4000,1,fr8 ; 16 bit result + set_fr_iimmed 0x0001,2,fr10 + set_fr_iimmed 0x4000,1,fr9 ; 17 bit result + set_fr_iimmed 0x0001,4,fr11 + mqcpxiu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x0010001,acc1 + + set_fr_iimmed 0x7fff,0x0000,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr11 + mqcpxiu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0x0000,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + mqcpxiu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 1,accg1 + test_acc_immed 0xfffc0002,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mqcpxrs.cgs b/sim/testsuite/sim/frv/mqcpxrs.cgs new file mode 100644 index 00000000000..d1d1f48db1c --- /dev/null +++ b/sim/testsuite/sim/frv/mqcpxrs.cgs @@ -0,0 +1,103 @@ +# frv testcase for mqcpxrs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mqcpxrs +mqcpxrs: + ; Positive operands + set_fr_iimmed 2,4,fr8 ; multiply small numbers + set_fr_iimmed 3,5,fr10 + set_fr_iimmed 3,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x0007,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ff0,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x2000,fr10 + set_fr_iimmed 0x7fff,0x0000,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr10 + set_fr_iimmed 0xfffe,2,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -3,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbff0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8006,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x8000,0x8000,acc1 + + ; Negative operands + set_fr_iimmed 0x8000,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0xfffe,0xfffc,fr9 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x7fff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -14,acc1 + + set_fr_iimmed 0xffff,0xffff,fr8 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr10 + set_fr_iimmed 0x7fff,0x0000,fr9 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x0000,fr8 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x0000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mqcpxru.cgs b/sim/testsuite/sim/frv/mqcpxru.cgs new file mode 100644 index 00000000000..45e1b358bed --- /dev/null +++ b/sim/testsuite/sim/frv/mqcpxru.cgs @@ -0,0 +1,78 @@ +# frv testcase for mqcpxru $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mqcpxru +mqcpxru: + set_fr_iimmed 4,2,fr8 ; multiply small numbers + set_fr_iimmed 5,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 3,1,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + test_accg_immed 0,accg1 + test_acc_immed 1,acc1 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result + set_fr_iimmed 2,0x0001,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffd,acc1 + + set_fr_iimmed 0x4000,1,fr8 ; 16 bit result + set_fr_iimmed 4,0x0001,fr10 + set_fr_iimmed 0x8000,1,fr9 ; 17 bit result + set_fr_iimmed 4,0x0001,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x0001ffff,acc1 + + set_fr_iimmed 0x7fff,0x0000,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0x0000,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0x0001,fr9 ; saturation + set_fr_iimmed 0xffff,0x0001,fr11 + mqcpxru fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0xffff,fr8 ; saturation + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xfffe,0xffff,fr9 ; saturation + set_fr_iimmed 0xffff,0xffff,fr11 + mqcpxru fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mqmachs.cgs b/sim/testsuite/sim/frv/mqmachs.cgs new file mode 100644 index 00000000000..ff023e70693 --- /dev/null +++ b/sim/testsuite/sim/frv/mqmachs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqmachs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mqmachs +mqmachs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + pass + + diff --git a/sim/testsuite/sim/frv/mqmachu.cgs b/sim/testsuite/sim/frv/mqmachu.cgs new file mode 100644 index 00000000000..b13eabe1045 --- /dev/null +++ b/sim/testsuite/sim/frv/mqmachu.cgs @@ -0,0 +1,144 @@ +# frv testcase for mqmachu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mqmachu +mqmachu: + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8000,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00018000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00018000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff8007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff8007,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4001,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4001,0x8000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x3ffd,0x8008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x3ffd,0x8008,acc1 + test_accg_immed 1,accg2 + test_acc_limmed 0x3fff,0x8001,acc2 + test_accg_immed 1,accg3 + test_acc_limmed 0x3fff,0x8001,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mqmacxhs.cgs b/sim/testsuite/sim/frv/mqmacxhs.cgs new file mode 100644 index 00000000000..0be1151c69a --- /dev/null +++ b/sim/testsuite/sim/frv/mqmacxhs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqmacxhs $GRi,$GRj,$ACCk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mqmacxhs +mqmacxhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 2,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 0xffff,1,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + pass + + diff --git a/sim/testsuite/sim/frv/mqmulhs.cgs b/sim/testsuite/sim/frv/mqmulhs.cgs new file mode 100644 index 00000000000..0a10c2908ce --- /dev/null +++ b/sim/testsuite/sim/frv/mqmulhs.cgs @@ -0,0 +1,125 @@ +# frv testcase for mqmulhs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mqmulhs +mqmulhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x0001,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -2,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -2,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffe,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffe,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xc000,0x8000,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xc000,0x8000,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x40000000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x40000000,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mqmulhu.cgs b/sim/testsuite/sim/frv/mqmulhu.cgs new file mode 100644 index 00000000000..e94c09ae97e --- /dev/null +++ b/sim/testsuite/sim/frv/mqmulhu.cgs @@ -0,0 +1,80 @@ +# frv testcase for mqmulhu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mqmulhu +mqmulhu: + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + mqmulhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmulhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + mqmulhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00010000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00010000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmulhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4000,0x0000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + mqmulhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xfffe,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xfffe,0x0001,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mqmulxhs.cgs b/sim/testsuite/sim/frv/mqmulxhs.cgs new file mode 100644 index 00000000000..7686bc1cf5c --- /dev/null +++ b/sim/testsuite/sim/frv/mqmulxhs.cgs @@ -0,0 +1,125 @@ +# frv testcase for mqmulxhs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mqmulxhs +mqmulxhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 4,acc0 + test_accg_immed 0,accg1 + test_acc_immed 9,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 2,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x0001,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -2,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -2,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffe,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffe,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xc000,0x8000,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xc000,0x8000,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x40000000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x40000000,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mqmulxhu.cgs b/sim/testsuite/sim/frv/mqmulxhu.cgs new file mode 100644 index 00000000000..b60e421bc73 --- /dev/null +++ b/sim/testsuite/sim/frv/mqmulxhu.cgs @@ -0,0 +1,80 @@ +# frv testcase for mqmulxhu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mqmulxhu +mqmulxhu: + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 1,2,fr11 + mqmulxhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 0,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqmulxhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 0x8000,2,fr11 + mqmulxhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00010000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00010000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmulxhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4000,0x0000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + mqmulxhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xfffe,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xfffe,0x0001,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mqsaths.cgs b/sim/testsuite/sim/frv/mqsaths.cgs new file mode 100644 index 00000000000..1d02a48d2fb --- /dev/null +++ b/sim/testsuite/sim/frv/mqsaths.cgs @@ -0,0 +1,50 @@ +# frv testcase for mqsaths $FRi,$FRj,$FRj +# mach: fr400 + + .include "testutils.inc" + + start + + .global mqsaths +mqsaths: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0001,0x7fff,fr11 + set_fr_iimmed 0x0000,0x0000,fr13 + mqsaths fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr11 + set_fr_iimmed 0x0040,0x0040,fr13 + mqsaths fr10,fr12,fr14 + test_fr_limmed 0xffff,0xffff,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x0040,0x0040,fr12 + set_fr_iimmed 0xffff,0x8000,fr11 + set_fr_iimmed 0x0040,0x0040,fr13 + mqsaths fr10,fr12,fr14 + test_fr_limmed 0x0001,0x0040,fr14 + test_fr_limmed 0xffff,0xffbf,fr15 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr12 + set_fr_iimmed 0x0001,0x7fff,fr11 + set_fr_iimmed 0x7fff,0x7fff,fr13 + mqsaths fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0001,0x7fff,fr15 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr12 + set_fr_iimmed 0xffff,0x8000,fr11 + set_fr_iimmed 0x7fff,0x7fff,fr13 + mqsaths fr10,fr12,fr14 + test_fr_limmed 0xffff,0x8000,fr14 + test_fr_limmed 0xffff,0x8000,fr15 + + pass diff --git a/sim/testsuite/sim/frv/mqxmachs.cgs b/sim/testsuite/sim/frv/mqxmachs.cgs new file mode 100644 index 00000000000..6791ed31874 --- /dev/null +++ b/sim/testsuite/sim/frv/mqxmachs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqxmachs $GRi,$GRj,$ACCk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mqxmachs +mqxmachs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_immed 6,acc2 + test_accg_immed 0,accg3 + test_acc_immed 6,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_immed 8,acc2 + test_accg_immed 0,accg3 + test_acc_immed 8,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8008,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7fff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7fff,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7ffd,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffb,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffb,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffb,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffb,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0008,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_immed 0x3fff0009,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fff0009,acc3 + test_accg_immed 0,accg0 + test_acc_immed 0x3fffbffd,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fffbffd,acc1 + + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/sim/frv/mqxmacxhs.cgs b/sim/testsuite/sim/frv/mqxmacxhs.cgs new file mode 100644 index 00000000000..c644eed231c --- /dev/null +++ b/sim/testsuite/sim/frv/mqxmacxhs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqxmacxhs $GRi,$GRj,$ACCk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mqxmacxhs +mqxmacxhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_immed 6,acc2 + test_accg_immed 0,accg3 + test_acc_immed 6,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 2,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_immed 8,acc2 + test_accg_immed 0,accg3 + test_acc_immed 8,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8008,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7fff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7fff,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7ffd,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffb,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffb,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffb,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffb,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0008,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_immed 0x3fff0009,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fff0009,acc3 + test_accg_immed 0,accg0 + test_acc_immed 0x3fffbffd,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fffbffd,acc1 + + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 0xffff,1,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/sim/frv/mrdacc.cgs b/sim/testsuite/sim/frv/mrdacc.cgs new file mode 100644 index 00000000000..217803655b6 --- /dev/null +++ b/sim/testsuite/sim/frv/mrdacc.cgs @@ -0,0 +1,26 @@ +# frv testcase for mrdacc $ACC40i,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mrdacc +mrdacc: + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed -1,accg3 + set_acc_immed -1,acc3 + set_accg_immed 0x12,accg2 + set_acc_immed 0xdeadbeef,acc2 + + mrdacc acc0,fr10 + test_fr_iimmed 0,fr10 + + mrdacc acc3,fr10 + test_fr_iimmed 0xffffffff,fr10 + + mrdacc acc2,fr10 + test_fr_iimmed 0xdeadbeef,fr10 + + pass diff --git a/sim/testsuite/sim/frv/mrdaccg.cgs b/sim/testsuite/sim/frv/mrdaccg.cgs new file mode 100644 index 00000000000..96e94065e63 --- /dev/null +++ b/sim/testsuite/sim/frv/mrdaccg.cgs @@ -0,0 +1,26 @@ +# frv testcase for mrdaccg $ACC40i,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mrdaccg +mrdaccg: + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed -1,accg3 + set_acc_immed -1,acc3 + set_accg_immed 0x12,accg2 + set_acc_immed 0xdeadbeef,acc2 + + mrdaccg accg0,fr10 + test_fr_iimmed 0,fr10 + + mrdaccg accg3,fr10 + test_fr_iimmed 0x000000ff,fr10 + + mrdaccg accg2,fr10 + test_fr_iimmed 0x00000012,fr10 + + pass diff --git a/sim/testsuite/sim/frv/mrotli.cgs b/sim/testsuite/sim/frv/mrotli.cgs new file mode 100644 index 00000000000..02220ee4942 --- /dev/null +++ b/sim/testsuite/sim/frv/mrotli.cgs @@ -0,0 +1,34 @@ +# frv testcase for mrotli $FRi,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mrotli +mrotli: + set_fr_iimmed 0,2,fr8 + mrotli fr8,0x20,fr8 ; Shift by 0 + test_fr_iimmed 2,fr8 + + set_fr_iimmed 0,2,fr8 + mrotli fr8,0,fr8 ; Shift by 0 + test_fr_iimmed 2,fr8 + + set_fr_iimmed 0,2,fr8 + mrotli fr8,1,fr8 ; Shift by 1 + test_fr_iimmed 4,fr8 + + set_fr_iimmed 0,1,fr8 + mrotli fr8,31,fr8 ; Shift by 31 + test_fr_iimmed 0x80000000,fr8 + + set_fr_iimmed 0,2,fr8 + mrotli fr8,31,fr8 ; max rotation + test_fr_iimmed 1,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + mrotli fr8,16,fr8 + test_fr_iimmed 0xbeefdead,fr8 + + pass diff --git a/sim/testsuite/sim/frv/mrotri.cgs b/sim/testsuite/sim/frv/mrotri.cgs new file mode 100644 index 00000000000..17a5c74e7e7 --- /dev/null +++ b/sim/testsuite/sim/frv/mrotri.cgs @@ -0,0 +1,34 @@ +# frv testcase for mrotri $FRinti,$s6,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mrotri +mrotri: + set_fr_iimmed 0x8000,0x0000,fr8 + mrotri fr8,0x20,fr8 ; Shift by 0 + test_fr_iimmed 0x80000000,fr8 + + set_fr_iimmed 0x8000,0x0000,fr8 + mrotri fr8,0,fr8 ; Shift by 0 + test_fr_iimmed 0x80000000,fr8 + + set_fr_iimmed 0x8000,0x0000,fr8 + mrotri fr8,1,fr8 ; Shift by 1 + test_fr_iimmed 0x40000000,fr8 + + set_fr_iimmed 0x8000,0x0000,fr8 + mrotri fr8,31,fr8 ; Shift by 31 + test_fr_iimmed 1,fr8 + + set_fr_iimmed 0x4000,0x0000,fr8 + mrotri fr8,31,fr8 ; max shift + test_fr_iimmed 0x80000000,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + mrotri fr8,16,fr8 ; max shift + test_fr_iimmed 0xbeefdead,fr8 + + pass diff --git a/sim/testsuite/sim/frv/msaths.cgs b/sim/testsuite/sim/frv/msaths.cgs new file mode 100644 index 00000000000..513d5d3d66a --- /dev/null +++ b/sim/testsuite/sim/frv/msaths.cgs @@ -0,0 +1,55 @@ +# frv testcase for msaths $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global msaths +msaths: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0001,0x0040,fr12 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffbf,fr12 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0001,0x7fff,fr12 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0xffff,0x8000,fr12 + + pass diff --git a/sim/testsuite/sim/frv/msathu.cgs b/sim/testsuite/sim/frv/msathu.cgs new file mode 100644 index 00000000000..4f376b2c34d --- /dev/null +++ b/sim/testsuite/sim/frv/msathu.cgs @@ -0,0 +1,55 @@ +# frv testcase for msathu $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global msathu +msathu: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0001,0x0040,fr12 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0040,0x0040,fr12 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0001,0x7fff,fr12 + + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x7fff,0xffff,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x7fff,0xffff,fr12 + + pass diff --git a/sim/testsuite/sim/frv/msllhi.cgs b/sim/testsuite/sim/frv/msllhi.cgs new file mode 100644 index 00000000000..4340b9f9c06 --- /dev/null +++ b/sim/testsuite/sim/frv/msllhi.cgs @@ -0,0 +1,30 @@ +# frv testcase for msllhi $FRi,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global msllhi +msllhi: + set_fr_iimmed 2,2,fr8 + msllhi fr8,0x20,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 2,2,fr8 + msllhi fr8,0,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 2,2,fr8 + msllhi fr8,1,fr8 ; Shift by 1 + test_fr_limmed 4,4,fr8 + + set_fr_iimmed 1,1,fr8 + msllhi fr8,31,fr8 ; Shift by 15 + test_fr_limmed 0x8000,0x8000,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + msllhi fr8,15,fr8 + test_fr_iimmed 0x80008000,fr8 + + pass diff --git a/sim/testsuite/sim/frv/msrahi.cgs b/sim/testsuite/sim/frv/msrahi.cgs new file mode 100644 index 00000000000..182f84e2147 --- /dev/null +++ b/sim/testsuite/sim/frv/msrahi.cgs @@ -0,0 +1,30 @@ +# frv testcase for msrahi $FRi,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global msrahi +msrahi: + set_fr_iimmed 2,2,fr8 + msrahi fr8,0x20,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 2,2,fr8 + msrahi fr8,0,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 3,2,fr8 + msrahi fr8,1,fr8 ; Shift by 1 + test_fr_limmed 1,1,fr8 + + set_fr_iimmed 0x8000,0x7fff,fr8 + msrahi fr8,31,fr8 ; Shift by 15 + test_fr_limmed 0xffff,0x0000,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + msrahi fr8,15,fr8 + test_fr_iimmed 0xffffffff,fr8 + + pass diff --git a/sim/testsuite/sim/frv/msrlhi.cgs b/sim/testsuite/sim/frv/msrlhi.cgs new file mode 100644 index 00000000000..c9971a98a68 --- /dev/null +++ b/sim/testsuite/sim/frv/msrlhi.cgs @@ -0,0 +1,30 @@ +# frv testcase for msrlhi $FRi,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global msrlhi +msrlhi: + set_fr_iimmed 2,2,fr8 + msrlhi fr8,0x20,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 2,2,fr8 + msrlhi fr8,0,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 3,2,fr8 + msrlhi fr8,1,fr8 ; Shift by 1 + test_fr_limmed 1,1,fr8 + + set_fr_iimmed 0xffff,0x8000,fr8 + msrlhi fr8,31,fr8 ; Shift by 15 + test_fr_limmed 0x0001,0x0001,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + msrlhi fr8,15,fr8 + test_fr_iimmed 0x00010001,fr8 + + pass diff --git a/sim/testsuite/sim/frv/msubaccs.cgs b/sim/testsuite/sim/frv/msubaccs.cgs new file mode 100644 index 00000000000..f793e9a5f53 --- /dev/null +++ b/sim/testsuite/sim/frv/msubaccs.cgs @@ -0,0 +1,131 @@ +# frv testcase for msubaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "testutils.inc" + + start + + .global msubaccs +msubaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg3 + test_acc_limmed 0x4111,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffffffe,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000002,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0x00000000,acc3 + msubaccs.p acc0,acc1 + msubaccs acc2,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x8,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/msubhss.cgs b/sim/testsuite/sim/frv/msubhss.cgs new file mode 100644 index 00000000000..ff3b23a2067 --- /dev/null +++ b/sim/testsuite/sim/frv/msubhss.cgs @@ -0,0 +1,100 @@ +# frv testcase for msubhss $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global msubhss +msubhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0xdead,0x4111,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x4111,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x1235,0x5679,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + msubhss.p fr10,fr10,fr12 + msubhss fr11,fr10,fr13 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x8000,0x8000,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/msubhus.cgs b/sim/testsuite/sim/frv/msubhus.cgs new file mode 100644 index 00000000000..4de2910a65a --- /dev/null +++ b/sim/testsuite/sim/frv/msubhus.cgs @@ -0,0 +1,80 @@ +# frv testcase for msubhus $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global msubhus +msubhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x7ffc,0x7ffd,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + msubhus.p fr10,fr10,fr12 + msubhus fr10,fr11,fr13 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x0000,0x0000,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/mtrap.cgs b/sim/testsuite/sim/frv/mtrap.cgs new file mode 100644 index 00000000000..a4c41f39f9e --- /dev/null +++ b/sim/testsuite/sim/frv/mtrap.cgs @@ -0,0 +1,50 @@ +# frv testcase for mp_exception +# mach: all + + .include "testutils.inc" + + start + + .global mp_exception +mpx: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 0x0e0,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + set_gr_immed 0,gr5 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + mtrap ; generate interrupt + test_gr_immed 1,gr5 + + and_spr_immed 0xffffc000,msr0 ; Clear msr0 fields + mcmpsh fr10,fr11,fcc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + mtrap ; nop + test_gr_immed 1,gr5 + + pass + +; exception handler +ok1: + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + inc_gr_immed 1,gr5 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/munpackh.cgs b/sim/testsuite/sim/frv/munpackh.cgs new file mode 100644 index 00000000000..45b2bd82421 --- /dev/null +++ b/sim/testsuite/sim/frv/munpackh.cgs @@ -0,0 +1,22 @@ +# frv testcase for munpackh $FRi,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global munpackh +munpackh: + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + munpackh fr10,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + munpackh fr10,fr12 + test_fr_limmed 0x1234,0x1234,fr12 + test_fr_limmed 0x5678,0x5678,fr13 + + pass diff --git a/sim/testsuite/sim/frv/mwcut.cgs b/sim/testsuite/sim/frv/mwcut.cgs new file mode 100644 index 00000000000..0e31b8fa93a --- /dev/null +++ b/sim/testsuite/sim/frv/mwcut.cgs @@ -0,0 +1,269 @@ +# frv testcase for mwcut $FRi,FRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mwcut +mwcut: + set_fr_iimmed 0x0123,0x4567,fr8 + set_fr_iimmed 0x89ab,0xcdef,fr9 + + set_fr_iimmed 0,0,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x01234567,fr11 + + set_fr_iimmed 0,1,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x02468acf,fr11 + + set_fr_iimmed 0,2,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x048d159e,fr11 + + set_fr_iimmed 0,3,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x091a2b3c,fr11 + + set_fr_iimmed 0,4,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x12345678,fr11 + + set_fr_iimmed 0,5,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x2468acf1,fr11 + + set_fr_iimmed 0,6,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x48d159e2,fr11 + + set_fr_iimmed 0,7,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x91a2b3c4,fr11 + + set_fr_iimmed 0,8,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x23456789,fr11 + + set_fr_iimmed 0,9,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x468acf13,fr11 + + set_fr_iimmed 0,10,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x8d159e26,fr11 + + set_fr_iimmed 0,11,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x1a2b3c4d,fr11 + + set_fr_iimmed 0,12,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x3456789a,fr11 + + set_fr_iimmed 0,13,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x68acf135,fr11 + + set_fr_iimmed 0,14,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xd159e26a,fr11 + + set_fr_iimmed 0,15,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xa2b3c4d5,fr11 + + set_fr_iimmed 0,16,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x456789ab,fr11 + + set_fr_iimmed 0,17,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x8acf1357,fr11 + + set_fr_iimmed 0,18,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x159e26af,fr11 + + set_fr_iimmed 0,19,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x2b3c4d5e,fr11 + + set_fr_iimmed 0,20,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x56789abc,fr11 + + set_fr_iimmed 0,21,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xacf13579,fr11 + + set_fr_iimmed 0,22,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x59e26af3,fr11 + + set_fr_iimmed 0,23,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xb3c4d5e6,fr11 + + set_fr_iimmed 0,24,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x6789abcd,fr11 + + set_fr_iimmed 0,25,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + set_fr_iimmed 0,26,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + set_fr_iimmed 0,27,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x3c4d5e6f,fr11 + + set_fr_iimmed 0,28,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x789abcde,fr11 + + set_fr_iimmed 0,29,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xf13579bd,fr11 + + set_fr_iimmed 0,30,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xe26af37b,fr11 + + set_fr_iimmed 0,31,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xc4d5e6f7,fr11 + + set_fr_iimmed 0,32,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x89abcdef,fr11 + + set_fr_iimmed 0,33,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x13579bde,fr11 + + set_fr_iimmed 0,34,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x26af37bc,fr11 + + set_fr_iimmed 0,35,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x4d5e6f78,fr11 + + set_fr_iimmed 0,36,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x9abcdef0,fr11 + + set_fr_iimmed 0,37,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x3579bde0,fr11 + + set_fr_iimmed 0,38,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x6af37bc0,fr11 + + set_fr_iimmed 0,39,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xd5e6f780,fr11 + + set_fr_iimmed 0,40,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xabcdef00,fr11 + + set_fr_iimmed 0,41,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x579bde00,fr11 + + set_fr_iimmed 0,42,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xaf37bc00,fr11 + + set_fr_iimmed 0,43,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x5e6f7800,fr11 + + set_fr_iimmed 0,44,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xbcdef000,fr11 + + set_fr_iimmed 0,45,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x79bde000,fr11 + + set_fr_iimmed 0,46,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xf37bc000,fr11 + + set_fr_iimmed 0,47,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xe6f78000,fr11 + + set_fr_iimmed 0,48,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xcdef0000,fr11 + + set_fr_iimmed 0,49,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x9bde0000,fr11 + + set_fr_iimmed 0,50,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x37bc0000,fr11 + + set_fr_iimmed 0,51,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x6f780000,fr11 + + set_fr_iimmed 0,52,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xdef00000,fr11 + + set_fr_iimmed 0,53,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xbde00000,fr11 + + set_fr_iimmed 0,54,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x7bc00000,fr11 + + set_fr_iimmed 0,55,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xf7800000,fr11 + + set_fr_iimmed 0,56,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xef000000,fr11 + + set_fr_iimmed 0,57,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xde000000,fr11 + + set_fr_iimmed 0,58,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xbc000000,fr11 + + set_fr_iimmed 0,59,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x78000000,fr11 + + set_fr_iimmed 0,60,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xf0000000,fr11 + + set_fr_iimmed 0,61,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xe0000000,fr11 + + set_fr_iimmed 0,62,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xc0000000,fr11 + + set_fr_iimmed 0,63,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + pass diff --git a/sim/testsuite/sim/frv/mwcuti.cgs b/sim/testsuite/sim/frv/mwcuti.cgs new file mode 100644 index 00000000000..338eab86389 --- /dev/null +++ b/sim/testsuite/sim/frv/mwcuti.cgs @@ -0,0 +1,205 @@ +# frv testcase for mwcuti $FRi,s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mwcuti +mwcuti: + set_fr_iimmed 0x0123,0x4567,fr8 + set_fr_iimmed 0x89ab,0xcdef,fr9 + + mwcuti fr8,0,fr11 + test_fr_iimmed 0x01234567,fr11 + + mwcuti fr8,1,fr11 + test_fr_iimmed 0x02468acf,fr11 + + mwcuti fr8,2,fr11 + test_fr_iimmed 0x048d159e,fr11 + + mwcuti fr8,3,fr11 + test_fr_iimmed 0x091a2b3c,fr11 + + mwcuti fr8,4,fr11 + test_fr_iimmed 0x12345678,fr11 + + mwcuti fr8,5,fr11 + test_fr_iimmed 0x2468acf1,fr11 + + mwcuti fr8,6,fr11 + test_fr_iimmed 0x48d159e2,fr11 + + mwcuti fr8,7,fr11 + test_fr_iimmed 0x91a2b3c4,fr11 + + mwcuti fr8,8,fr11 + test_fr_iimmed 0x23456789,fr11 + + mwcuti fr8,9,fr11 + test_fr_iimmed 0x468acf13,fr11 + + mwcuti fr8,10,fr11 + test_fr_iimmed 0x8d159e26,fr11 + + mwcuti fr8,11,fr11 + test_fr_iimmed 0x1a2b3c4d,fr11 + + mwcuti fr8,12,fr11 + test_fr_iimmed 0x3456789a,fr11 + + mwcuti fr8,13,fr11 + test_fr_iimmed 0x68acf135,fr11 + + mwcuti fr8,14,fr11 + test_fr_iimmed 0xd159e26a,fr11 + + mwcuti fr8,15,fr11 + test_fr_iimmed 0xa2b3c4d5,fr11 + + mwcuti fr8,16,fr11 + test_fr_iimmed 0x456789ab,fr11 + + mwcuti fr8,17,fr11 + test_fr_iimmed 0x8acf1357,fr11 + + mwcuti fr8,18,fr11 + test_fr_iimmed 0x159e26af,fr11 + + mwcuti fr8,19,fr11 + test_fr_iimmed 0x2b3c4d5e,fr11 + + mwcuti fr8,20,fr11 + test_fr_iimmed 0x56789abc,fr11 + + mwcuti fr8,21,fr11 + test_fr_iimmed 0xacf13579,fr11 + + mwcuti fr8,22,fr11 + test_fr_iimmed 0x59e26af3,fr11 + + mwcuti fr8,23,fr11 + test_fr_iimmed 0xb3c4d5e6,fr11 + + mwcuti fr8,24,fr11 + test_fr_iimmed 0x6789abcd,fr11 + + mwcuti fr8,25,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + mwcuti fr8,26,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + mwcuti fr8,27,fr11 + test_fr_iimmed 0x3c4d5e6f,fr11 + + mwcuti fr8,28,fr11 + test_fr_iimmed 0x789abcde,fr11 + + mwcuti fr8,29,fr11 + test_fr_iimmed 0xf13579bd,fr11 + + mwcuti fr8,30,fr11 + test_fr_iimmed 0xe26af37b,fr11 + + mwcuti fr8,31,fr11 + test_fr_iimmed 0xc4d5e6f7,fr11 + + mwcuti fr8,32,fr11 + test_fr_iimmed 0x89abcdef,fr11 + + mwcuti fr8,33,fr11 + test_fr_iimmed 0x13579bde,fr11 + + mwcuti fr8,34,fr11 + test_fr_iimmed 0x26af37bc,fr11 + + mwcuti fr8,35,fr11 + test_fr_iimmed 0x4d5e6f78,fr11 + + mwcuti fr8,36,fr11 + test_fr_iimmed 0x9abcdef0,fr11 + + mwcuti fr8,37,fr11 + test_fr_iimmed 0x3579bde0,fr11 + + mwcuti fr8,38,fr11 + test_fr_iimmed 0x6af37bc0,fr11 + + mwcuti fr8,39,fr11 + test_fr_iimmed 0xd5e6f780,fr11 + + mwcuti fr8,40,fr11 + test_fr_iimmed 0xabcdef00,fr11 + + mwcuti fr8,41,fr11 + test_fr_iimmed 0x579bde00,fr11 + + mwcuti fr8,42,fr11 + test_fr_iimmed 0xaf37bc00,fr11 + + mwcuti fr8,43,fr11 + test_fr_iimmed 0x5e6f7800,fr11 + + mwcuti fr8,44,fr11 + test_fr_iimmed 0xbcdef000,fr11 + + mwcuti fr8,45,fr11 + test_fr_iimmed 0x79bde000,fr11 + + mwcuti fr8,46,fr11 + test_fr_iimmed 0xf37bc000,fr11 + + mwcuti fr8,47,fr11 + test_fr_iimmed 0xe6f78000,fr11 + + mwcuti fr8,48,fr11 + test_fr_iimmed 0xcdef0000,fr11 + + mwcuti fr8,49,fr11 + test_fr_iimmed 0x9bde0000,fr11 + + mwcuti fr8,50,fr11 + test_fr_iimmed 0x37bc0000,fr11 + + mwcuti fr8,51,fr11 + test_fr_iimmed 0x6f780000,fr11 + + mwcuti fr8,52,fr11 + test_fr_iimmed 0xdef00000,fr11 + + mwcuti fr8,53,fr11 + test_fr_iimmed 0xbde00000,fr11 + + mwcuti fr8,54,fr11 + test_fr_iimmed 0x7bc00000,fr11 + + mwcuti fr8,55,fr11 + test_fr_iimmed 0xf7800000,fr11 + + mwcuti fr8,56,fr11 + test_fr_iimmed 0xef000000,fr11 + + mwcuti fr8,57,fr11 + test_fr_iimmed 0xde000000,fr11 + + mwcuti fr8,58,fr11 + test_fr_iimmed 0xbc000000,fr11 + + mwcuti fr8,59,fr11 + test_fr_iimmed 0x78000000,fr11 + + mwcuti fr8,60,fr11 + test_fr_iimmed 0xf0000000,fr11 + + mwcuti fr8,61,fr11 + test_fr_iimmed 0xe0000000,fr11 + + mwcuti fr8,62,fr11 + test_fr_iimmed 0xc0000000,fr11 + + mwcuti fr8,63,fr11 + test_fr_iimmed 0x80000000,fr11 + + pass diff --git a/sim/testsuite/sim/frv/mwtacc.cgs b/sim/testsuite/sim/frv/mwtacc.cgs new file mode 100644 index 00000000000..20b4d31885b --- /dev/null +++ b/sim/testsuite/sim/frv/mwtacc.cgs @@ -0,0 +1,23 @@ +# frv testcase for mwtacc $FRinti,$ACC40k +# mach: all + + .include "testutils.inc" + + start + + .global mwtacc +mwtacc: + test_accg_immed 0x00,accg0 + test_acc_immed 0x00000000,acc0 + + set_fr_iimmed 0xdead,0xbeef,fr10 + mwtacc fr10,acc0 + test_accg_immed 0x00,accg0 + test_acc_immed 0xdeadbeef,acc0 + + set_fr_iimmed 0x1234,0x5678,fr10 + mwtacc fr10,acc0 + test_accg_immed 0x00,accg0 + test_acc_immed 0x12345678,acc0 + + pass diff --git a/sim/testsuite/sim/frv/mwtaccg.cgs b/sim/testsuite/sim/frv/mwtaccg.cgs new file mode 100644 index 00000000000..6e26bab287b --- /dev/null +++ b/sim/testsuite/sim/frv/mwtaccg.cgs @@ -0,0 +1,23 @@ +# frv testcase for mwtaccg $FRinti,$ACC40k +# mach: all + + .include "testutils.inc" + + start + + .global mwtaccg +mwtaccg: + test_accg_immed 0x00,accg0 + test_acc_immed 0x00000000,acc0 + + set_fr_iimmed 0xdead,0xbeef,fr10 + mwtaccg fr10,accg0 + test_accg_immed 0xef,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x1234,0x5678,fr10 + mwtaccg fr10,accg0 + test_accg_immed 0x78,accg0 + test_acc_immed 0,acc0 + + pass diff --git a/sim/testsuite/sim/frv/mxor.cgs b/sim/testsuite/sim/frv/mxor.cgs new file mode 100644 index 00000000000..6d1cce11bf5 --- /dev/null +++ b/sim/testsuite/sim/frv/mxor.cgs @@ -0,0 +1,30 @@ +# frv testcase for mxor $FRinti,$FRintj,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mxor +mxor: + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + mxor fr7,fr8,fr8 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + mxor fr7,fr8,fr8 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + mxor fr7,fr8,fr8 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + mxor fr7,fr8,fr8 + test_fr_iimmed 0xdeadbeef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/nandcr.cgs b/sim/testsuite/sim/frv/nandcr.cgs new file mode 100644 index 00000000000..8d3298fd787 --- /dev/null +++ b/sim/testsuite/sim/frv/nandcr.cgs @@ -0,0 +1,59 @@ +# frv testcase for nandcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global nandcr +nandcr: + set_spr_immed 0x1b1b,cccr + nandcr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc7,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc7,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc6,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc6,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc5,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc5,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc5,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc5,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc4,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc4,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc4,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + nandcr cc4,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/sim/frv/nandncr.cgs b/sim/testsuite/sim/frv/nandncr.cgs new file mode 100644 index 00000000000..c761c56102c --- /dev/null +++ b/sim/testsuite/sim/frv/nandncr.cgs @@ -0,0 +1,59 @@ +# frv testcase for nandncr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global nandncr +nandncr: + set_spr_immed 0x1b1b,cccr + nandncr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc7,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc7,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc6,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc6,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc5,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc5,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc5,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + nandncr cc5,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + nandncr cc4,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc4,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc4,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc4,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/nfadds.cgs b/sim/testsuite/sim/frv/nfadds.cgs new file mode 100644 index 00000000000..87fe403dc59 --- /dev/null +++ b/sim/testsuite/sim/frv/nfadds.cgs @@ -0,0 +1,179 @@ +# frv testcase for nfadds $GRi,$GRj,$GRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfadds +nfadds: + nfadds fr16,fr0,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr4,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr12,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr24,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr32,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr36,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr40,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr44,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr48,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr52,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr20,fr0,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr4,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr12,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr24,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr32,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr36,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr40,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr44,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr48,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr52,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr8,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr12,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr24,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr28,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr36,fr40,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfadds fr48,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr52,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr56,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr60,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/sim/frv/nfdadds.cgs b/sim/testsuite/sim/frv/nfdadds.cgs new file mode 100644 index 00000000000..6d3ef6cfd7e --- /dev/null +++ b/sim/testsuite/sim/frv/nfdadds.cgs @@ -0,0 +1,225 @@ +# frv testcase for nfdadds $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdadds +nfdadds: + nfdadds fr16,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr20,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr8,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr12,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr24,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr28,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr36,fr40,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfdadds fr48,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr52,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/sim/frv/nfdcmps.cgs b/sim/testsuite/sim/frv/nfdcmps.cgs new file mode 100644 index 00000000000..977805ab2d7 --- /dev/null +++ b/sim/testsuite/sim/frv/nfdcmps.cgs @@ -0,0 +1,1549 @@ +# frv testcase for nfdcmps $FRi,$FRj,$FCCi_2 +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdcmps +nfdcmps: + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr0,fr0,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr4,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr8,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr0,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr0,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr4,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr4,fr4,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr8,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr4,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr4,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr8,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr8,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr8,fr8,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr8,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr8,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr12,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr12,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr12,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr12,fr12,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr12,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr12,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr16,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr16,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr16,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr16,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr16,fr16,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr16,fr20,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr16,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr16,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr20,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr20,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr20,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr20,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr20,fr16,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr20,fr20,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr20,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr20,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr24,fr24,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr24,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr24,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr28,fr28,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr28,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr28,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr28,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr32,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr36,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr40,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr44,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr48,fr48,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr48,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr48,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr48,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr28,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr32,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr36,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr40,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr44,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr48,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr52,fr52,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr52,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr52,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr0,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr4,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr8,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr12,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr16,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr20,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr24,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr28,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr32,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr36,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr40,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr44,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr48,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr52,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr0,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr4,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr8,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr12,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr16,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr20,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr24,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr28,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr32,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr36,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr40,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr44,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr48,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr52,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nfddivs.cgs b/sim/testsuite/sim/frv/nfddivs.cgs new file mode 100644 index 00000000000..0b16447057e --- /dev/null +++ b/sim/testsuite/sim/frv/nfddivs.cgs @@ -0,0 +1,306 @@ +# frv testcase for nfddivs $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfddivs +nfddivs: + nfddivs fr0,fr28,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr4,fr28,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr12,fr28,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr24,fr28,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr32,fr28,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr36,fr28,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr40,fr28,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr44,fr28,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr48,fr28,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr52,fr28,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr16,fr0,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr52,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr20,fr0,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr52,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr40,fr32,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfddivs fr48,fr20,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfddivs fr52,fr16,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0x0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/sim/frv/nfditos.cgs b/sim/testsuite/sim/frv/nfditos.cgs new file mode 100644 index 00000000000..1200944332d --- /dev/null +++ b/sim/testsuite/sim/frv/nfditos.cgs @@ -0,0 +1,31 @@ +# frv testcase for nfditos $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfditos +nfditos: + set_fr_iimmed 0,0,fr2 + set_fr_iimmed 0x0000,0x0002,fr3 + nfditos fr2,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr2 + set_fr_iimmed 0xdead,0xbeef,fr3 + nfditos fr2,fr2 + test_fr_iimmed 0xce054904,fr2 + test_fr_iimmed 0xce054904,fr3 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO test cases to set ne flags + + pass diff --git a/sim/testsuite/sim/frv/nfdivs.cgs b/sim/testsuite/sim/frv/nfdivs.cgs new file mode 100644 index 00000000000..a46068ba2b5 --- /dev/null +++ b/sim/testsuite/sim/frv/nfdivs.cgs @@ -0,0 +1,234 @@ +# frv testcase for nfdivs $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfdivs +nfdivs: + nfdivs fr0,fr28,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr4,fr28,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr8,fr28,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr12,fr28,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr24,fr28,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr28,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr32,fr28,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr36,fr28,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr40,fr28,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr44,fr28,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr48,fr28,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr52,fr28,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr16,fr0,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr52,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr20,fr0,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr52,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr8,fr28,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr28,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr40,fr32,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfdivs fr48,fr20,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfdivs fr52,fr16,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr56,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr60,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/sim/frv/nfdmadds.cgs b/sim/testsuite/sim/frv/nfdmadds.cgs new file mode 100644 index 00000000000..1af110cee6d --- /dev/null +++ b/sim/testsuite/sim/frv/nfdmadds.cgs @@ -0,0 +1,310 @@ +# frv testcase for nfdmadds $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdmadds +nfdmadds: + nfdmadds fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmadds fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr36,fr2 + set_fr_fr fr36,fr3 + nfdmadds fr28,fr8,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr8,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr36,fr2 + set_fr_fr fr36,fr3 + nfdmadds fr32,fr36,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO -- test cases to set ne flags + + pass diff --git a/sim/testsuite/sim/frv/nfdmas.cgs b/sim/testsuite/sim/frv/nfdmas.cgs new file mode 100644 index 00000000000..07f76aafb55 --- /dev/null +++ b/sim/testsuite/sim/frv/nfdmas.cgs @@ -0,0 +1,349 @@ +# frv testcase for nfdmas $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + load_float_constants2 + load_float_constants3 + + .global nfdmas +nfdmas: + nfdmas fr16,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr4 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr12 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr24 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr40 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr44 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr48 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmas fr20,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr4 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr12 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr24 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr40 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr44 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr48 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmas fr28,fr0,fr60 + test_fr_fr fr60,fr0 + test_fr_fr fr62,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr4,fr60 + test_fr_fr fr60,fr4 + test_fr_fr fr62,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr12,fr60 + test_fr_fr fr60,fr12 + test_fr_fr fr62,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr24,fr60 + test_fr_fr fr60,fr24 + test_fr_fr fr62,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr28,fr60 + test_fr_fr fr60,fr28 + test_fr_fr fr62,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr32,fr60 + test_fr_fr fr60,fr32 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr32 + test_fr_fr fr63,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr36,fr60 + test_fr_fr fr60,fr36 + test_fr_fr fr62,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr40,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr44,fr60 + test_fr_fr fr60,fr44 + test_fr_fr fr62,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr48,fr60 + test_fr_fr fr60,fr48 + test_fr_fr fr62,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr52,fr60 + test_fr_fr fr60,fr52 + test_fr_fr fr62,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmas fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr8,fr28,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmas fr32,fr36,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO -- test cases to set ne flags + + pass diff --git a/sim/testsuite/sim/frv/nfdmss.cgs b/sim/testsuite/sim/frv/nfdmss.cgs new file mode 100644 index 00000000000..3633d706544 --- /dev/null +++ b/sim/testsuite/sim/frv/nfdmss.cgs @@ -0,0 +1,319 @@ +# frv testcase for nfdmss $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + load_float_constants2 + load_float_constants3 + + .global nfdmss +nfdmss: + nfdmss fr16,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmss fr20,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmss fr28,fr0,fr60 + test_fr_fr fr60,fr0 + test_fr_fr fr62,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr4,fr60 + test_fr_fr fr60,fr4 + test_fr_fr fr62,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr12,fr60 + test_fr_fr fr60,fr12 + test_fr_fr fr62,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr24,fr60 + test_fr_fr fr60,fr24 + test_fr_fr fr62,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr28,fr60 + test_fr_fr fr60,fr28 + test_fr_fr fr61,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr62,fr28 + test_fr_fr fr63,fr20 + test_fr_fr fr63,fr16 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr32,fr60 + test_fr_fr fr60,fr32 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr32 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr36,fr60 + test_fr_fr fr60,fr36 + test_fr_fr fr62,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr40,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr44,fr60 + test_fr_fr fr60,fr44 + test_fr_fr fr62,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr48,fr60 + test_fr_fr fr60,fr48 + test_fr_fr fr62,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr52,fr60 + test_fr_fr fr60,fr52 + test_fr_fr fr62,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmss fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr8,fr28,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr62,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmss fr32,fr36,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr40 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO -- test cases to set ne flags + + pass diff --git a/sim/testsuite/sim/frv/nfdmulcs.cgs b/sim/testsuite/sim/frv/nfdmulcs.cgs new file mode 100644 index 00000000000..827e3c9ccea --- /dev/null +++ b/sim/testsuite/sim/frv/nfdmulcs.cgs @@ -0,0 +1,313 @@ +# frv testcase for nfdmulcs $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdmulcs +nfdmulcs: + nfdmulcs fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfdmulcs fr48,fr32,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr52,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + ; test all regs different + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + set_fr_fr fr32,fr50 ; 2 + set_fr_fr fr28,fr51 ; 1 + set_fr_fr fr44,fr52 ; 9 + set_fr_fr fr36,fr53 ; 3 + nfdmulcs fr50,fr52,fr54 ; 2*3, 1*9 + test_fr_fr fr54,fr40 ; 6 + test_fr_fr fr55,fr44 ; 9 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nfdmuls.cgs b/sim/testsuite/sim/frv/nfdmuls.cgs new file mode 100644 index 00000000000..082cc62db0d --- /dev/null +++ b/sim/testsuite/sim/frv/nfdmuls.cgs @@ -0,0 +1,300 @@ +# frv testcase for nfdmuls $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdmuls +nfdmuls: + nfdmuls fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfdmuls fr48,fr32,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr52,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nfdsads.cgs b/sim/testsuite/sim/frv/nfdsads.cgs new file mode 100644 index 00000000000..90f17d93630 --- /dev/null +++ b/sim/testsuite/sim/frv/nfdsads.cgs @@ -0,0 +1,212 @@ +# frv testcase for nfdsads $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdsads +nfdsads: + nfdsads fr16,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr32,fr2 + test_fr_fr fr2,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr36,fr2 + test_fr_fr fr2,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr40,fr2 + test_fr_fr fr2,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr44,fr2 + test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsads fr20,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr32,fr2 + test_fr_fr fr2,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr36,fr2 + test_fr_fr fr2,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr40,fr2 + test_fr_fr fr2,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr44,fr2 + test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsads fr8,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr12,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr24,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr28,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsads fr36,fr40,fr2 + test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + set_fr_fr fr4,fr49 + nfdsads fr48,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr0,fr53 + nfdsads fr52,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsads fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsads fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/sim/frv/nfdsqrts.cgs b/sim/testsuite/sim/frv/nfdsqrts.cgs new file mode 100644 index 00000000000..1a906bb7279 --- /dev/null +++ b/sim/testsuite/sim/frv/nfdsqrts.cgs @@ -0,0 +1,21 @@ +# frv testcase for nfdsqrts $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfdsqrts +nfdsqrts: + set_fr_iimmed 0x4049,0x0fdb,fr45 ; 3.141592654 + nfdsqrts fr44,fr2 ; 9.0 + test_fr_fr fr2,fr36 ; 3.0 + test_fr_iimmed 0x3fe2dfc5,fr3 ; 1.7724539 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO test cases to set ne flags + + pass diff --git a/sim/testsuite/sim/frv/nfdstoi.cgs b/sim/testsuite/sim/frv/nfdstoi.cgs new file mode 100644 index 00000000000..56dc941bb70 --- /dev/null +++ b/sim/testsuite/sim/frv/nfdstoi.cgs @@ -0,0 +1,29 @@ +# frv testcase for nfdstoi $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfdstoi +nfdstoi: + set_fr_fr fr20,fr17 + nfdstoi fr16,fr2 + test_fr_iimmed 0,fr2 + test_fr_iimmed 0,fr3 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0xce05,0x4904,fr2 + set_fr_fr fr32,fr3 + nfdstoi fr2,fr2 + test_fr_iimmed 0xdeadbf00,fr2 + test_fr_iimmed 0x00000002,fr3 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO test cases to set ne flags + + pass diff --git a/sim/testsuite/sim/frv/nfdsubs.cgs b/sim/testsuite/sim/frv/nfdsubs.cgs new file mode 100644 index 00000000000..82f3d8f210d --- /dev/null +++ b/sim/testsuite/sim/frv/nfdsubs.cgs @@ -0,0 +1,202 @@ +# frv testcase for nfdsubs $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdsubs +nfdsubs: + nfdsubs fr0,fr16,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr4,fr16,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr8,fr16,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr12,fr16,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr24,fr16,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr28,fr16,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr32,fr16,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr36,fr16,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr40,fr16,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr44,fr16,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr48,fr16,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr52,fr16,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr0,fr20,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr4,fr20,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr8,fr20,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr12,fr20,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr24,fr20,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr28,fr20,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr32,fr20,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr36,fr20,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr40,fr20,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr44,fr20,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr48,fr20,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr52,fr20,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr32,fr36,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr44,fr40,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfdsubs fr4,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr0,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/sim/frv/nfitos.cgs b/sim/testsuite/sim/frv/nfitos.cgs new file mode 100644 index 00000000000..1fb07b6bea5 --- /dev/null +++ b/sim/testsuite/sim/frv/nfitos.cgs @@ -0,0 +1,44 @@ +# frv testcase for nfitos $FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfitos +nfitos: + set_fr_iimmed 0,0,fr1 + nfitos fr1,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0x0000,0x0002,fr1 + nfitos fr1,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr1 + nfitos fr1,fr1 + test_fr_iimmed 0xce054904,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; These were an attempt to cause overflow + set_fr_iimmed 0x7fff,0xffff,fr1 + nfitos fr1,fr1 + test_fr_iimmed 0x4f000000,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0x8000,0x0000,fr1 + nfitos fr1,fr1 + test_fr_iimmed 0xcf000000,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nfmadds.cgs b/sim/testsuite/sim/frv/nfmadds.cgs new file mode 100644 index 00000000000..2113cd27716 --- /dev/null +++ b/sim/testsuite/sim/frv/nfmadds.cgs @@ -0,0 +1,227 @@ +# frv testcase for nfmadds $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfmadds +nfmadds: + set_fr_fr fr16,fr1 + nfmadds fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmadds fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr16,fr1 + nfmadds fr28,fr0,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr4,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr12,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr24,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr32,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr36,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr40,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr44,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr48,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr52,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr36,fr1 + nfmadds fr28,fr8,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr8,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr36,fr1 + nfmadds fr32,fr36,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO test cases to set ne flags + + pass diff --git a/sim/testsuite/sim/frv/nfmas.cgs b/sim/testsuite/sim/frv/nfmas.cgs new file mode 100644 index 00000000000..4933beb1f72 --- /dev/null +++ b/sim/testsuite/sim/frv/nfmas.cgs @@ -0,0 +1,297 @@ +# frv testcase for nfmas $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfmas +nfmas: + nfmas fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfmas fr48,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr52,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr56,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr60,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 6,fner1 + test_spr_immed 0,fner0 + + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfmas fr48,fr32,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr52,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr56,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr60,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 6,fner1 + test_spr_immed 0,fner0 + + pass + diff --git a/sim/testsuite/sim/frv/nfmss.cgs b/sim/testsuite/sim/frv/nfmss.cgs new file mode 100644 index 00000000000..b2818332522 --- /dev/null +++ b/sim/testsuite/sim/frv/nfmss.cgs @@ -0,0 +1,279 @@ +# frv testcase for nfmss $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfmss +nfmss: + nfmss fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfmss fr4,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr0,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr56,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr60,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0x6,fner1 + test_spr_immed 0,fner0 + + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfmss fr48,fr32,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr52,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr56,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr60,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0x6,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nfmsubs.cgs b/sim/testsuite/sim/frv/nfmsubs.cgs new file mode 100644 index 00000000000..1ae87e36d1f --- /dev/null +++ b/sim/testsuite/sim/frv/nfmsubs.cgs @@ -0,0 +1,227 @@ +# frv testcase for nfmsubs $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfmsubs +nfmsubs: + set_fr_fr fr16,fr1 + nfmsubs fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmsubs fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr16,fr1 + nfmsubs fr28,fr0,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr4,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr12,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr24,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr32,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr36,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr40,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr44,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr48,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr52,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr32,fr1 + nfmsubs fr8,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr36,fr1 + nfmsubs fr36,fr36,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmsubs fr32,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO test cases to set ne flags + pass diff --git a/sim/testsuite/sim/frv/nfmuls.cgs b/sim/testsuite/sim/frv/nfmuls.cgs new file mode 100644 index 00000000000..b59ca425e45 --- /dev/null +++ b/sim/testsuite/sim/frv/nfmuls.cgs @@ -0,0 +1,228 @@ +# frv testcase for nfmuls $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfmuls +nfmuls: + nfmuls fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr28,fr0,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr4,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr12,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr24,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr32,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr36,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr40,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr44,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr48,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr52,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr28,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr8,fr28,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr32,fr36,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfmuls fr48,fr32,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr52,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr56,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr60,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nfsqrts.cgs b/sim/testsuite/sim/frv/nfsqrts.cgs new file mode 100644 index 00000000000..419826aac96 --- /dev/null +++ b/sim/testsuite/sim/frv/nfsqrts.cgs @@ -0,0 +1,35 @@ +# frv testcase for nfsqrts $FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfsqrts +nfsqrts: + nfsqrts fr44,fr1 ; 9.0 + test_fr_fr fr1,fr36 ; 3.0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + nfsqrts fr10,fr10 + test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; fp_exceptions + nfsqrts fr8,fr1 ; -1 -- invalid + test_fr_iimmed 0x7fc00000,fr1 ; nan1 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + test_spr_bits 0x80000000,31,0x0,fqst0 ; fq0.miv is clear + test_spr_bits 0x18000,15,0x0,fqst0 ; fq0.sie is clear + test_spr_bits 0x380,7,0x0,fqst0 ; fq0.ftt is clear + test_spr_bits 0x7e,1,0x0,fqst0 ; fq0.cexc is clear + test_spr_bits 0x1,0,0x0,fqst0 ; fq0.valid is clear + test_spr_immed 0,fqop0 ; fq0.opc + + pass diff --git a/sim/testsuite/sim/frv/nfstoi.cgs b/sim/testsuite/sim/frv/nfstoi.cgs new file mode 100644 index 00000000000..0fc5a7a18d7 --- /dev/null +++ b/sim/testsuite/sim/frv/nfstoi.cgs @@ -0,0 +1,49 @@ +# frv testcase for nfstoi $FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfstoi +nfstoi: + nfstoi fr16,fr1 + test_fr_iimmed 0,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfstoi fr20,fr1 + test_fr_iimmed 0,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfstoi fr32,fr1 + test_fr_iimmed 0x00000002,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0xce05,0x4904,fr1 + nfstoi fr1,fr1 + test_fr_iimmed 0xdeadbf00,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; These were an attempt to cause overflow and nan exceptions + nfstoi fr48,fr1 + test_fr_iimmed 0x7fffffff,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfstoi fr52,fr1 + test_fr_iimmed 0x7fffffff,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfstoi fr56,fr1 + test_fr_iimmed 0x80000000,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nfsubs.cgs b/sim/testsuite/sim/frv/nfsubs.cgs new file mode 100644 index 00000000000..aea8aa300e7 --- /dev/null +++ b/sim/testsuite/sim/frv/nfsubs.cgs @@ -0,0 +1,163 @@ +# frv testcase for nfsubs $FRi,$FRj,$FRk +# mach: fr500 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfsubs +nfsubs: + nfsubs fr0,fr16,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr4,fr16,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr8,fr16,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr12,fr16,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr24,fr16,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr28,fr16,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr32,fr16,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr36,fr16,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr40,fr16,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr44,fr16,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr48,fr16,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr52,fr16,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr0,fr20,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr4,fr20,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr8,fr20,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr12,fr20,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr24,fr20,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr28,fr20,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr32,fr20,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr36,fr20,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr40,fr20,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr44,fr20,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr48,fr20,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr52,fr20,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr32,fr36,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr44,fr40,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfsubs fr4,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr0,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr56,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr60,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/sim/frv/nld.cgs b/sim/testsuite/sim/frv/nld.cgs new file mode 100644 index 00000000000..297468b44d6 --- /dev/null +++ b/sim/testsuite/sim/frv/nld.cgs @@ -0,0 +1,42 @@ +# frv testcase for nld @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nld +nld: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + nld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + nld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldbf.cgs b/sim/testsuite/sim/frv/nldbf.cgs new file mode 100644 index 00000000000..1a5c25b6741 --- /dev/null +++ b/sim/testsuite/sim/frv/nldbf.cgs @@ -0,0 +1,42 @@ +# frv testcase for nldbf @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldbf +nldbf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + test_spr_limmed 0xc800,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + nldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + test_spr_limmed 0xc800,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_spr_limmed 0xc800,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldbfi.cgs b/sim/testsuite/sim/frv/nldbfi.cgs new file mode 100644 index 00000000000..aa90bc91194 --- /dev/null +++ b/sim/testsuite/sim/frv/nldbfi.cgs @@ -0,0 +1,39 @@ +# frv testcase for nldbfi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldbfi +nldbfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + nldbfi @(sp,0),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + test_spr_limmed 0xc800,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 1,gr20 + nldbfi @(sp,1),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + test_spr_limmed 0xc800,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + nldbfi @(sp,-1),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_spr_limmed 0xc800,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldbfu.cgs b/sim/testsuite/sim/frv/nldbfu.cgs new file mode 100644 index 00000000000..174042b4bc1 --- /dev/null +++ b/sim/testsuite/sim/frv/nldbfu.cgs @@ -0,0 +1,46 @@ +# frv testcase for nldbfu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldbfu +nldbfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + nldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc800,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + nldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc800,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc800,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldd.cgs b/sim/testsuite/sim/frv/nldd.cgs new file mode 100644 index 00000000000..1f457611709 --- /dev/null +++ b/sim/testsuite/sim/frv/nldd.cgs @@ -0,0 +1,50 @@ +# frv testcase for nldd @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldd +nldd: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + nldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + nldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nlddf.cgs b/sim/testsuite/sim/frv/nlddf.cgs new file mode 100644 index 00000000000..d30b6dd2385 --- /dev/null +++ b/sim/testsuite/sim/frv/nlddf.cgs @@ -0,0 +1,50 @@ +# frv testcase for nlddf @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlddf +nlddf: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nlddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + nlddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + nlddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nlddfi.cgs b/sim/testsuite/sim/frv/nlddfi.cgs new file mode 100644 index 00000000000..b58ad6ffe3c --- /dev/null +++ b/sim/testsuite/sim/frv/nlddfi.cgs @@ -0,0 +1,47 @@ +# frv testcase for nlddfi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlddfi +nlddfi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_gr sp,gr20 + nlddfi @(sp,0),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + nlddfi @(sp,8),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + nlddfi @(sp,-8),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nlddfu.cgs b/sim/testsuite/sim/frv/nlddfu.cgs new file mode 100644 index 00000000000..d45c995cd2c --- /dev/null +++ b/sim/testsuite/sim/frv/nlddfu.cgs @@ -0,0 +1,53 @@ +# frv testcase for nlddfu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlddfu +nlddfu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + nlddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + nlddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + nlddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nlddi.cgs b/sim/testsuite/sim/frv/nlddi.cgs new file mode 100644 index 00000000000..04d24875417 --- /dev/null +++ b/sim/testsuite/sim/frv/nlddi.cgs @@ -0,0 +1,47 @@ +# frv testcase for nlddi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlddi +nlddi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_gr sp,gr20 + nlddi @(sp,0),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + nlddi @(sp,8),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + nlddi @(sp,-8),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nlddu.cgs b/sim/testsuite/sim/frv/nlddu.cgs new file mode 100644 index 00000000000..44565c8a6ff --- /dev/null +++ b/sim/testsuite/sim/frv/nlddu.cgs @@ -0,0 +1,66 @@ +# frv testcase for nlddu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlddu +nlddu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + nlddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + test_spr_limmed 0x88a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + nlddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + test_spr_limmed 0x88a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + nlddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + test_spr_limmed 0x88a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_gr_gr sp,gr8 + nlddu @(gr8,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0c01,nesr3 + test_spr_gr neear3,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldf.cgs b/sim/testsuite/sim/frv/nldf.cgs new file mode 100644 index 00000000000..6aabc67ea57 --- /dev/null +++ b/sim/testsuite/sim/frv/nldf.cgs @@ -0,0 +1,42 @@ +# frv testcase for nldf @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldf +nldf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + nldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + nldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldfi.cgs b/sim/testsuite/sim/frv/nldfi.cgs new file mode 100644 index 00000000000..20f62dfc15f --- /dev/null +++ b/sim/testsuite/sim/frv/nldfi.cgs @@ -0,0 +1,39 @@ +# frv testcase for nldfi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldfi +nldfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + nldfi @(sp,0),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + nldfi @(sp,4),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + nldfi @(sp,-4),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldfu.cgs b/sim/testsuite/sim/frv/nldfu.cgs new file mode 100644 index 00000000000..8e95016b608 --- /dev/null +++ b/sim/testsuite/sim/frv/nldfu.cgs @@ -0,0 +1,45 @@ +# frv testcase for nldfu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldfu +nldfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + nldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc880,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + nldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc880,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + nldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc880,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldhf.cgs b/sim/testsuite/sim/frv/nldhf.cgs new file mode 100644 index 00000000000..b90d8f9f301 --- /dev/null +++ b/sim/testsuite/sim/frv/nldhf.cgs @@ -0,0 +1,41 @@ +# frv testcase for nldhf @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldhf +nldhf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + test_spr_limmed 0xc840,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + nldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + test_spr_limmed 0xc840,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_spr_limmed 0xc840,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldhfi.cgs b/sim/testsuite/sim/frv/nldhfi.cgs new file mode 100644 index 00000000000..bcd52ed6e99 --- /dev/null +++ b/sim/testsuite/sim/frv/nldhfi.cgs @@ -0,0 +1,38 @@ +# frv testcase for nldhfi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldhfi +nldhfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + nldhfi @(sp,0),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + test_spr_limmed 0xc840,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + nldhfi @(sp,2),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + test_spr_limmed 0xc840,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + nldhfi @(sp,-2),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_spr_limmed 0xc840,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldhfu.cgs b/sim/testsuite/sim/frv/nldhfu.cgs new file mode 100644 index 00000000000..97d1dd9037f --- /dev/null +++ b/sim/testsuite/sim/frv/nldhfu.cgs @@ -0,0 +1,45 @@ +# frv testcase for nldhfu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldhfu +nldhfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + nldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc840,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + nldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc840,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc840,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldi.cgs b/sim/testsuite/sim/frv/nldi.cgs new file mode 100644 index 00000000000..c70f0cb9eb4 --- /dev/null +++ b/sim/testsuite/sim/frv/nldi.cgs @@ -0,0 +1,39 @@ +# frv testcase for nldi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldi +nldi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + nldi @(sp,0),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + nldi @(sp,4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + nldi @(sp,-4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldq.cgs b/sim/testsuite/sim/frv/nldq.cgs new file mode 100644 index 00000000000..0338e19fc0c --- /dev/null +++ b/sim/testsuite/sim/frv/nldq.cgs @@ -0,0 +1,67 @@ +# frv testcase for nldq @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldq +nldq: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_spr_limmed 0x88c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + nldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_spr_limmed 0x88c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + nldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_spr_limmed 0x88c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldqf.cgs b/sim/testsuite/sim/frv/nldqf.cgs new file mode 100644 index 00000000000..8e268acc85d --- /dev/null +++ b/sim/testsuite/sim/frv/nldqf.cgs @@ -0,0 +1,67 @@ +# frv testcase for nldqf @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldqf +nldqf: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + nldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + nldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldqfi.cgs b/sim/testsuite/sim/frv/nldqfi.cgs new file mode 100644 index 00000000000..ff05fae7ad3 --- /dev/null +++ b/sim/testsuite/sim/frv/nldqfi.cgs @@ -0,0 +1,64 @@ +# frv testcase for nldqfi @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldqfi +nldqfi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + set_gr_gr sp,gr20 + nldqfi @(sp,0),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + nldqfi @(sp,16),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 32,sp + nldqfi @(sp,-16),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldqfu.cgs b/sim/testsuite/sim/frv/nldqfu.cgs new file mode 100644 index 00000000000..ffe2990cff0 --- /dev/null +++ b/sim/testsuite/sim/frv/nldqfu.cgs @@ -0,0 +1,70 @@ +# frv testcase for nldqfu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldqfu +nldqfu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + set_gr_immed 0,gr7 + nldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + nldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + nldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldqi.cgs b/sim/testsuite/sim/frv/nldqi.cgs new file mode 100644 index 00000000000..d820322a976 --- /dev/null +++ b/sim/testsuite/sim/frv/nldqi.cgs @@ -0,0 +1,64 @@ +# frv testcase for nldqi @($GRi,$d12),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldqi +nldqi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_gr sp,gr20 + nldqi @(sp,0),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_spr_limmed 0x88c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + nldqi @(sp,16),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_spr_limmed 0x88c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + nldqi @(sp,-16),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_spr_limmed 0x88c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldqu.cgs b/sim/testsuite/sim/frv/nldqu.cgs new file mode 100644 index 00000000000..a7e8b30fd2a --- /dev/null +++ b/sim/testsuite/sim/frv/nldqu.cgs @@ -0,0 +1,87 @@ +# frv testcase for nldqu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldqu +nldqu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + nldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + test_spr_limmed 0x88c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + nldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + test_spr_limmed 0x88c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + nldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + test_spr_limmed 0x88c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + set_gr_gr sp,gr8 + nldqu @(gr8,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_spr_limmed 0x88c0,0x0c01,nesr3 + test_spr_gr neear3,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldsb.cgs b/sim/testsuite/sim/frv/nldsb.cgs new file mode 100644 index 00000000000..1db547c7cab --- /dev/null +++ b/sim/testsuite/sim/frv/nldsb.cgs @@ -0,0 +1,42 @@ +# frv testcase for nldsb @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldsb +nldsb: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldsb @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + test_spr_limmed 0x8820,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + nldsb @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + test_spr_limmed 0x8820,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldsb @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_spr_limmed 0x8820,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldsbi.cgs b/sim/testsuite/sim/frv/nldsbi.cgs new file mode 100644 index 00000000000..4b9dcba3e68 --- /dev/null +++ b/sim/testsuite/sim/frv/nldsbi.cgs @@ -0,0 +1,39 @@ +# frv testcase for nldsbi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldsbi +nldsbi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + nldsbi @(sp,0),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + test_spr_limmed 0x8820,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr20 + nldsbi @(sp,1),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + test_spr_limmed 0x8820,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + nldsbi @(sp,-1),gr8 + test_gr_immed 0,gr8 + test_spr_limmed 0x8820,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldsbu.cgs b/sim/testsuite/sim/frv/nldsbu.cgs new file mode 100644 index 00000000000..e60ffc011e2 --- /dev/null +++ b/sim/testsuite/sim/frv/nldsbu.cgs @@ -0,0 +1,56 @@ +# frv testcase for nldsbu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldsbu +nldsbu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + nldsbu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8820,0x0001,nesr0 + test_spr_gr neear0,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + nldsbu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8820,0x0401,nesr1 + test_spr_gr neear1,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldsbu @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8820,0x0801,nesr2 + test_spr_gr neear2,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -3,sp + set_mem_limmed 0x0000,0x00da,sp + set_gr_immed 3,gr7 + nldsbu @(sp,gr7),sp + test_gr_limmed 0xffff,0xffda,sp + test_spr_limmed 0x8120,0x0c01,nesr3 + test_spr_gr neear3,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldsh.cgs b/sim/testsuite/sim/frv/nldsh.cgs new file mode 100644 index 00000000000..afc00c49df5 --- /dev/null +++ b/sim/testsuite/sim/frv/nldsh.cgs @@ -0,0 +1,41 @@ +# frv testcase for nldsh @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldsh +nldsh: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldsh @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + test_spr_limmed 0x8860,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + nldsh @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + test_spr_limmed 0x8860,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nldsh @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_spr_limmed 0x8860,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldshi.cgs b/sim/testsuite/sim/frv/nldshi.cgs new file mode 100644 index 00000000000..60de1564874 --- /dev/null +++ b/sim/testsuite/sim/frv/nldshi.cgs @@ -0,0 +1,38 @@ +# frv testcase for nldshi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldshi +nldshi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + nldshi @(sp,0),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + test_spr_limmed 0x8860,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + nldshi @(sp,2),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + test_spr_limmed 0x8860,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + nldshi @(sp,-2),gr8 + test_gr_immed 0,gr8 + test_spr_limmed 0x8860,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldshu.cgs b/sim/testsuite/sim/frv/nldshu.cgs new file mode 100644 index 00000000000..775b760df8f --- /dev/null +++ b/sim/testsuite/sim/frv/nldshu.cgs @@ -0,0 +1,55 @@ +# frv testcase for nldshu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldshu +nldshu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + nldshu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8860,0x0001,nesr0 + test_spr_gr neear0,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + nldshu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8860,0x0401,nesr1 + test_spr_gr neear1,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nldshu @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8860,0x0801,nesr2 + test_spr_gr neear2,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -2,sp + set_mem_limmed 0x0000,0xdead,sp + set_gr_immed 2,gr7 + nldshu @(sp,gr7),sp + test_gr_limmed 0xffff,0xdead,sp + test_spr_limmed 0x8160,0x0c01,nesr3 + test_spr_gr neear3,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldu.cgs b/sim/testsuite/sim/frv/nldu.cgs new file mode 100644 index 00000000000..0d1735e8848 --- /dev/null +++ b/sim/testsuite/sim/frv/nldu.cgs @@ -0,0 +1,55 @@ +# frv testcase for nldu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldu +nldu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + nldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8880,0x0001,nesr0 + test_spr_gr neear0,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + nldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8880,0x0401,nesr1 + test_spr_gr neear1,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + nldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8880,0x0801,nesr2 + test_spr_gr neear2,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + nldu @(sp,gr7),sp + test_gr_limmed 0xdead,0xbeef,sp + test_spr_limmed 0x8180,0x0c01,nesr3 + test_spr_gr neear3,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldub.cgs b/sim/testsuite/sim/frv/nldub.cgs new file mode 100644 index 00000000000..2067bcc089d --- /dev/null +++ b/sim/testsuite/sim/frv/nldub.cgs @@ -0,0 +1,42 @@ +# frv testcase for nldub @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldub +nldub: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + test_spr_limmed 0x8800,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + nldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + test_spr_limmed 0x8800,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_spr_limmed 0x8800,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldubi.cgs b/sim/testsuite/sim/frv/nldubi.cgs new file mode 100644 index 00000000000..8eba5164120 --- /dev/null +++ b/sim/testsuite/sim/frv/nldubi.cgs @@ -0,0 +1,39 @@ +# frv testcase for nldubi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldubi +nldubi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + nldubi @(sp,0),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + test_spr_limmed 0x8800,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr20 + nldubi @(sp,1),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + test_spr_limmed 0x8800,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + nldubi @(sp,-1),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_spr_limmed 0x8800,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldubu.cgs b/sim/testsuite/sim/frv/nldubu.cgs new file mode 100644 index 00000000000..acf9d9c818e --- /dev/null +++ b/sim/testsuite/sim/frv/nldubu.cgs @@ -0,0 +1,55 @@ +# frv testcase for nldubu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldubu +nldubu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + nldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8800,0x0001,nesr0 + test_spr_gr neear0,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + nldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8800,0x0401,nesr1 + test_spr_gr neear1,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_spr_limmed 0x8800,0x0801,nesr2 + test_spr_gr neear2,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -3,sp + set_mem_limmed 0xffff,0xffda,sp + set_gr_immed 3,gr7 + nldubu @(sp,gr7),sp + test_gr_limmed 0x0000,0x00da,sp + test_spr_limmed 0x8100,0x0c01,nesr3 + test_spr_gr neear3,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nlduh.cgs b/sim/testsuite/sim/frv/nlduh.cgs new file mode 100644 index 00000000000..1871a22044b --- /dev/null +++ b/sim/testsuite/sim/frv/nlduh.cgs @@ -0,0 +1,41 @@ +# frv testcase for nlduh @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlduh +nlduh: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nlduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + test_spr_limmed 0x8840,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + nlduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + test_spr_limmed 0x8840,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nlduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_spr_limmed 0x8840,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nlduhi.cgs b/sim/testsuite/sim/frv/nlduhi.cgs new file mode 100644 index 00000000000..ae7171ee417 --- /dev/null +++ b/sim/testsuite/sim/frv/nlduhi.cgs @@ -0,0 +1,38 @@ +# frv testcase for nlduhi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlduhi +nlduhi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + nlduhi @(sp,0),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + test_spr_limmed 0x8840,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + nlduhi @(sp,2),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + test_spr_limmed 0x8840,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + nlduhi @(sp,-2),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_spr_limmed 0x8840,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nlduhu.cgs b/sim/testsuite/sim/frv/nlduhu.cgs new file mode 100644 index 00000000000..8142fc59517 --- /dev/null +++ b/sim/testsuite/sim/frv/nlduhu.cgs @@ -0,0 +1,55 @@ +# frv testcase for nlduhu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlduhu +nlduhu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + nlduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8840,0x0001,nesr0 + test_spr_gr neear0,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + nlduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8840,0x0401,nesr1 + test_spr_gr neear1,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nlduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8840,0x0801,nesr2 + test_spr_gr neear2,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0xdead,sp + set_gr_immed 2,gr7 + nlduhu @(sp,gr7),sp + test_gr_limmed 0x0000,0xdead,sp + test_spr_limmed 0x8140,0x0c01,nesr3 + test_spr_gr neear3,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nop.cgs b/sim/testsuite/sim/frv/nop.cgs new file mode 100644 index 00000000000..7180066ce9c --- /dev/null +++ b/sim/testsuite/sim/frv/nop.cgs @@ -0,0 +1,12 @@ +# frv testcase for nop +# mach: all + + .include "testutils.inc" + + start + + .global nop +nop: + nop + + pass diff --git a/sim/testsuite/sim/frv/norcr.cgs b/sim/testsuite/sim/frv/norcr.cgs new file mode 100644 index 00000000000..e097a1b3667 --- /dev/null +++ b/sim/testsuite/sim/frv/norcr.cgs @@ -0,0 +1,59 @@ +# frv testcase for norcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global norcr +norcr: + set_spr_immed 0x1b1b,cccr + norcr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + norcr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + norcr cc7,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norcr cc7,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + norcr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + norcr cc6,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norcr cc6,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc5,cc7,cc3 + test_spr_immed 0x1bdb,cccr + + norcr cc5,cc6,cc3 + test_spr_immed 0x1bdb,cccr + + norcr cc5,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norcr cc5,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc4,cc7,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc4,cc6,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc4,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc4,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/sim/frv/norncr.cgs b/sim/testsuite/sim/frv/norncr.cgs new file mode 100644 index 00000000000..a7b95da6b6b --- /dev/null +++ b/sim/testsuite/sim/frv/norncr.cgs @@ -0,0 +1,59 @@ +# frv testcase for norncr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global norncr +norncr: + set_spr_immed 0x1b1b,cccr + norncr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + norncr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + norncr cc7,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norncr cc7,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + norncr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + norncr cc6,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norncr cc6,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc5,cc7,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc5,cc6,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc5,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc5,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc4,cc7,cc3 + test_spr_immed 0x1bdb,cccr + + norncr cc4,cc6,cc3 + test_spr_immed 0x1bdb,cccr + + norncr cc4,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norncr cc4,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/sim/frv/not.cgs b/sim/testsuite/sim/frv/not.cgs new file mode 100644 index 00000000000..e44eabfcd0a --- /dev/null +++ b/sim/testsuite/sim/frv/not.cgs @@ -0,0 +1,18 @@ +# frv testcase for not $GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global not +not: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + not gr7,gr7 + test_gr_limmed 0x5555,0x5555,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + not gr7,gr7 + test_gr_limmed 0x2152,0x4110,gr7 + + pass diff --git a/sim/testsuite/sim/frv/notcr.cgs b/sim/testsuite/sim/frv/notcr.cgs new file mode 100644 index 00000000000..e6c08e0603a --- /dev/null +++ b/sim/testsuite/sim/frv/notcr.cgs @@ -0,0 +1,23 @@ +# frv testcase for notcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global notcr +notcr: + set_spr_immed 0x1b1b,cccr + notcr cc7,cc3 + test_spr_immed 0x1b5b,cccr + + notcr cc6,cc3 + test_spr_immed 0x1b1b,cccr + + notcr cc5,cc3 + test_spr_immed 0x1bdb,cccr + + notcr cc4,cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/sim/frv/nsdiv.cgs b/sim/testsuite/sim/frv/nsdiv.cgs new file mode 100644 index 00000000000..f52452d1cb4 --- /dev/null +++ b/sim/testsuite/sim/frv/nsdiv.cgs @@ -0,0 +1,64 @@ +# frv testcase for nsdiv $GRi,$GRj,$GRk +# mach: fr500 frv + + .include "testutils.inc" + + start + + .global nsdiv +nsdiv: + set_spr_immed 0,gner0 + set_spr_immed 0,gner1 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + nsdiv gr1,gr3,gr2 + test_gr_immed 4,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + nsdiv gr1,gr3,gr2 + test_gr_immed -1,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + set_spr_immed 4,gner1 ; turn on NE bit for gr2 + nsdiv gr1,gr3,gr2 ; overflow is masked + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + nsdiv gr1,gr0,gr32 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + nsdiv gr1,gr3,gr2 + test_gr_limmed 0x8000,0x0000,gr2 + test_spr_immed 1,gner0 + test_spr_immed 4,gner1 + + nsdiv gr1,gr0,gr10 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0x00000404,gner1 + + ; simple division 12 / 3 -- should turn off ne flag + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + nsdiv gr1,gr3,gr2 + test_gr_immed 4,gr2 + test_spr_immed 1,gner0 + test_spr_immed 0x00000400,gner1 + + pass diff --git a/sim/testsuite/sim/frv/nsdivi.cgs b/sim/testsuite/sim/frv/nsdivi.cgs new file mode 100644 index 00000000000..d167d743630 --- /dev/null +++ b/sim/testsuite/sim/frv/nsdivi.cgs @@ -0,0 +1,64 @@ +# frv testcase for nsdivi $GRi,$s12,$GRk +# mach: fr500 frv + + .include "testutils.inc" + + start + + .global nsdivi +nsdivi: + set_spr_immed 0,gner0 + set_spr_immed 0,gner1 + + ; simple division 12 / 3 + set_gr_immed 12,gr1 + nsdivi gr1,3,gr2 + test_gr_immed 4,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; Random example + set_gr_limmed 0xfedc,0xba98,gr1 + nsdivi gr1,0x7ff,gr2 + test_gr_limmed 0xffff,0xdb93,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; Random negative example + set_gr_limmed 0xfedc,0xba98,gr1 + nsdivi gr1,-2048,gr2 + test_gr_immed 0x2468,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_limmed 0x8000,0x0000,gr1 + nsdivi gr1,-1,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + nsdivi gr1,0,gr32 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_limmed 0x8000,0x0000,gr1 + nsdivi gr1,-1,gr2 + test_gr_limmed 0x8000,0x0000,gr2 + test_spr_immed 1,gner0 + test_spr_immed 4,gner1 + + nsdivi gr1,0,gr10 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0x00000404,gner1 + + ; simple division 12 / 3 -- should turn off ne flag + set_gr_immed 12,gr1 + nsdivi gr1,3,gr2 + test_gr_immed 4,gr2 + test_spr_immed 1,gner0 + test_spr_immed 0x00000400,gner1 + + pass diff --git a/sim/testsuite/sim/frv/nudiv.cgs b/sim/testsuite/sim/frv/nudiv.cgs new file mode 100644 index 00000000000..6a4e59cf750 --- /dev/null +++ b/sim/testsuite/sim/frv/nudiv.cgs @@ -0,0 +1,49 @@ +# frv testcase for nudiv $GRi,$GRj,$GRk +# mach: fr500 frv + + .include "testutils.inc" + + start + + .global nudiv +nudiv: + set_spr_immed 0,gner0 + set_spr_immed 0,gner1 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + nudiv gr3,gr2,gr3 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; example 1 from the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + nudiv gr3,gr2,gr3 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + or_spr_immed 0x20,isr ; turn on isr.edem + nudiv gr1,gr0,gr32 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + and_spr_immed -33,isr ; turn off isr.edem + nudiv gr1,gr0,gr10 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0x00000400,gner1 + + ; simple division 12 / 3 -- should turn off ne flag + set_gr_immed 12,gr1 + set_gr_immed 3,gr3 + nudiv gr1,gr3,gr10 + test_gr_immed 4,gr10 + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + pass diff --git a/sim/testsuite/sim/frv/nudivi.cgs b/sim/testsuite/sim/frv/nudivi.cgs new file mode 100644 index 00000000000..ea97ef8488c --- /dev/null +++ b/sim/testsuite/sim/frv/nudivi.cgs @@ -0,0 +1,51 @@ +# frv testcase for nudivi $GRi,$s12,$GRk +# mach: fr500 frv + + .include "testutils.inc" + + start + + .global nudivi +nudivi: + set_spr_immed 0,gner0 + set_spr_immed 0,gner1 + + ; simple division 12 / 3 + set_gr_immed 0x0000000c,gr3 + nudivi gr3,3,gr3 + test_gr_immed 0x00000004,gr3 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; random example + set_gr_limmed 0xfedc,0xba98,gr3 + nudivi gr3,0x7ff,gr3 + test_gr_limmed 0x001f,0xdf93,gr3 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; random example + set_gr_limmed 0xffff,0xffff,gr3 + nudivi gr3,-2048,gr3 + test_gr_immed 1,gr3 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + or_spr_immed 0x20,isr ; turn on isr.edem + nudivi gr1,0,gr32 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + and_spr_immed -33,isr ; turn off isr.edem + nudivi gr1,0,gr10 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0x00000400,gner1 + + ; simple division 12 / 3 -- should turn off ne flag + set_gr_immed 12,gr1 + nudivi gr1,3,gr10 + test_gr_immed 4,gr10 + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + pass diff --git a/sim/testsuite/sim/frv/or.cgs b/sim/testsuite/sim/frv/or.cgs new file mode 100644 index 00000000000..b432429a013 --- /dev/null +++ b/sim/testsuite/sim/frv/or.cgs @@ -0,0 +1,31 @@ +# frv testcase for or $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global or +or: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + or gr7,gr8,gr8 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + or gr7,gr8,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + or gr7,gr8,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/orcc.cgs b/sim/testsuite/sim/frv/orcc.cgs new file mode 100644 index 00000000000..a0a3e5bdeda --- /dev/null +++ b/sim/testsuite/sim/frv/orcc.cgs @@ -0,0 +1,31 @@ +# frv testcase for orcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global orcc +orcc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + orcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + orcc gr7,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + orcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/orcr.cgs b/sim/testsuite/sim/frv/orcr.cgs new file mode 100644 index 00000000000..a5114b248e7 --- /dev/null +++ b/sim/testsuite/sim/frv/orcr.cgs @@ -0,0 +1,59 @@ +# frv testcase for orcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global orcr +orcr: + set_spr_immed 0x1b1b,cccr + orcr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + orcr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + orcr cc7,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orcr cc7,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + orcr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + orcr cc6,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orcr cc6,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc5,cc7,cc3 + test_spr_immed 0x1b9b,cccr + + orcr cc5,cc6,cc3 + test_spr_immed 0x1b9b,cccr + + orcr cc5,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orcr cc5,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc4,cc7,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc4,cc6,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc4,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc4,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/ori.cgs b/sim/testsuite/sim/frv/ori.cgs new file mode 100644 index 00000000000..aa1d61a1d0a --- /dev/null +++ b/sim/testsuite/sim/frv/ori.cgs @@ -0,0 +1,34 @@ +# frv testcase for ori $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ori +ori: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x07,0 ; Set mask opposite of expected + ori gr7,0x555,gr8 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xaaaa,0xafff,gr8 + + set_gr_immed 0x00000000,gr7 + set_icc 0x08,0 ; Set mask opposite of expected + ori gr7,0,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xb800,gr7 + set_icc 0x05,0 ; Set mask opposite of expected + ori gr7,0x6ef,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xdead,0xb000,gr7 + set_icc 0x05,0 ; Set mask opposite of expected + ori gr7,-273,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xffff,0xfeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/oricc.cgs b/sim/testsuite/sim/frv/oricc.cgs new file mode 100644 index 00000000000..71e6d53320a --- /dev/null +++ b/sim/testsuite/sim/frv/oricc.cgs @@ -0,0 +1,34 @@ +# frv testcase for oricc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global oricc +oricc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x07,0 ; Set mask opposite of expected + oricc gr7,0x155,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xabff,gr8 + + set_gr_immed 0x00000000,gr7 + set_icc 0x08,0 ; Set mask opposite of expected + oricc gr7,0,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbe00,gr7 + set_icc 0x05,0 ; Set mask opposite of expected + oricc gr7,0x0ef,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xdead,0xb000,gr7 + set_icc 0x05,0 ; Set mask opposite of expected + oricc gr7,-273,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xfeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/orncr.cgs b/sim/testsuite/sim/frv/orncr.cgs new file mode 100644 index 00000000000..b0e4e5914f8 --- /dev/null +++ b/sim/testsuite/sim/frv/orncr.cgs @@ -0,0 +1,59 @@ +# frv testcase for orncr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global orncr +orncr: + set_spr_immed 0x1b1b,cccr + orncr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + orncr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + orncr cc7,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orncr cc7,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + orncr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + orncr cc6,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orncr cc6,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc5,cc7,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc5,cc6,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc5,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc5,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc4,cc7,cc3 + test_spr_immed 0x1b9b,cccr + + orncr cc4,cc6,cc3 + test_spr_immed 0x1b9b,cccr + + orncr cc4,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orncr cc4,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/parallel.exp b/sim/testsuite/sim/frv/parallel.exp new file mode 100644 index 00000000000..d1fff4fda35 --- /dev/null +++ b/sim/testsuite/sim/frv/parallel.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "frv fr500 fr400" + set cpu_option -mcpu + + # The .pcgs suffix is for "parallel cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.pcgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/frv/ret.cgs b/sim/testsuite/sim/frv/ret.cgs new file mode 100644 index 00000000000..14479980a59 --- /dev/null +++ b/sim/testsuite/sim/frv/ret.cgs @@ -0,0 +1,91 @@ +# frv testcase for ret +# mach: all + + .include "testutils.inc" + + start + + .global ret +ret: + set_spr_addr ok1,lr + set_icc 0x0 0 + ret + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + ret + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + ret + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + ret + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + ret + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + ret + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + ret + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + ret + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + ret + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + ret + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + ret + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + ret + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + ret + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + ret + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + ret + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + ret + fail +okg: + + pass diff --git a/sim/testsuite/sim/frv/rett.cgs b/sim/testsuite/sim/frv/rett.cgs new file mode 100644 index 00000000000..f964baea2aa --- /dev/null +++ b/sim/testsuite/sim/frv/rett.cgs @@ -0,0 +1,30 @@ +# frv testcase for rett $debug +# mach: all + + .include "testutils.inc" + + start + + .global rett +rett: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x0 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 +ok0: + test_gr_immed 1,gr7 + pass + fail +ok1: + inc_gr_immed 1,gr7 + rett 1 ; should be a nop + rett 0 + fail diff --git a/sim/testsuite/sim/frv/rst.cgs b/sim/testsuite/sim/frv/rst.cgs new file mode 100644 index 00000000000..c8ba442516d --- /dev/null +++ b/sim/testsuite/sim/frv/rst.cgs @@ -0,0 +1,107 @@ +# frv testcase for rst $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global rst +rst: + ; No nesr's active + set_gr_gr sp,gr10 + set_gr_gr sp,gr24 + set_mem_limmed 0x2222,0x2222,gr24 + set_gr_gr gr24,gr27 + inc_gr_immed -4,gr27 + set_mem_limmed 0x3333,0x3333,gr27 + set_gr_gr gr27,gr26 + inc_gr_immed -4,gr26 + set_mem_limmed 0x4444,0x4444,gr26 + set_gr_gr gr26,gr25 + inc_gr_immed -4,gr25 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + rst gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_gr_limmed 0x1111,0x1111,gr20 + + ; 1 nesr active with the incorrect address in neear for gr + nldi @(sp,0),gr20 + test_spr_gr neear0,gr10 + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_gr_limmed 0xffff,0xffff,gr8 + set_gr_immed -4,gr7 + rst gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr24 + test_mem_limmed 0xffff,0xffff,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_gr_limmed 0x1111,0x1111,gr20 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -4,gr10 + nldfi @(sp,-4),fr20 + test_spr_gr neear1,gr10 + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_fr_iimmed 0x1111,0x1111,fr20 + set_gr_limmed 0xffff,0xffff,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + rst gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for gr + inc_gr_immed -4,gr10 + nldi @(sp,-4),gr20 + test_spr_gr neear2,gr10 + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_gr_limmed 0xffff,0xffff,gr8 + inc_gr_immed -4,sp + set_gr_immed 0,gr7 + rst gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_gr_limmed 0xffff,0xffff,gr20 + + ; 1 nesr active with the correct address in neear for fr + inc_gr_immed -4,gr10 + nldfi @(sp,-4),fr20 + test_spr_gr neear3,gr10 + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_fr_iimmed 0x1111,0x1111,fr20 + set_gr_limmed 0xffff,0xffff,gr8 + set_gr_immed -4,gr7 + rst gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0xffff,0xffff,gr25 + test_fr_limmed 0xffff,0xffff,fr20 + + pass diff --git a/sim/testsuite/sim/frv/rstb.cgs b/sim/testsuite/sim/frv/rstb.cgs new file mode 100644 index 00000000000..e7bab4231a7 --- /dev/null +++ b/sim/testsuite/sim/frv/rstb.cgs @@ -0,0 +1,72 @@ +# frv testcase for rstb $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr21 + set_gr_gr gr21,gr22 + set_gr_limmed 0x1111,0x1111,gr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + rstb gr8,@(sp,gr7) + test_mem_limmed 0xff22,0x2222,sp + test_gr_limmed 0x1111,0x1111,gr20 + + ; 1 nesr active with the incorrect address in neear for gr + inc_gr_immed 3,gr22 + nldubi @(sp,3),gr20 + test_spr_gr neear0,gr22 + set_gr_limmed 0x1111,0x1111,gr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_gr_limmed 0xffff,0xffff,gr8 + inc_gr_immed 1,gr7 + rstb gr8,@(sp,gr7) + test_mem_limmed 0x22ff,0x2222,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -1,gr22 + nldbfi @(sp,2),fr20 + test_spr_gr neear1,gr22 + set_fr_iimmed 0x1111,0x1111,fr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_gr_limmed 0xffff,0xffff,gr8 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + rstb gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x22ff,gr21 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for gr + inc_gr_immed -1,gr22 + nldubi @(sp,-3),gr20 + test_spr_gr neear2,gr22 + set_gr_limmed 0x1111,0x1111,gr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_gr_limmed 0xffff,0xffff,gr8 + inc_gr_immed -4,sp + set_gr_immed 1,gr7 + rstb gr8,@(sp,gr7) + test_mem_limmed 0x22ff,0x2222,gr21 + test_gr_limmed 0x0000,0x00ff,gr20 + + ; 1 nesr active with the correct address in neear for fr + inc_gr_immed -1,gr22 + nldbfi @(sp,0),fr20 + test_spr_gr neear3,gr22 + set_fr_iimmed 0x1111,0x1111,fr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_gr_limmed 0xffff,0xffff,gr8 + set_gr_immed 0,gr7 + rstb gr8,@(sp,gr7) + test_mem_limmed 0xff22,0x2222,gr21 + test_fr_limmed 0x0000,0x00ff,fr20 + + pass diff --git a/sim/testsuite/sim/frv/rstbf.cgs b/sim/testsuite/sim/frv/rstbf.cgs new file mode 100644 index 00000000000..e35260a4825 --- /dev/null +++ b/sim/testsuite/sim/frv/rstbf.cgs @@ -0,0 +1,76 @@ +# frv testcase for rstbf $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr21 + set_gr_gr gr21,gr22 + set_fr_iimmed 0x1111,0x1111,fr20 + set_gr_limmed 0x1111,0x1111,gr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + rstbf fr8,@(sp,gr7) + test_mem_limmed 0xff22,0x2222,sp + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the incorrect address in neear for gr + inc_gr_immed 1,gr22 + nldubi @(sp,1),gr20 + test_spr_gr neear0,gr22 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_fr_iimmed 0xffff,0xffff,fr8 + inc_gr_immed 2,gr7 + rstbf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0xff22,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -1,gr22 + nldbfi @(sp,0),fr20 + test_spr_gr neear1,gr22 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_fr_iimmed 0xffff,0xffff,fr8 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + rstbf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x22ff,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for gr + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_fr_iimmed 0xffff,0xffff,fr8 + inc_gr_immed -4,sp + set_gr_immed 1,gr7 + rstbf fr8,@(sp,gr7) + test_mem_limmed 0x22ff,0x2222,gr21 + test_gr_limmed 0x0000,0x00ff,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for fr + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_fr_iimmed 0xffff,0xffff,fr8 + set_gr_immed 0,gr7 + rstbf fr8,@(sp,gr7) + test_mem_limmed 0xff22,0x2222,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x0000,0x00ff,fr20 + + pass diff --git a/sim/testsuite/sim/frv/rstd.cgs b/sim/testsuite/sim/frv/rstd.cgs new file mode 100644 index 00000000000..bf676351c67 --- /dev/null +++ b/sim/testsuite/sim/frv/rstd.cgs @@ -0,0 +1,171 @@ +# frv testcase for rstd $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr20 + set_mem_limmed 0x2222,0x2222,gr20 + set_gr_gr gr20,gr27 + inc_gr_immed -4,gr27 + set_mem_limmed 0x3333,0x3333,gr27 + set_gr_gr gr27,gr26 + inc_gr_immed -4,gr26 + set_mem_limmed 0x4444,0x4444,gr26 + set_gr_gr gr26,gr25 + inc_gr_immed -4,gr25 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_gr gr25,gr24 + inc_gr_immed -4,gr24 + set_mem_limmed 0x6666,0x6666,gr24 + set_gr_gr gr24,gr23 + inc_gr_immed -4,gr23 + set_mem_limmed 0x7777,0x7777,gr23 + set_gr_gr gr23,gr22 + inc_gr_immed -4,gr22 + set_mem_limmed 0x8888,0x8888,gr22 + set_gr_gr gr22,gr21 + inc_gr_immed -4,gr21 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + inc_gr_immed -4,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + rstd gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr20 + test_mem_limmed 0xeeee,0xeeee,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + + ; 1 nesr active with the incorrect address in neear for gr + set_gr_gr sp,gr10 + nlddi @(sp,0),gr40 + test_spr_gr neear0,gr10 + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_immed -8,gr7 + rstd gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr20 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0xeeee,0xeeee,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -8,gr10 + nlddfi @(sp,-8),fr40 + test_spr_gr neear1,gr10 + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + rstd gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr20 + test_mem_limmed 0xeeee,0xeeee,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + + ; 1 nesr active with the correct address in neear for gr + inc_gr_immed -8,gr10 + nlddi @(sp,-8),gr40 + test_spr_gr neear2,gr10 + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + inc_gr_immed -8,sp + set_gr_immed 0,gr7 + rstd gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr20 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xeeee,0xeeee,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_gr_limmed 0xffff,0xffff,gr41 + test_gr_limmed 0xeeee,0xeeee,gr40 + + ; 1 nesr active with the correct address in neear for fr + inc_gr_immed -8,gr10 + nlddfi @(sp,-8),fr40 + test_spr_gr neear3,gr10 + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_gr_immed -8,gr7 + rstd gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr20 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xeeee,0xeeee,gr21 + test_fr_limmed 0xffff,0xffff,fr41 + test_fr_limmed 0xeeee,0xeeee,fr40 + + pass diff --git a/sim/testsuite/sim/frv/rstdf.cgs b/sim/testsuite/sim/frv/rstdf.cgs new file mode 100644 index 00000000000..9d0d841c5d4 --- /dev/null +++ b/sim/testsuite/sim/frv/rstdf.cgs @@ -0,0 +1,186 @@ +# frv testcase for rstdf $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr20 + set_mem_limmed 0x2222,0x2222,gr20 + set_gr_gr gr20,gr27 + inc_gr_immed -4,gr27 + set_mem_limmed 0x3333,0x3333,gr27 + set_gr_gr gr27,gr26 + inc_gr_immed -4,gr26 + set_mem_limmed 0x4444,0x4444,gr26 + set_gr_gr gr26,gr25 + inc_gr_immed -4,gr25 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_gr gr25,gr24 + inc_gr_immed -4,gr24 + set_mem_limmed 0x6666,0x6666,gr24 + set_gr_gr gr24,gr23 + inc_gr_immed -4,gr23 + set_mem_limmed 0x7777,0x7777,gr23 + set_gr_gr gr23,gr22 + inc_gr_immed -4,gr22 + set_mem_limmed 0x8888,0x8888,gr22 + set_gr_gr gr22,gr21 + inc_gr_immed -4,gr21 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + inc_gr_immed -4,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + rstdf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr20 + test_mem_limmed 0xeeee,0xeeee,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + + ; 1 nesr active with the incorrect address in neear for gr + set_gr_gr sp,gr10 + inc_gr_immed -16,gr10 + nlddi @(sp,-16),gr40 + test_spr_gr neear0,gr10 + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_gr_immed -8,gr7 + rstdf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr20 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0xeeee,0xeeee,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -8,gr10 + nlddfi @(sp,-24),fr40 + test_spr_gr neear1,gr10 + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + rstdf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr20 + test_mem_limmed 0xeeee,0xeeee,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + + ; 1 nesr active with the correct address in neear for gr + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + inc_gr_immed -8,sp + set_gr_immed 0,gr7 + rstdf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr20 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xeeee,0xeeee,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_gr_limmed 0xffff,0xffff,gr41 + test_gr_limmed 0xeeee,0xeeee,gr40 + test_fr_limmed 0x1111,0x1111,fr41 + test_fr_limmed 0x1111,0x1111,fr40 + + ; 1 nesr active with the correct address in neear for fr + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_gr_immed -8,gr7 + rstdf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr20 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xeeee,0xeeee,gr21 + test_gr_limmed 0x1111,0x1111,gr41 + test_gr_limmed 0x1111,0x1111,gr40 + test_fr_limmed 0xffff,0xffff,fr41 + test_fr_limmed 0xeeee,0xeeee,fr40 + + pass diff --git a/sim/testsuite/sim/frv/rstf.cgs b/sim/testsuite/sim/frv/rstf.cgs new file mode 100644 index 00000000000..17a123af26f --- /dev/null +++ b/sim/testsuite/sim/frv/rstf.cgs @@ -0,0 +1,112 @@ +# frv testcase for rstf $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr10 + set_gr_gr sp,gr24 + set_mem_limmed 0x2222,0x2222,gr24 + set_gr_gr gr24,gr27 + inc_gr_immed -4,gr27 + set_mem_limmed 0x3333,0x3333,gr27 + set_gr_gr gr27,gr26 + inc_gr_immed -4,gr26 + set_mem_limmed 0x4444,0x4444,gr26 + set_gr_gr gr26,gr25 + inc_gr_immed -4,gr25 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + rstf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the incorrect address in neear for gr + inc_gr_immed -8,gr10 + nldi @(sp,-8),gr20 + test_spr_gr neear0,gr10 + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_fr_iimmed 0xffff,0xffff,fr8 + set_gr_immed -4,gr7 + rstf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr24 + test_mem_limmed 0xffff,0xffff,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -4,gr10 + nldfi @(sp,-12),fr20 + test_spr_gr neear1,gr10 + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_fr_iimmed 0xffff,0xffff,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + rstf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for gr + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_fr_iimmed 0xffff,0xffff,fr8 + inc_gr_immed -4,sp + set_gr_immed 0,gr7 + rstf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_gr_limmed 0xffff,0xffff,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for fr + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_fr_iimmed 0xffff,0xffff,fr8 + set_gr_immed -4,gr7 + rstf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0xffff,0xffff,gr25 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0xffff,0xffff,fr20 + + pass diff --git a/sim/testsuite/sim/frv/rsth.cgs b/sim/testsuite/sim/frv/rsth.cgs new file mode 100644 index 00000000000..a2b283ef3b2 --- /dev/null +++ b/sim/testsuite/sim/frv/rsth.cgs @@ -0,0 +1,83 @@ +# frv testcase for rsth $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr22 + set_mem_limmed 0x2222,0x2222,gr22 + set_gr_gr gr22,gr21 + inc_gr_immed -4,gr21 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_gr gr22,gr23 + set_gr_limmed 0x1111,0x1111,gr20 + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + rsth gr8,@(sp,gr7) + test_mem_limmed 0xffff,0x2222,gr22 + test_mem_limmed 0x3333,0x3333,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + + ; 1 nesr active with the incorrect address in neear for gr + nlduhi @(sp,0),gr20 + test_spr_gr neear0,gr23 + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_limmed 0x1111,0x1111,gr20 + set_gr_limmed 0xffff,0xffff,gr8 + set_gr_immed 2,gr7 + rsth gr8,@(sp,gr7) + test_mem_limmed 0x2222,0xffff,gr22 + test_mem_limmed 0x3333,0x3333,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed 2,gr23 + nldhfi @(sp,2),fr20 + test_spr_gr neear1,gr23 + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_fr_iimmed 0x1111,0x1111,fr20 + set_gr_limmed 0xffff,0xffff,gr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + rsth gr8,@(sp,gr7) + test_mem_limmed 0xffff,0x2222,gr22 + test_mem_limmed 0x3333,0x3333,gr21 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for gr + inc_gr_immed -4,gr23 + nlduhi @(sp,-6),gr20 + test_spr_gr neear2,gr23 + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_limmed 0x1111,0x1111,gr20 + set_gr_limmed 0xffff,0xffff,gr8 + inc_gr_immed -4,sp + set_gr_immed -2,gr7 + rsth gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr22 + test_mem_limmed 0x3333,0xffff,gr21 + test_gr_limmed 0x0000,0xffff,gr20 + + ; 1 nesr active with the correct address in neear for fr + inc_gr_immed -2,gr23 + nldhfi @(sp,-4),fr20 + test_spr_gr neear3,gr23 + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_fr_iimmed 0x1111,0x1111,fr20 + set_gr_limmed 0xffff,0xffff,gr8 + set_gr_immed -4,gr7 + rsth gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr22 + test_mem_limmed 0xffff,0x3333,gr21 + test_fr_limmed 0x0000,0xffff,fr20 + + pass diff --git a/sim/testsuite/sim/frv/rsthf.cgs b/sim/testsuite/sim/frv/rsthf.cgs new file mode 100644 index 00000000000..06adb97fd00 --- /dev/null +++ b/sim/testsuite/sim/frv/rsthf.cgs @@ -0,0 +1,87 @@ +# frv testcase for rsthf $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr22 + set_mem_limmed 0x2222,0x2222,gr22 + set_gr_gr gr22,gr21 + inc_gr_immed -4,gr21 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_gr gr22,gr23 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + rsthf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0x2222,gr22 + test_mem_limmed 0x3333,0x3333,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the incorrect address in neear for gr + inc_gr_immed -2,gr23 + nlduhi @(sp,-2),gr20 + test_spr_gr neear0,gr23 + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0xffff,0xffff,fr8 + set_gr_immed 2,gr7 + rsthf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0xffff,gr22 + test_mem_limmed 0x3333,0x3333,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -2,gr23 + nldhfi @(sp,-4),fr20 + test_spr_gr neear1,gr23 + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_fr_iimmed 0xffff,0xffff,fr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + rsthf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0x2222,gr22 + test_mem_limmed 0x3333,0x3333,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for gr + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_fr_iimmed 0xffff,0xffff,fr8 + inc_gr_immed -4,sp + set_gr_immed -2,gr7 + rsthf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr22 + test_mem_limmed 0x3333,0xffff,gr21 + test_gr_limmed 0x0000,0xffff,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for fr + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_fr_iimmed 0xffff,0xffff,fr8 + set_gr_immed -4,gr7 + rsthf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr22 + test_mem_limmed 0xffff,0x3333,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x0000,0xffff,fr20 + + pass diff --git a/sim/testsuite/sim/frv/rstq.cgs b/sim/testsuite/sim/frv/rstq.cgs new file mode 100644 index 00000000000..ba066514640 --- /dev/null +++ b/sim/testsuite/sim/frv/rstq.cgs @@ -0,0 +1,297 @@ +# frv testcase for rstq $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr6 + set_mem_limmed 0x2222,0x2222,gr6 + set_gr_gr gr6,gr27 + inc_gr_immed -4,gr27 + set_mem_limmed 0x3333,0x3333,gr27 + set_gr_gr gr27,gr26 + inc_gr_immed -4,gr26 + set_mem_limmed 0x4444,0x4444,gr26 + set_gr_gr gr26,gr25 + inc_gr_immed -4,gr25 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_gr gr25,gr24 + inc_gr_immed -4,gr24 + set_mem_limmed 0x6666,0x6666,gr24 + set_gr_gr gr24,gr23 + inc_gr_immed -4,gr23 + set_mem_limmed 0x7777,0x7777,gr23 + set_gr_gr gr23,gr22 + inc_gr_immed -4,gr22 + set_mem_limmed 0x8888,0x8888,gr22 + set_gr_gr gr22,gr21 + inc_gr_immed -4,gr21 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_gr gr21,gr20 + inc_gr_immed -4,gr20 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_gr_gr gr20,gr19 + inc_gr_immed -4,gr19 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_gr_gr gr19,gr18 + inc_gr_immed -4,gr18 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_gr_gr gr18,gr17 + inc_gr_immed -4,gr17 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_gr_gr gr17,gr16 + inc_gr_immed -4,gr16 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_gr_gr gr16,gr15 + inc_gr_immed -4,gr15 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_gr_gr gr15,gr14 + inc_gr_immed -4,gr14 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_gr_gr gr14,gr13 + inc_gr_immed -4,gr13 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + inc_gr_immed -12,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + rstq gr8,@(sp,gr7) + test_mem_limmed 0xdddd,0xdddd,gr6 + test_mem_limmed 0xcccc,0xcccc,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0xeeee,0xeeee,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_gr_limmed 0x1111,0x1111,gr42 + test_gr_limmed 0x1111,0x1111,gr43 + + ; 1 nesr active with the incorrect address in neear for gr + set_gr_gr sp,gr12 + nldqi @(sp,0),gr40 + test_spr_gr neear0,gr12 + set_mem_limmed 0x2222,0x2222,gr6 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + set_gr_immed -16,gr7 + rstq gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr6 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0xdddd,0xdddd,gr24 + test_mem_limmed 0xcccc,0xcccc,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xeeee,0xeeee,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_gr_limmed 0x1111,0x1111,gr42 + test_gr_limmed 0x1111,0x1111,gr43 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -16,gr12 + nlddfi @(sp,-16),fr40 + test_spr_gr neear1,gr12 + set_mem_limmed 0x2222,0x2222,gr6 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_fr_iimmed 0x1111,0x1111,fr42 + set_fr_iimmed 0x1111,0x1111,fr43 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + rstq gr8,@(sp,gr7) + test_mem_limmed 0xdddd,0xdddd,gr6 + test_mem_limmed 0xcccc,0xcccc,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0xeeee,0xeeee,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + test_fr_limmed 0x1111,0x1111,fr42 + test_fr_limmed 0x1111,0x1111,fr43 + + ; 1 nesr active with the correct address in neear for gr + inc_gr_immed -16,gr12 + nlddi @(sp,-16),gr40 + test_spr_gr neear2,gr12 + set_mem_limmed 0x2222,0x2222,gr6 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + inc_gr_immed -16,sp + set_gr_immed 0,gr7 + rstq gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr6 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xdddd,0xdddd,gr20 + test_mem_limmed 0xcccc,0xcccc,gr19 + test_mem_limmed 0xffff,0xffff,gr18 + test_mem_limmed 0xeeee,0xeeee,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_gr_limmed 0xeeee,0xeeee,gr40 + test_gr_limmed 0xffff,0xffff,gr41 + test_gr_limmed 0xcccc,0xcccc,gr42 + test_gr_limmed 0xdddd,0xdddd,gr43 + + ; 1 nesr active with the correct address in neear for fr + inc_gr_immed -16,gr12 + nlddfi @(sp,-16),fr40 + test_spr_gr neear3,gr12 + set_mem_limmed 0x2222,0x2222,gr6 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_fr_iimmed 0x1111,0x1111,fr42 + set_fr_iimmed 0x1111,0x1111,fr43 + set_gr_immed -16,gr7 + rstq gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr6 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xdddd,0xdddd,gr16 + test_mem_limmed 0xcccc,0xcccc,gr15 + test_mem_limmed 0xffff,0xffff,gr14 + test_mem_limmed 0xeeee,0xeeee,gr13 + test_fr_limmed 0xeeee,0xeeee,fr40 + test_fr_limmed 0xffff,0xffff,fr41 + test_fr_limmed 0xcccc,0xcccc,fr42 + test_fr_limmed 0xdddd,0xdddd,fr43 + + pass diff --git a/sim/testsuite/sim/frv/rstqf.cgs b/sim/testsuite/sim/frv/rstqf.cgs new file mode 100644 index 00000000000..942e8652ffa --- /dev/null +++ b/sim/testsuite/sim/frv/rstqf.cgs @@ -0,0 +1,332 @@ +# frv testcase for rstqf $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr12 + set_mem_limmed 0x2222,0x2222,gr12 + set_gr_gr gr12,gr27 + inc_gr_immed -4,gr27 + set_mem_limmed 0x3333,0x3333,gr27 + set_gr_gr gr27,gr26 + inc_gr_immed -4,gr26 + set_mem_limmed 0x4444,0x4444,gr26 + set_gr_gr gr26,gr25 + inc_gr_immed -4,gr25 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_gr gr25,gr24 + inc_gr_immed -4,gr24 + set_mem_limmed 0x6666,0x6666,gr24 + set_gr_gr gr24,gr23 + inc_gr_immed -4,gr23 + set_mem_limmed 0x7777,0x7777,gr23 + set_gr_gr gr23,gr22 + inc_gr_immed -4,gr22 + set_mem_limmed 0x8888,0x8888,gr22 + set_gr_gr gr22,gr21 + inc_gr_immed -4,gr21 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_gr gr21,gr20 + inc_gr_immed -4,gr20 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_gr_gr gr20,gr19 + inc_gr_immed -4,gr19 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_gr_gr gr19,gr18 + inc_gr_immed -4,gr18 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_gr_gr gr18,gr17 + inc_gr_immed -4,gr17 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_gr_gr gr17,gr16 + inc_gr_immed -4,gr16 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_gr_gr gr16,gr15 + inc_gr_immed -4,gr15 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_gr_gr gr15,gr14 + inc_gr_immed -4,gr14 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_gr_gr gr14,gr13 + inc_gr_immed -4,gr13 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_fr_iimmed 0x1111,0x1111,fr42 + set_fr_iimmed 0x1111,0x1111,fr43 + inc_gr_immed -12,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_fr_iimmed 0xcccc,0xcccc,fr10 + set_fr_iimmed 0xdddd,0xdddd,fr11 + rstqf fr8,@(sp,gr7) + test_mem_limmed 0xdddd,0xdddd,gr12 + test_mem_limmed 0xcccc,0xcccc,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0xeeee,0xeeee,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_gr_limmed 0x1111,0x1111,gr42 + test_gr_limmed 0x1111,0x1111,gr43 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + test_fr_limmed 0x1111,0x1111,fr42 + test_fr_limmed 0x1111,0x1111,fr43 + + ; 1 nesr active with the incorrect address in neear for gr + set_gr_gr sp,gr10 + inc_gr_immed -32,gr10 + nldqi @(sp,-32),gr40 + test_spr_gr neear0,gr10 + set_mem_limmed 0x2222,0x2222,gr12 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_fr_iimmed 0xcccc,0xcccc,fr10 + set_fr_iimmed 0xdddd,0xdddd,fr11 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_fr_iimmed 0x1111,0x1111,fr42 + set_fr_iimmed 0x1111,0x1111,fr43 + set_gr_immed -16,gr7 + rstqf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr12 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0xdddd,0xdddd,gr24 + test_mem_limmed 0xcccc,0xcccc,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xeeee,0xeeee,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_gr_limmed 0x1111,0x1111,gr42 + test_gr_limmed 0x1111,0x1111,gr43 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + test_fr_limmed 0x1111,0x1111,fr42 + test_fr_limmed 0x1111,0x1111,fr43 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -16,gr10 + nlddfi @(sp,-48),fr40 + test_spr_gr neear1,gr10 + set_mem_limmed 0x2222,0x2222,gr12 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_fr_iimmed 0xcccc,0xcccc,fr10 + set_fr_iimmed 0xdddd,0xdddd,fr11 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_fr_iimmed 0x1111,0x1111,fr42 + set_fr_iimmed 0x1111,0x1111,fr43 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + rstqf fr8,@(sp,gr7) + test_mem_limmed 0xdddd,0xdddd,gr12 + test_mem_limmed 0xcccc,0xcccc,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0xeeee,0xeeee,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_gr_limmed 0x1111,0x1111,gr42 + test_gr_limmed 0x1111,0x1111,gr43 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + test_fr_limmed 0x1111,0x1111,fr42 + test_fr_limmed 0x1111,0x1111,fr43 + + ; 1 nesr active with the correct address in neear for gr + set_mem_limmed 0x2222,0x2222,gr12 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_fr_iimmed 0xcccc,0xcccc,fr10 + set_fr_iimmed 0xdddd,0xdddd,fr11 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_fr_iimmed 0x1111,0x1111,fr42 + set_fr_iimmed 0x1111,0x1111,fr43 + inc_gr_immed -16,sp + set_gr_immed 0,gr7 + rstqf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr12 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xdddd,0xdddd,gr20 + test_mem_limmed 0xcccc,0xcccc,gr19 + test_mem_limmed 0xffff,0xffff,gr18 + test_mem_limmed 0xeeee,0xeeee,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_gr_limmed 0xeeee,0xeeee,gr40 + test_gr_limmed 0xffff,0xffff,gr41 + test_gr_limmed 0xcccc,0xcccc,gr42 + test_gr_limmed 0xdddd,0xdddd,gr43 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + test_fr_limmed 0x1111,0x1111,fr42 + test_fr_limmed 0x1111,0x1111,fr43 + + ; 1 nesr active with the correct address in neear for fr + set_mem_limmed 0x2222,0x2222,gr12 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_fr_iimmed 0xcccc,0xcccc,fr10 + set_fr_iimmed 0xdddd,0xdddd,fr11 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_fr_iimmed 0x1111,0x1111,fr42 + set_fr_iimmed 0x1111,0x1111,fr43 + set_gr_immed -16,gr7 + rstqf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr12 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xdddd,0xdddd,gr16 + test_mem_limmed 0xcccc,0xcccc,gr15 + test_mem_limmed 0xffff,0xffff,gr14 + test_mem_limmed 0xeeee,0xeeee,gr13 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_gr_limmed 0x1111,0x1111,gr42 + test_gr_limmed 0x1111,0x1111,gr43 + test_fr_limmed 0xeeee,0xeeee,fr40 + test_fr_limmed 0xffff,0xffff,fr41 + test_fr_limmed 0xcccc,0xcccc,fr42 + test_fr_limmed 0xdddd,0xdddd,fr43 + + pass diff --git a/sim/testsuite/sim/frv/scan.cgs b/sim/testsuite/sim/frv/scan.cgs new file mode 100644 index 00000000000..d19107df12e --- /dev/null +++ b/sim/testsuite/sim/frv/scan.cgs @@ -0,0 +1,73 @@ +# frv testcase for scan $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global scan +scan: + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + scan gr7,gr8,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + scan gr7,gr8,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + scan gr7,gr8,gr9 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + scan gr7,gr8,gr9 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + scan gr7,gr8,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + scan gr7,gr8,gr9 + test_gr_immed 2,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + scan gr7,gr8,gr9 + test_gr_immed 16,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + scan gr7,gr8,gr9 + test_gr_immed 31,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + scan gr7,gr8,gr9 + test_gr_immed 7,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/sim/frv/scani.cgs b/sim/testsuite/sim/frv/scani.cgs new file mode 100644 index 00000000000..97175dc1051 --- /dev/null +++ b/sim/testsuite/sim/frv/scani.cgs @@ -0,0 +1,55 @@ +# frv testcase for scani $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global scani +scani: + set_gr_limmed 0xffff,0xfeaa,gr7 + scani gr7,0x2aa,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0xffff,0xfeaa,gr7 + + set_gr_limmed 0xffff,0xfeaa,gr7 + scani gr7,0x2ab,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0xffff,0xfeaa,gr7 + + set_gr_limmed 0x0000,0x0155,gr7 + scani gr7,0x2aa,gr9 + test_gr_immed 63,gr9 + test_gr_limmed 0x0000,0x0155,gr7 + + set_gr_limmed 0x0000,0x0155,gr7 + scani gr7,0x2ab,gr9 + test_gr_immed 63,gr9 + test_gr_limmed 0x0000,0x0155,gr7 + + set_gr_limmed 0x7fff,0xffff,gr7 + scani gr7,-1,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0x7fff,0xffff,gr7 + + set_gr_limmed 0xbfff,0xffff,gr7 + scani gr7,-1,gr9 + test_gr_immed 1,gr9 + test_gr_limmed 0xbfff,0xffff,gr7 + + set_gr_limmed 0xfffe,0xffff,gr7 + scani gr7,-1,gr9 + test_gr_immed 15,gr9 + test_gr_limmed 0xfffe,0xffff,gr7 + + set_gr_limmed 0xffff,0xfffd,gr7 + scani gr7,-1,gr9 + test_gr_immed 30,gr9 + test_gr_limmed 0xffff,0xfffd,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + scani gr7,-2048,gr9 + test_gr_immed 2,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + + pass diff --git a/sim/testsuite/sim/frv/sdiv.cgs b/sim/testsuite/sim/frv/sdiv.cgs new file mode 100644 index 00000000000..d193b2318c1 --- /dev/null +++ b/sim/testsuite/sim/frv/sdiv.cgs @@ -0,0 +1,75 @@ +# frv testcase for sdiv $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sdiv +sdiv: + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + sdiv gr1,gr3,gr2 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + sdiv gr1,gr3,gr2 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + sdiv gr1,gr3,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_addr e1,gr17 + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e1: sdiv gr1,gr3,gr2 ; overflow + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2; gr2 updated + + ; divide by zero + set_spr_addr ok2,lr + set_gr_addr e2,gr17 + set_gr_immed 0xdeadbeef,gr2 +e2: sdiv gr1,gr0,gr2 ; divide by zero + test_gr_immed 2,gr15 ; handler called + test_gr_immed 0xdeadbeef,gr2 ; gr2 not updated. + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail + +ok2: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/sdivi.cgs b/sim/testsuite/sim/frv/sdivi.cgs new file mode 100644 index 00000000000..eb781e720a4 --- /dev/null +++ b/sim/testsuite/sim/frv/sdivi.cgs @@ -0,0 +1,74 @@ +# frv testcase for sdivi $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sdivi +sdivi: + ; simple division 12 / 3 + set_gr_immed 12,gr1 + sdivi gr1,3,gr2 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0xfedc,0xba98,gr1 + sdivi gr1,0x7ff,gr2 + test_gr_limmed 0xffff,0xdb93,gr2 + + ; Random negative example + set_gr_limmed 0xfedc,0xba98,gr1 + sdivi gr1,-2048,gr2 + test_gr_immed 0x2468,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_limmed 0x8000,0x0000,gr1 + sdivi gr1,-1,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_addr e1,gr17 + set_gr_limmed 0x8000,0x0000,gr1 +e1: sdivi gr1,-1,gr2 + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; divide by zero + set_spr_addr ok2,lr + set_gr_addr e2,gr17 +e2: sdivi gr1,0,gr2 ; divide by zero + test_gr_immed 2,gr15 + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail + +ok2: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/sethi.cgs b/sim/testsuite/sim/frv/sethi.cgs new file mode 100644 index 00000000000..00a3bdd6137 --- /dev/null +++ b/sim/testsuite/sim/frv/sethi.cgs @@ -0,0 +1,18 @@ +# frv testcase for sethi $s16,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sethi +sethi: + set_gr_immed 0,gr1 + sethi 0,gr1 + test_gr_immed 0,gr1 + sethi 1,gr1 + test_gr_immed 0x00010000,gr1 + sethi 0x7fff,gr1 + test_gr_immed 0x7fff0000,gr1 + + pass diff --git a/sim/testsuite/sim/frv/sethilo.pcgs b/sim/testsuite/sim/frv/sethilo.pcgs new file mode 100644 index 00000000000..c8e7b602ce5 --- /dev/null +++ b/sim/testsuite/sim/frv/sethilo.pcgs @@ -0,0 +1,18 @@ +# frv parallel testcase for sethi $s16,$GRk and setlo $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sethilo +sethilo: + sethi.p 0xdead,gr7 + setlo 0xbeef,gr7 + test_gr_immed 0xdeadbeef,gr7 + + setlo.p 0xdead,gr7 + sethi 0xbeef,gr7 + test_gr_immed 0xbeefdead,gr7 + + pass diff --git a/sim/testsuite/sim/frv/setlo.cgs b/sim/testsuite/sim/frv/setlo.cgs new file mode 100644 index 00000000000..6bdac2eba2e --- /dev/null +++ b/sim/testsuite/sim/frv/setlo.cgs @@ -0,0 +1,18 @@ +# frv testcase for setlo $s16,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_gr_immed 0,gr1 + setlo 0,gr1 + test_gr_immed 0,gr1 + setlo 1,gr1 + test_gr_immed 1,gr1 + setlo 0x7fff,gr1 + test_gr_immed 0x7fff,gr1 + + pass diff --git a/sim/testsuite/sim/frv/setlos.cgs b/sim/testsuite/sim/frv/setlos.cgs new file mode 100644 index 00000000000..8979d13a7e1 --- /dev/null +++ b/sim/testsuite/sim/frv/setlos.cgs @@ -0,0 +1,21 @@ +# frv testcase for setlos $s16,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global setlos +setlos: + setlos 0,gr1 + test_gr_immed 0,gr1 + setlos 1,gr1 + test_gr_immed 1,gr1 + setlos 0x7fff,gr1 + test_gr_immed 0x7fff,gr1 + setlos -1,gr1 + test_gr_immed -1,gr1 + setlos -32768,gr1 + test_gr_immed -32768,gr1 + + pass diff --git a/sim/testsuite/sim/frv/sll.cgs b/sim/testsuite/sim/frv/sll.cgs new file mode 100644 index 00000000000..9103cf6874a --- /dev/null +++ b/sim/testsuite/sim/frv/sll.cgs @@ -0,0 +1,38 @@ +# frv testcase for sll $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sll +sll: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + sll gr8,gr7,gr8 + test_icc 1 1 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sll gr8,gr7,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sll gr8,gr7,gr8 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + sll gr8,gr7,gr8 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/sllcc.cgs b/sim/testsuite/sim/frv/sllcc.cgs new file mode 100644 index 00000000000..533b5045399 --- /dev/null +++ b/sim/testsuite/sim/frv/sllcc.cgs @@ -0,0 +1,38 @@ +# frv testcase for sllcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global sllcc +sllcc: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sllcc gr8,gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sllcc gr8,gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sllcc gr8,gr7,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + sllcc gr8,gr7,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/slli.cgs b/sim/testsuite/sim/frv/slli.cgs new file mode 100644 index 00000000000..80c25c0043a --- /dev/null +++ b/sim/testsuite/sim/frv/slli.cgs @@ -0,0 +1,34 @@ +# frv testcase for slli $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global slli +slli: + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + slli gr8,0x7e0,gr8 ; Shift by 0 + test_icc 1 1 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + slli gr8,-31,gr8 ; Shift by 1 + test_icc 1 1 1 1 icc0 + test_gr_immed 4,gr8 + + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + slli gr8,31,gr8 ; Shift by 31 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + slli gr8,31,gr8 ; clear register + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/sllicc.cgs b/sim/testsuite/sim/frv/sllicc.cgs new file mode 100644 index 00000000000..b8e4c7da788 --- /dev/null +++ b/sim/testsuite/sim/frv/sllicc.cgs @@ -0,0 +1,34 @@ +# frv testcase for sllicc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global sllicc +sllicc: + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sllicc gr8,0x1e0,gr8,icc0 ; Shift by 0 + test_icc 0 0 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sllicc gr8,-31,gr8,icc0 ; Shift by 1 + test_icc 0 0 0 1 icc0 + test_gr_immed 4,gr8 + + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sllicc gr8,31,gr8,icc0 ; Shift by 31 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 2,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + sllicc gr8,31,gr8,icc0 ; clear register + test_icc 0 1 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/smul.cgs b/sim/testsuite/sim/frv/smul.cgs new file mode 100644 index 00000000000..ed065a93d14 --- /dev/null +++ b/sim/testsuite/sim/frv/smul.cgs @@ -0,0 +1,182 @@ +# frv testcase for smul $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global smul +smul: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + smul gr7,gr8,gr8 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + smul gr7,gr8,gr8 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + smul gr7,gr8,gr8 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + pass diff --git a/sim/testsuite/sim/frv/smulcc.cgs b/sim/testsuite/sim/frv/smulcc.cgs new file mode 100644 index 00000000000..76a009ec22f --- /dev/null +++ b/sim/testsuite/sim/frv/smulcc.cgs @@ -0,0 +1,238 @@ +# frv testcase for smulcc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global smulcc +smulcc: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x1,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x2,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0xb,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x8,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0xd,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0xe,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0xf,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0xc,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x5,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x6,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x7,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x4,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0x9,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xa,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x4,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x5,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x6,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x7,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xc,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xd,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0xe,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0xc,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0xd,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xe,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xf,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + pass diff --git a/sim/testsuite/sim/frv/smuli.cgs b/sim/testsuite/sim/frv/smuli.cgs new file mode 100644 index 00000000000..19a695cf56b --- /dev/null +++ b/sim/testsuite/sim/frv/smuli.cgs @@ -0,0 +1,210 @@ +# frv testcase for smuli $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global smuli +smuli: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0x0,0 + smuli gr7,2,gr8 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0x1,0 + smuli gr7,2,gr8 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_icc 0x2,0 + smuli gr7,1,gr8 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0x3,0 + smuli gr7,2,gr8 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_icc 0x4,0 + smuli gr7,0,gr8 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_icc 0x5,0 + smuli gr7,2,gr8 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x6,0 + smuli gr7,2,gr8 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_icc 0x7,0 + smuli gr7,4,gr8 + test_icc 0 1 1 1 icc0 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_icc 0x8,0 + smuli gr7,0x7ff,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x3ff,gr8 + test_gr_limmed 0x7fff,0xf801,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_icc 0x9,0 + smuli gr7,2,gr8 + test_icc 1 0 0 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0xa,0 + smuli gr7,-2,gr8 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0xb,0 + smuli gr7,-2,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_icc 0xc,0 + smuli gr7,1,gr8 + test_icc 1 1 0 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0xd,0 + smuli gr7,-2,gr8 + test_icc 1 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_icc 0xe,0 + smuli gr7,0,gr8 + test_icc 1 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_icc 0xf,0 + smuli gr7,-2,gr8 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x0,0 + smuli gr7,-2,gr8 + test_icc 0 0 0 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_icc 0x1,0 + smuli gr7,-2,gr8 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_icc 0x2,0 + smuli gr7,-4,gr8 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_icc 0x3,0 + smuli gr7,-2048,gr8 + test_icc 0 0 1 1 icc0 + test_gr_limmed 0xffff,0xfc00,gr8 + test_gr_limmed 0x0000,0x0800,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_icc 0x4,0 + smuli gr7,-2,gr8 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_icc 0x5,0 + smuli gr7,-2,gr8 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_icc 0x6,0 + smuli gr7,-1,gr8 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_icc 0x7,0 + smuli gr7,-2,gr8 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_icc 0x8,0 + smuli gr7,-2,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_icc 0x9,0 + smuli gr7,-4,gr8 + test_icc 1 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_icc 0xa,0 + smuli gr7,-2048,gr8 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x0000,0x03ff,gr8 + test_gr_limmed 0xffff,0xf800,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_icc 0xb,0 + smuli gr7,-2048,gr8 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0x0000,0x0400,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + pass diff --git a/sim/testsuite/sim/frv/smulicc.cgs b/sim/testsuite/sim/frv/smulicc.cgs new file mode 100644 index 00000000000..e9aa889c249 --- /dev/null +++ b/sim/testsuite/sim/frv/smulicc.cgs @@ -0,0 +1,210 @@ +# frv testcase for smulicc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global smulicc +smulicc: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0x0,0 + smulicc gr7,2,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0x1,0 + smulicc gr7,2,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_icc 0x2,0 + smulicc gr7,1,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0x3,0 + smulicc gr7,2,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_icc 0x4,0 + smulicc gr7,0,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_icc 0x5,0 + smulicc gr7,2,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x6,0 + smulicc gr7,2,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_icc 0x7,0 + smulicc gr7,4,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_icc 0x8,0 + smulicc gr7,0x1ff,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0xff,gr8 + test_gr_limmed 0x7fff,0xfe01,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_icc 0x9,0 + smulicc gr7,2,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0xa,0 + smulicc gr7,-2,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0xb,0 + smulicc gr7,-2,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_icc 0xc,0 + smulicc gr7,1,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0xd,0 + smulicc gr7,-2,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_icc 0xe,0 + smulicc gr7,0,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_icc 0xf,0 + smulicc gr7,-2,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x0,0 + smulicc gr7,-2,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_icc 0x1,0 + smulicc gr7,-2,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_icc 0x2,0 + smulicc gr7,-4,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_icc 0x3,0 + smulicc gr7,-512,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xff00,gr8 + test_gr_limmed 0x0000,0x0200,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_icc 0x4,0 + smulicc gr7,-2,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_icc 0x5,0 + smulicc gr7,-2,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_icc 0x6,0 + smulicc gr7,-1,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_icc 0x7,0 + smulicc gr7,-2,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_icc 0x8,0 + smulicc gr7,-2,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_icc 0x9,0 + smulicc gr7,-4,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_icc 0xa,0 + smulicc gr7,-512,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x0000,0x00ff,gr8 + test_gr_limmed 0xffff,0xfe00,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_icc 0xb,0 + smulicc gr7,-512,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_limmed 0x0000,0x0100,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + pass diff --git a/sim/testsuite/sim/frv/sra.cgs b/sim/testsuite/sim/frv/sra.cgs new file mode 100644 index 00000000000..0f0c8644d03 --- /dev/null +++ b/sim/testsuite/sim/frv/sra.cgs @@ -0,0 +1,38 @@ +# frv testcase for sra $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sra +sra: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + sra gr8,gr7,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sra gr8,gr7,gr8 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sra gr8,gr7,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + sra gr8,gr7,gr8 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/sracc.cgs b/sim/testsuite/sim/frv/sracc.cgs new file mode 100644 index 00000000000..14f4a8bf49c --- /dev/null +++ b/sim/testsuite/sim/frv/sracc.cgs @@ -0,0 +1,38 @@ +# frv testcase for sracc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global sracc +sracc: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + sracc gr8,gr7,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sracc gr8,gr7,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sracc gr8,gr7,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + sracc gr8,gr7,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/srai.cgs b/sim/testsuite/sim/frv/srai.cgs new file mode 100644 index 00000000000..02b9654f587 --- /dev/null +++ b/sim/testsuite/sim/frv/srai.cgs @@ -0,0 +1,34 @@ +# frv testcase for srai $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global srai +srai: + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + srai gr8,0x7e0,gr8 ; Shift by 0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srai gr8,-31,gr8 ; Shift by 1 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srai gr8,31,gr8 ; Shift by 31 + test_icc 1 1 1 1 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + srai gr8,31,gr8 ; clear register + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/sraicc.cgs b/sim/testsuite/sim/frv/sraicc.cgs new file mode 100644 index 00000000000..5dbd1e600c6 --- /dev/null +++ b/sim/testsuite/sim/frv/sraicc.cgs @@ -0,0 +1,34 @@ +# frv testcase for sraicc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global sraicc +sraicc: + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + sraicc gr8,0x1e0,gr8,icc0 ; Shift by 0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sraicc gr8,-31,gr8,icc0 ; Shift by 1 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sraicc gr8,31,gr8,icc0 ; Shift by 31 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + sraicc gr8,31,gr8,icc0 ; clear register + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/srl.cgs b/sim/testsuite/sim/frv/srl.cgs new file mode 100644 index 00000000000..045e75edba6 --- /dev/null +++ b/sim/testsuite/sim/frv/srl.cgs @@ -0,0 +1,38 @@ +# frv testcase for srl $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global srl +srl: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + srl gr8,gr7,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srl gr8,gr7,gr8 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srl gr8,gr7,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + srl gr8,gr7,gr8 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/srlcc.cgs b/sim/testsuite/sim/frv/srlcc.cgs new file mode 100644 index 00000000000..1450a4b9ed9 --- /dev/null +++ b/sim/testsuite/sim/frv/srlcc.cgs @@ -0,0 +1,38 @@ +# frv testcase for srlcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global srlcc +srlcc: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + srlcc gr8,gr7,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srlcc gr8,gr7,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srlcc gr8,gr7,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + srlcc gr8,gr7,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/srli.cgs b/sim/testsuite/sim/frv/srli.cgs new file mode 100644 index 00000000000..72207d3a3e3 --- /dev/null +++ b/sim/testsuite/sim/frv/srli.cgs @@ -0,0 +1,34 @@ +# frv testcase for srli $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global srli +srli: + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + srli gr8,0x7e0,gr8 ; Shift by 0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srli gr8,-31,gr8 ; Shift by 1 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srli gr8,31,gr8 ; Shift by 31 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + srli gr8,31,gr8 ; clear register + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/srlicc.cgs b/sim/testsuite/sim/frv/srlicc.cgs new file mode 100644 index 00000000000..d232802eb57 --- /dev/null +++ b/sim/testsuite/sim/frv/srlicc.cgs @@ -0,0 +1,34 @@ +# frv testcase for srlicc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global srlicc +srlicc: + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + srlicc gr8,0x1e0,gr8,icc0 ; Shift by 0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srlicc gr8,-31,gr8,icc0 ; Shift by 1 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srlicc gr8,31,gr8,icc0 ; Shift by 31 + test_icc 0 0 1 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + srlicc gr8,31,gr8,icc0 ; clear register + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/st.cgs b/sim/testsuite/sim/frv/st.cgs new file mode 100644 index 00000000000..557713c0594 --- /dev/null +++ b/sim/testsuite/sim/frv/st.cgs @@ -0,0 +1,16 @@ +# frv testcase for st $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + st gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + + pass diff --git a/sim/testsuite/sim/frv/stb.cgs b/sim/testsuite/sim/frv/stb.cgs new file mode 100644 index 00000000000..15fa1e65398 --- /dev/null +++ b/sim/testsuite/sim/frv/stb.cgs @@ -0,0 +1,16 @@ +# frv testcase for stb $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + stb gr8,@(sp,gr7) + test_mem_limmed 0xffad,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stbf.cgs b/sim/testsuite/sim/frv/stbf.cgs new file mode 100644 index 00000000000..741327d8a11 --- /dev/null +++ b/sim/testsuite/sim/frv/stbf.cgs @@ -0,0 +1,16 @@ +# frv testcase for stbf $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stbf +stbf: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + stbf fr8,@(sp,gr7) + test_mem_limmed 0xffad,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stbfi.cgs b/sim/testsuite/sim/frv/stbfi.cgs new file mode 100644 index 00000000000..cfea70867f3 --- /dev/null +++ b/sim/testsuite/sim/frv/stbfi.cgs @@ -0,0 +1,24 @@ +# frv testcase for stbfi $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stbfi +stbfi: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xffff,0xffff,fr8 + stbfi fr8,@(sp,0) + test_mem_limmed 0xffad,0xbeef,sp + + inc_gr_immed 0x801,sp ; 2049 + stbfi fr8,@(sp,-2048) + test_mem_limmed 0xffff,0xbeef,gr20 + + inc_gr_immed -4094,sp + stbfi fr8,@(sp,0x7ff) + test_mem_limmed 0xffff,0xffef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/stbfu.cgs b/sim/testsuite/sim/frv/stbfu.cgs new file mode 100644 index 00000000000..01bbb99ca9e --- /dev/null +++ b/sim/testsuite/sim/frv/stbfu.cgs @@ -0,0 +1,19 @@ +# frv testcase for stbfu $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stbfu +stbfu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + stbfu fr8,@(sp,gr7) + test_mem_limmed 0xffad,0xbeef,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/sim/frv/stbi.cgs b/sim/testsuite/sim/frv/stbi.cgs new file mode 100644 index 00000000000..f23efc9155a --- /dev/null +++ b/sim/testsuite/sim/frv/stbi.cgs @@ -0,0 +1,24 @@ +# frv testcase for stbi $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stbi +stbi: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xffff,0xffff,gr8 + stbi gr8,@(sp,0) + test_mem_limmed 0xffad,0xbeef,sp + + inc_gr_immed 0x801,sp ; 2049 + stbi gr8,@(sp,-2048) + test_mem_limmed 0xffff,0xbeef,gr20 + + inc_gr_immed -4094,sp + stbi gr8,@(sp,0x7ff) + test_mem_limmed 0xffff,0xffef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/stbu.cgs b/sim/testsuite/sim/frv/stbu.cgs new file mode 100644 index 00000000000..e56ad1137d1 --- /dev/null +++ b/sim/testsuite/sim/frv/stbu.cgs @@ -0,0 +1,19 @@ +# frv testcase for stbu $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stbu +stbu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + stbu gr8,@(sp,gr7) + test_mem_limmed 0xffad,0xbeef,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/sim/frv/stc.cgs b/sim/testsuite/sim/frv/stc.cgs new file mode 100644 index 00000000000..581297cef9d --- /dev/null +++ b/sim/testsuite/sim/frv/stc.cgs @@ -0,0 +1,17 @@ +# frv testcase for stc $CPRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stc +stc: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xffff,0xffff,cpr8 + stc cpr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + + pass diff --git a/sim/testsuite/sim/frv/stcu.cgs b/sim/testsuite/sim/frv/stcu.cgs new file mode 100644 index 00000000000..eb9e6c5efa1 --- /dev/null +++ b/sim/testsuite/sim/frv/stcu.cgs @@ -0,0 +1,33 @@ +# frv testcase for stcu $CPRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stcu +stcu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xffff,0xffff,cpr8 + stcu cpr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + test_gr_gr sp,gr20 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_cpr_limmed 0x1234,0x5678,cpr8 + stcu cpr8,@(sp,gr7) + test_mem_limmed 0x1234,0x5678,sp + test_gr_gr sp,gr20 + + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + set_cpr_limmed 0x9abc,0xdef0,cpr8 + stcu cpr8,@(sp,gr7) + test_mem_limmed 0x9abc,0xdef0,sp + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/std.cgs b/sim/testsuite/sim/frv/std.cgs new file mode 100644 index 00000000000..8a2ed12e99f --- /dev/null +++ b/sim/testsuite/sim/frv/std.cgs @@ -0,0 +1,32 @@ +# frv testcase for std $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + std gr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr3 ; sp is gr1 + set_gr_limmed 0xbeef,0xdead,gr0 + set_gr_limmed 0xdead,0xbeef,gr1 + std gr0,@(gr3,gr7) + test_mem_immed 0,gr3 + inc_gr_immed 4,gr3 + test_mem_immed 0,gr3 + + pass diff --git a/sim/testsuite/sim/frv/std.pcgs b/sim/testsuite/sim/frv/std.pcgs new file mode 100644 index 00000000000..d518b8b9746 --- /dev/null +++ b/sim/testsuite/sim/frv/std.pcgs @@ -0,0 +1,37 @@ +# frv parallel testcase for std $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + std gr8,@(sp,gr7) ; non parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + std.p gr8,@(sp,gr0) ; parallel + setlos 0,gr8 + ld @(sp,gr0),gr10 + ld @(sp,gr7),gr11 + test_mem_limmed 0xbeef,0xdead,sp ; memory is set + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + test_gr_immed 0xbeefdead,gr10 ; regs were pre-loaded + test_gr_immed 0xdeadbeef,gr11 ; not this one + + pass diff --git a/sim/testsuite/sim/frv/stdc.cgs b/sim/testsuite/sim/frv/stdc.cgs new file mode 100644 index 00000000000..bdff0ac81c9 --- /dev/null +++ b/sim/testsuite/sim/frv/stdc.cgs @@ -0,0 +1,21 @@ +# frv testcase for stdc $CPk,@($GRi,$GRj) +# mach: frv + + .include "testutils.inc" + + start + + .global stdc +stdc: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + stdc cpr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stdc.pcgs b/sim/testsuite/sim/frv/stdc.pcgs new file mode 100644 index 00000000000..46c49250566 --- /dev/null +++ b/sim/testsuite/sim/frv/stdc.pcgs @@ -0,0 +1,38 @@ +# frv parallel testcase for stdc $CPk,@($GRi,$GRj) +# mach: frv + + .include "testutils.inc" + + start + + .global stdc +stdc: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + stdc cpr8,@(sp,gr7) ; non parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 4,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + stdc.p cpr8,@(sp,gr0) ; parallel + addi sp,4,sp + subi sp,4,sp + ldc @(sp,gr0),cpr10 + ldc @(sp,gr7),cpr11 + test_mem_limmed 0xbeef,0xdead,sp ; memory is set + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + + pass diff --git a/sim/testsuite/sim/frv/stdcu.cgs b/sim/testsuite/sim/frv/stdcu.cgs new file mode 100644 index 00000000000..bbae5fff096 --- /dev/null +++ b/sim/testsuite/sim/frv/stdcu.cgs @@ -0,0 +1,44 @@ +# frv testcase for stdcu $CPk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stdcu +stdcu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + stdcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + inc_gr_immed -12,sp + set_gr_immed 8,gr7 + set_cpr_limmed 0x1234,0x5678,cpr8 + set_cpr_limmed 0x9abc,0xdef0,cpr9 + stdcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0x1234,0x5678,sp + inc_gr_immed 4,sp + test_mem_limmed 0x9abc,0xdef0,sp + + inc_gr_immed 4,sp + set_gr_immed -8,gr7 + set_cpr_limmed 0xfedc,0xba98,cpr8 + set_cpr_limmed 0x7654,0x3210,cpr9 + stdcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xfedc,0xba98,sp + inc_gr_immed 4,sp + test_mem_limmed 0x7654,0x3210,sp + + pass diff --git a/sim/testsuite/sim/frv/stdf.cgs b/sim/testsuite/sim/frv/stdf.cgs new file mode 100644 index 00000000000..82c1461d97a --- /dev/null +++ b/sim/testsuite/sim/frv/stdf.cgs @@ -0,0 +1,21 @@ +# frv testcase for stdf $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stdf +stdf: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + stdf fr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stdf.pcgs b/sim/testsuite/sim/frv/stdf.pcgs new file mode 100644 index 00000000000..8c7ddd81261 --- /dev/null +++ b/sim/testsuite/sim/frv/stdf.pcgs @@ -0,0 +1,37 @@ +# frv parallel testcase for stdf $GRk,@($GRi,$GRj) +# mach: fr500 frv + + .include "testutils.inc" + + start + + .global stdf +stdf: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + stdf fr8,@(sp,gr7) ; non parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + stdf.p fr8,@(sp,gr0) ; parallel + fnegs fr8,fr8 + ldf @(sp,gr0),fr10 + ldf @(sp,gr7),fr11 ; memory is set + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + test_fr_iimmed 0xbeefdead,fr10 ; regs were pre-loaded + test_fr_iimmed 0xdeadbeef,fr11 ; not this one + + pass diff --git a/sim/testsuite/sim/frv/stdfi.cgs b/sim/testsuite/sim/frv/stdfi.cgs new file mode 100644 index 00000000000..fea9b5171dd --- /dev/null +++ b/sim/testsuite/sim/frv/stdfi.cgs @@ -0,0 +1,56 @@ +# frv testcase for stdfi $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stdfi +stdfi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr22 + inc_gr_immed -4,sp + set_mem_limmed 0x8765,0x4321,sp + set_gr_gr sp,gr23 + inc_gr_immed -4,sp + set_mem_limmed 0xfedc,0xba98,sp + set_gr_gr sp,gr24 + inc_gr_immed -4,sp + set_mem_limmed 0x89ab,0xcdef,sp + set_gr_gr sp,gr25 + set_fr_iimmed 0xffff,0xffff,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + + stdfi fr8,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0x8765,0x4321,gr23 + test_mem_limmed 0x1234,0x5678,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x808,sp ; 2056 + stdfi fr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xffff,0xffff,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4080,sp + stdfi fr8,@(sp,0x7f8) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xffff,0xffff,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xffff,gr20 + + pass diff --git a/sim/testsuite/sim/frv/stdfu.cgs b/sim/testsuite/sim/frv/stdfu.cgs new file mode 100644 index 00000000000..439cfa0a9b4 --- /dev/null +++ b/sim/testsuite/sim/frv/stdfu.cgs @@ -0,0 +1,24 @@ +# frv testcase for stdfu $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stdfu +stdfu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + stdfu fr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stdi.cgs b/sim/testsuite/sim/frv/stdi.cgs new file mode 100644 index 00000000000..e1a783d71aa --- /dev/null +++ b/sim/testsuite/sim/frv/stdi.cgs @@ -0,0 +1,56 @@ +# frv testcase for stdi $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stdi +stdi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr22 + inc_gr_immed -4,sp + set_mem_limmed 0x8765,0x4321,sp + set_gr_gr sp,gr23 + inc_gr_immed -4,sp + set_mem_limmed 0xfedc,0xba98,sp + set_gr_gr sp,gr24 + inc_gr_immed -4,sp + set_mem_limmed 0x89ab,0xcdef,sp + set_gr_gr sp,gr25 + set_gr_limmed 0xffff,0xffff,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + + stdi gr8,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0x8765,0x4321,gr23 + test_mem_limmed 0x1234,0x5678,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x808,sp ; 2056 + stdi gr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xffff,0xffff,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4080,sp + stdi gr8,@(sp,0x7f8) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xffff,0xffff,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xffff,gr20 + + pass diff --git a/sim/testsuite/sim/frv/stdu.cgs b/sim/testsuite/sim/frv/stdu.cgs new file mode 100644 index 00000000000..b5f122f5ef7 --- /dev/null +++ b/sim/testsuite/sim/frv/stdu.cgs @@ -0,0 +1,24 @@ +# frv testcase for stdu $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stdu +stdu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + stdu gr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stf.cgs b/sim/testsuite/sim/frv/stf.cgs new file mode 100644 index 00000000000..5ebc060bef2 --- /dev/null +++ b/sim/testsuite/sim/frv/stf.cgs @@ -0,0 +1,16 @@ +# frv testcase for stf $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stf +stf: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + stf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + + pass diff --git a/sim/testsuite/sim/frv/stfi.cgs b/sim/testsuite/sim/frv/stfi.cgs new file mode 100644 index 00000000000..cfce1fdfe57 --- /dev/null +++ b/sim/testsuite/sim/frv/stfi.cgs @@ -0,0 +1,37 @@ +# frv testcase for stfi $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stfi +stfi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr22 + set_fr_iimmed 0xffff,0xffff,fr8 + + stfi fr8,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x804,sp ; 2052 + stfi fr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4088,sp + stfi fr8,@(sp,0x7fc) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xffff,gr20 + + pass diff --git a/sim/testsuite/sim/frv/stfu.cgs b/sim/testsuite/sim/frv/stfu.cgs new file mode 100644 index 00000000000..e47e61dc56c --- /dev/null +++ b/sim/testsuite/sim/frv/stfu.cgs @@ -0,0 +1,19 @@ +# frv testcase for stfu $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stfu +stfu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + stfu fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/sim/frv/sth.cgs b/sim/testsuite/sim/frv/sth.cgs new file mode 100644 index 00000000000..c11ae407cd0 --- /dev/null +++ b/sim/testsuite/sim/frv/sth.cgs @@ -0,0 +1,16 @@ +# frv testcase for sth $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + sth gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/sthf.cgs b/sim/testsuite/sim/frv/sthf.cgs new file mode 100644 index 00000000000..7310e4ee8c1 --- /dev/null +++ b/sim/testsuite/sim/frv/sthf.cgs @@ -0,0 +1,16 @@ +# frv testcase for sthf $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sthf +sthf: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + sthf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/sthfi.cgs b/sim/testsuite/sim/frv/sthfi.cgs new file mode 100644 index 00000000000..ae9da976fd2 --- /dev/null +++ b/sim/testsuite/sim/frv/sthfi.cgs @@ -0,0 +1,31 @@ +# frv testcase for sthfi $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sthfi +sthfi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + set_fr_iimmed 0xffff,0xffff,fr8 + + sthfi fr8,@(sp,0) + test_mem_limmed 0xffff,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x802,sp ; 2050 + sthfi fr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4092,sp + sthfi fr8,@(sp,0x7fe) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xbeef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/sthfu.cgs b/sim/testsuite/sim/frv/sthfu.cgs new file mode 100644 index 00000000000..df472e73525 --- /dev/null +++ b/sim/testsuite/sim/frv/sthfu.cgs @@ -0,0 +1,19 @@ +# frv testcase for sthfu $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sthfu +sthfu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + sthfu fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xbeef,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/sim/frv/sthi.cgs b/sim/testsuite/sim/frv/sthi.cgs new file mode 100644 index 00000000000..93636e90956 --- /dev/null +++ b/sim/testsuite/sim/frv/sthi.cgs @@ -0,0 +1,31 @@ +# frv testcase for sthi $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sthi +sthi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + set_gr_limmed 0xffff,0xffff,gr8 + + sthi gr8,@(sp,0) + test_mem_limmed 0xffff,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x802,sp ; 2050 + sthi gr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4092,sp + sthi gr8,@(sp,0x7fe) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xbeef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/sthu.cgs b/sim/testsuite/sim/frv/sthu.cgs new file mode 100644 index 00000000000..ab35b30d396 --- /dev/null +++ b/sim/testsuite/sim/frv/sthu.cgs @@ -0,0 +1,19 @@ +# frv testcase for sthu $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sthu +sthu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + sthu gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xbeef,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/sim/frv/sti.cgs b/sim/testsuite/sim/frv/sti.cgs new file mode 100644 index 00000000000..ce05003d227 --- /dev/null +++ b/sim/testsuite/sim/frv/sti.cgs @@ -0,0 +1,37 @@ +# frv testcase for sti $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sti +sti: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr22 + set_gr_limmed 0xffff,0xffff,gr8 + + sti gr8,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x804,sp ; 2052 + sti gr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4088,sp + sti gr8,@(sp,0x7fc) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xffff,gr20 + + pass diff --git a/sim/testsuite/sim/frv/stq.cgs b/sim/testsuite/sim/frv/stq.cgs new file mode 100644 index 00000000000..5ec836952f0 --- /dev/null +++ b/sim/testsuite/sim/frv/stq.cgs @@ -0,0 +1,53 @@ +# frv testcase for stq $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stq +stq: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + stq gr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr4 ; sp is gr1 + set_gr_limmed 0xbeef,0xdead,gr0 + set_gr_limmed 0xdead,0xbeef,gr1 + set_gr_limmed 0xdead,0xdead,gr2 + set_gr_limmed 0xbeef,0xbeef,gr3 + stq gr0,@(gr4,gr7) + test_mem_immed 0,gr4 + inc_gr_immed 4,gr4 + test_mem_immed 0,gr4 + inc_gr_immed 4,gr4 + test_mem_immed 0,gr4 + inc_gr_immed 4,gr4 + test_mem_immed 0,gr4 + + pass diff --git a/sim/testsuite/sim/frv/stq.pcgs b/sim/testsuite/sim/frv/stq.pcgs new file mode 100644 index 00000000000..268dd9eafbf --- /dev/null +++ b/sim/testsuite/sim/frv/stq.pcgs @@ -0,0 +1,59 @@ +# frv parallel testcase for stq $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stq +stq: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + stq gr8,@(sp,gr7) ; non parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + stq.p gr8,@(sp,gr7) ; parallel + setlos 0,gr8 + ldq @(sp,gr7),gr12 + test_mem_limmed 0xbeef,0xdead,sp ; memory is set + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + test_gr_immed 0xbeefdead,gr12 + test_gr_immed 0xdeadbeef,gr13 + test_gr_immed 0xdeaddead,gr14 + test_gr_immed 0xbeefbeef,gr15 + + pass diff --git a/sim/testsuite/sim/frv/stqc.cgs b/sim/testsuite/sim/frv/stqc.cgs new file mode 100644 index 00000000000..19fc79d6e09 --- /dev/null +++ b/sim/testsuite/sim/frv/stqc.cgs @@ -0,0 +1,32 @@ +# frv testcase for stqc $CPRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqc +stqc: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + set_cpr_limmed 0xdead,0xdead,cpr10 + set_cpr_limmed 0xbeef,0xbeef,cpr11 + stqc cpr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stqc.pcgs b/sim/testsuite/sim/frv/stqc.pcgs new file mode 100644 index 00000000000..bda68bac785 --- /dev/null +++ b/sim/testsuite/sim/frv/stqc.pcgs @@ -0,0 +1,60 @@ +# frv parallel testcase for stqc $CPRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqc +stqc: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + set_cpr_limmed 0xdead,0xdead,cpr10 + set_cpr_limmed 0xbeef,0xbeef,cpr11 + stqc cpr8,@(sp,gr7) ; non parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + set_cpr_limmed 0xdead,0xdead,cpr10 + set_cpr_limmed 0xbeef,0xbeef,cpr11 + stqc.p cpr8,@(sp,gr7) ; parallel + addi sp,4,sp + subi sp,4,sp + ldqc @(sp,gr7),cpr12 + test_mem_limmed 0xbeef,0xdead,sp ; memory is set + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + test_cpr_limmed 0xbeef,0xdead,cpr12 + test_cpr_limmed 0xdead,0xbeef,cpr13 + test_cpr_limmed 0xdead,0xdead,cpr14 + test_cpr_limmed 0xbeef,0xbeef,cpr15 + + pass diff --git a/sim/testsuite/sim/frv/stqcu.cgs b/sim/testsuite/sim/frv/stqcu.cgs new file mode 100644 index 00000000000..a7746caa538 --- /dev/null +++ b/sim/testsuite/sim/frv/stqcu.cgs @@ -0,0 +1,66 @@ +# frv testcase for stqcu $CPRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqcu +stqcu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + set_cpr_limmed 0xdead,0xdead,cpr10 + set_cpr_limmed 0xbeef,0xbeef,cpr11 + stqcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + inc_gr_immed -28,sp + set_gr_immed 16,gr7 + set_cpr_limmed 0x1111,0x1111,cpr8 + set_cpr_limmed 0x2222,0x2222,cpr9 + set_cpr_limmed 0x3333,0x3333,cpr10 + set_cpr_limmed 0x4444,0x4444,cpr11 + stqcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0x1111,0x1111,sp + inc_gr_immed 4,sp + test_mem_limmed 0x2222,0x2222,sp + inc_gr_immed 4,sp + test_mem_limmed 0x3333,0x3333,sp + inc_gr_immed 4,sp + test_mem_limmed 0x4444,0x4444,sp + + inc_gr_immed 4,sp + set_gr_immed -16,gr7 + set_cpr_limmed 0x5555,0x5555,cpr8 + set_cpr_limmed 0x6666,0x6666,cpr9 + set_cpr_limmed 0x7777,0x7777,cpr10 + set_cpr_limmed 0x8888,0x8888,cpr11 + stqcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0x5555,0x5555,sp + inc_gr_immed 4,sp + test_mem_limmed 0x6666,0x6666,sp + inc_gr_immed 4,sp + test_mem_limmed 0x7777,0x7777,sp + inc_gr_immed 4,sp + test_mem_limmed 0x8888,0x8888,sp + + pass diff --git a/sim/testsuite/sim/frv/stqf.cgs b/sim/testsuite/sim/frv/stqf.cgs new file mode 100644 index 00000000000..24dbb42ff35 --- /dev/null +++ b/sim/testsuite/sim/frv/stqf.cgs @@ -0,0 +1,32 @@ +# frv testcase for stqf $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqf +stqf: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + set_fr_iimmed 0xdead,0xdead,fr10 + set_fr_iimmed 0xbeef,0xbeef,fr11 + stqf fr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stqf.pcgs b/sim/testsuite/sim/frv/stqf.pcgs new file mode 100644 index 00000000000..497f5fb8096 --- /dev/null +++ b/sim/testsuite/sim/frv/stqf.pcgs @@ -0,0 +1,59 @@ +# frv parallel testcase for stqf $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqf +stqf: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + set_fr_iimmed 0xdead,0xdead,fr10 + set_fr_iimmed 0xbeef,0xbeef,fr11 + stqf fr8,@(sp,gr7) ; non-parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + set_fr_iimmed 0xdead,0xdead,fr10 + set_fr_iimmed 0xbeef,0xbeef,fr11 + stqf.p fr8,@(sp,gr7) ; parallel + fnegs fr8,fr8 + ldqf @(sp,gr7),fr12 + test_mem_limmed 0xbeef,0xdead,sp ; memory is set + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + test_fr_iimmed 0xbeefdead,fr12 + test_fr_iimmed 0xdeadbeef,fr13 + test_fr_iimmed 0xdeaddead,fr14 + test_fr_iimmed 0xbeefbeef,fr15 + + pass diff --git a/sim/testsuite/sim/frv/stqfi.cgs b/sim/testsuite/sim/frv/stqfi.cgs new file mode 100644 index 00000000000..6a36a903fb8 --- /dev/null +++ b/sim/testsuite/sim/frv/stqfi.cgs @@ -0,0 +1,95 @@ +# frv testcase for stqfi $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqfi +stqfi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr10 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr11 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr12 + inc_gr_immed -4,sp + set_mem_limmed 0x8765,0x4321,sp + set_gr_gr sp,gr13 + inc_gr_immed -4,sp + set_mem_limmed 0xfedc,0xba98,sp + set_gr_gr sp,gr14 + inc_gr_immed -4,sp + set_mem_limmed 0x89ab,0xcdef,sp + set_gr_gr sp,gr15 + inc_gr_immed -4,sp + set_mem_limmed 0x2345,0x6789,sp + set_gr_gr sp,gr16 + inc_gr_immed -4,sp + set_mem_limmed 0x9876,0x5432,sp + set_gr_gr sp,gr17 + inc_gr_immed -4,sp + set_mem_limmed 0x3456,0x789a,sp + set_gr_gr sp,gr18 + inc_gr_immed -4,sp + set_mem_limmed 0xa987,0x6543,sp + set_gr_gr sp,gr19 + inc_gr_immed -4,sp + set_mem_limmed 0x4567,0x89ab,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xba98,0x7654,sp + set_gr_gr sp,gr21 + set_fr_iimmed 0xffff,0xffff,fr8 + set_fr_iimmed 0xeeee,0xeeee,fr9 + set_fr_iimmed 0xdddd,0xdddd,fr10 + set_fr_iimmed 0xcccc,0xcccc,fr11 + + stqfi fr8,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0x9876,0x5432,gr17 + test_mem_limmed 0x2345,0x6789,gr16 + test_mem_limmed 0x89ab,0xcdef,gr15 + test_mem_limmed 0xfedc,0xba98,gr14 + test_mem_limmed 0x8765,0x4321,gr13 + test_mem_limmed 0x1234,0x5678,gr12 + test_mem_limmed 0xbeef,0xdead,gr11 + test_mem_limmed 0xdead,0xbeef,gr10 + + inc_gr_immed 0x810,sp ; 2064 + stqfi fr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xffff,0xffff,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xdddd,0xdddd,gr15 + test_mem_limmed 0xcccc,0xcccc,gr14 + test_mem_limmed 0x8765,0x4321,gr13 + test_mem_limmed 0x1234,0x5678,gr12 + test_mem_limmed 0xbeef,0xdead,gr11 + test_mem_limmed 0xdead,0xbeef,gr10 + + inc_gr_immed -4064,sp + stqfi fr8,@(sp,0x7f0) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xffff,0xffff,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xdddd,0xdddd,gr15 + test_mem_limmed 0xcccc,0xcccc,gr14 + test_mem_limmed 0xffff,0xffff,gr13 + test_mem_limmed 0xeeee,0xeeee,gr12 + test_mem_limmed 0xdddd,0xdddd,gr11 + test_mem_limmed 0xcccc,0xcccc,gr10 + + pass diff --git a/sim/testsuite/sim/frv/stqfu.cgs b/sim/testsuite/sim/frv/stqfu.cgs new file mode 100644 index 00000000000..80a1494d973 --- /dev/null +++ b/sim/testsuite/sim/frv/stqfu.cgs @@ -0,0 +1,35 @@ +# frv testcase for stqfu $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqfu +stqfu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + set_fr_iimmed 0xdead,0xdead,fr10 + set_fr_iimmed 0xbeef,0xbeef,fr11 + stqfu fr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stqi.cgs b/sim/testsuite/sim/frv/stqi.cgs new file mode 100644 index 00000000000..5a3680ef1c3 --- /dev/null +++ b/sim/testsuite/sim/frv/stqi.cgs @@ -0,0 +1,95 @@ +# frv testcase for stqi $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqi +stqi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr10 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr11 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr12 + inc_gr_immed -4,sp + set_mem_limmed 0x8765,0x4321,sp + set_gr_gr sp,gr13 + inc_gr_immed -4,sp + set_mem_limmed 0xfedc,0xba98,sp + set_gr_gr sp,gr14 + inc_gr_immed -4,sp + set_mem_limmed 0x89ab,0xcdef,sp + set_gr_gr sp,gr15 + inc_gr_immed -4,sp + set_mem_limmed 0x2345,0x6789,sp + set_gr_gr sp,gr16 + inc_gr_immed -4,sp + set_mem_limmed 0x9876,0x5432,sp + set_gr_gr sp,gr17 + inc_gr_immed -4,sp + set_mem_limmed 0x3456,0x789a,sp + set_gr_gr sp,gr18 + inc_gr_immed -4,sp + set_mem_limmed 0xa987,0x6543,sp + set_gr_gr sp,gr19 + inc_gr_immed -4,sp + set_mem_limmed 0x4567,0x89ab,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xba98,0x7654,sp + set_gr_gr sp,gr21 + set_gr_limmed 0xffff,0xffff,gr4 + set_gr_limmed 0xeeee,0xeeee,gr5 + set_gr_limmed 0xdddd,0xdddd,gr6 + set_gr_limmed 0xcccc,0xcccc,gr7 + + stqi gr4,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0x9876,0x5432,gr17 + test_mem_limmed 0x2345,0x6789,gr16 + test_mem_limmed 0x89ab,0xcdef,gr15 + test_mem_limmed 0xfedc,0xba98,gr14 + test_mem_limmed 0x8765,0x4321,gr13 + test_mem_limmed 0x1234,0x5678,gr12 + test_mem_limmed 0xbeef,0xdead,gr11 + test_mem_limmed 0xdead,0xbeef,gr10 + + inc_gr_immed 0x810,sp ; 2064 + stqi gr4,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xffff,0xffff,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xdddd,0xdddd,gr15 + test_mem_limmed 0xcccc,0xcccc,gr14 + test_mem_limmed 0x8765,0x4321,gr13 + test_mem_limmed 0x1234,0x5678,gr12 + test_mem_limmed 0xbeef,0xdead,gr11 + test_mem_limmed 0xdead,0xbeef,gr10 + + inc_gr_immed -4064,sp + stqi gr4,@(sp,0x7f0) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xffff,0xffff,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xdddd,0xdddd,gr15 + test_mem_limmed 0xcccc,0xcccc,gr14 + test_mem_limmed 0xffff,0xffff,gr13 + test_mem_limmed 0xeeee,0xeeee,gr12 + test_mem_limmed 0xdddd,0xdddd,gr11 + test_mem_limmed 0xcccc,0xcccc,gr10 + + pass diff --git a/sim/testsuite/sim/frv/stqu.cgs b/sim/testsuite/sim/frv/stqu.cgs new file mode 100644 index 00000000000..31e8de51a6a --- /dev/null +++ b/sim/testsuite/sim/frv/stqu.cgs @@ -0,0 +1,35 @@ +# frv testcase for stqu $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqu +stqu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + stqu gr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stu.cgs b/sim/testsuite/sim/frv/stu.cgs new file mode 100644 index 00000000000..cc480405426 --- /dev/null +++ b/sim/testsuite/sim/frv/stu.cgs @@ -0,0 +1,19 @@ +# frv testcase for stu $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stu +stu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + stu gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/sim/frv/sub.cgs b/sim/testsuite/sim/frv/sub.cgs new file mode 100644 index 00000000000..5a1410ca6f2 --- /dev/null +++ b/sim/testsuite/sim/frv/sub.cgs @@ -0,0 +1,26 @@ +# frv testcase for sub $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sub +sub: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + sub gr8,gr7,gr8 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + sub gr8,gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + + sub gr8,gr8,gr8 + test_gr_immed 0,gr8 + + sub gr8,gr7,gr8 + test_gr_immed -1,gr8 + + pass diff --git a/sim/testsuite/sim/frv/subcc.cgs b/sim/testsuite/sim/frv/subcc.cgs new file mode 100644 index 00000000000..188e0ff8a99 --- /dev/null +++ b/sim/testsuite/sim/frv/subcc.cgs @@ -0,0 +1,34 @@ +# frv testcase for subcc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global subcc +subcc: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + subcc gr8,gr7,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + subcc gr8,gr7,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_icc 0x0b,0 ; Set mask opposite of expected + subcc gr8,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Set mask opposite of expected + subcc gr8,gr7,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + pass diff --git a/sim/testsuite/sim/frv/subi.cgs b/sim/testsuite/sim/frv/subi.cgs new file mode 100644 index 00000000000..c6328389f58 --- /dev/null +++ b/sim/testsuite/sim/frv/subi.cgs @@ -0,0 +1,56 @@ +# frv testcase for subi $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global subi +subi: + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + subi gr8,1,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + subi gr8,1,gr8 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x7ff,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + subi gr8,0x7ff,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Set mask opposite of expected + subi gr8,1,gr8 + test_icc 0 1 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + subi gr8,-1,gr8 + test_icc 1 1 1 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + subi gr8,-1,gr8 + test_icc 0 1 1 0 icc0 + test_gr_limmed 0x8000,0x0001,gr8 + + set_gr_immed -2048,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + subi gr8,-2048,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_icc 0x0e,0 ; Set mask opposite of expected + subi gr8,-1,gr8 + test_icc 1 1 1 0 icc0 + test_gr_immed 1,gr8 + + pass diff --git a/sim/testsuite/sim/frv/subicc.cgs b/sim/testsuite/sim/frv/subicc.cgs new file mode 100644 index 00000000000..b2296ee02c8 --- /dev/null +++ b/sim/testsuite/sim/frv/subicc.cgs @@ -0,0 +1,56 @@ +# frv testcase for subicc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global subicc +subicc: + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + subicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + subicc gr8,1,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x1ff,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + subicc gr8,0x1ff,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Set mask opposite of expected + subicc gr8,1,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + subicc gr8,-1,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + subicc gr8,-1,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0x8000,0x0001,gr8 + + set_gr_immed -512,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + subicc gr8,-512,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x0e,0 ; Set mask opposite of expected + subicc gr8,-1,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + + pass diff --git a/sim/testsuite/sim/frv/subx.cgs b/sim/testsuite/sim/frv/subx.cgs new file mode 100644 index 00000000000..4559a52cdd7 --- /dev/null +++ b/sim/testsuite/sim/frv/subx.cgs @@ -0,0 +1,60 @@ +# frv testcase for subx $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global subx +subx: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry is off + subx gr8,gr7,gr8,icc0 + test_icc 1 1 1 0 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0c,0 ; Make sure carry is off + subx gr8,gr7,gr8,icc0 + test_icc 1 1 0 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_icc 0x0a,0 ; Make sure carry is off + subx gr8,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Make sure carry is off + subx gr8,gr7,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 3,gr8 + set_icc 0x0f,0 ; Make sure carry is on + subx gr8,gr7,gr8,icc0 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 0,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Make sure carry is on + subx gr8,gr7,gr8,icc0 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0x7fff,0xfffe,gr7 + set_icc 0x0b,0 ; Make sure carry is on + subx gr8,gr7,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 0,gr7 + set_icc 0x07,0 ; Make sure carry is on + subx gr8,gr7,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + pass diff --git a/sim/testsuite/sim/frv/subxcc.cgs b/sim/testsuite/sim/frv/subxcc.cgs new file mode 100644 index 00000000000..713a2a71be0 --- /dev/null +++ b/sim/testsuite/sim/frv/subxcc.cgs @@ -0,0 +1,60 @@ +# frv testcase for subxcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global subxcc +subxcc: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry is off + subxcc gr8,gr7,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0c,0 ; Make sure carry is off + subxcc gr8,gr7,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_icc 0x0a,0 ; Make sure carry is off + subxcc gr8,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Make sure carry is off + subxcc gr8,gr7,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 3,gr8 + set_icc 0x0f,0 ; Make sure carry is on + subxcc gr8,gr7,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 0,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Make sure carry is on + subxcc gr8,gr7,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0x7fff,0xfffe,gr7 + set_icc 0x0b,0 ; Make sure carry is on + subxcc gr8,gr7,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 0,gr7 + set_icc 0x07,0 ; Make sure carry is on + subxcc gr8,gr7,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + pass diff --git a/sim/testsuite/sim/frv/subxi.cgs b/sim/testsuite/sim/frv/subxi.cgs new file mode 100644 index 00000000000..bbe8e4ddfdf --- /dev/null +++ b/sim/testsuite/sim/frv/subxi.cgs @@ -0,0 +1,61 @@ +# frv testcase for subxi $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global subxi +subxi: + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry is off + subxi gr8,1,gr8,icc0 + test_icc 1 1 1 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0c,0 ; Make sure carry is off + subxi gr8,1,gr8,icc0 + test_icc 1 1 0 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x1ff,gr8 + set_icc 0x0a,0 ; Make sure carry is off + subxi gr8,0x1ff,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Make sure carry is off + subxi gr8,1,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 3,gr8 + set_icc 0x0f,0 ; Make sure carry is on + subxi gr8,1,gr8,icc0 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Make sure carry is on + subxi gr8,0,gr8,icc0 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x200,gr8 + set_icc 0x0b,0 ; Make sure carry is on + subxi gr8,0x1ff,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_icc 0x07,0 ; Make sure carry is on + subxi gr8,0,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_icc 0x07,0 ; Make sure carry is on + subxi gr8,-512,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 510,gr8 + + pass diff --git a/sim/testsuite/sim/frv/subxicc.cgs b/sim/testsuite/sim/frv/subxicc.cgs new file mode 100644 index 00000000000..369cab9dce0 --- /dev/null +++ b/sim/testsuite/sim/frv/subxicc.cgs @@ -0,0 +1,61 @@ +# frv testcase for subxicc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global subxicc +subxicc: + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry is off + subxicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0c,0 ; Make sure carry is off + subxicc gr8,1,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x1ff,gr8 + set_icc 0x0a,0 ; Make sure carry is off + subxicc gr8,0x1ff,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Make sure carry is off + subxicc gr8,1,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 3,gr8 + set_icc 0x0f,0 ; Make sure carry is on + subxicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Make sure carry is on + subxicc gr8,0,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x200,gr8 + set_icc 0x0b,0 ; Make sure carry is on + subxicc gr8,0x1ff,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x07,0 ; Make sure carry is on + subxicc gr8,0,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_icc 0x07,0 ; Make sure carry is on + subxicc gr8,-512,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 510,gr8 + + pass diff --git a/sim/testsuite/sim/frv/swap.cgs b/sim/testsuite/sim/frv/swap.cgs new file mode 100644 index 00000000000..1e229032868 --- /dev/null +++ b/sim/testsuite/sim/frv/swap.cgs @@ -0,0 +1,42 @@ +# frv testcase for swap @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global swap +swap: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + swap @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 0,gr7 + swap @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + swap @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xbeef,0xdead,gr20 + + pass diff --git a/sim/testsuite/sim/frv/swapi.cgs b/sim/testsuite/sim/frv/swapi.cgs new file mode 100644 index 00000000000..4951bfa7cfd --- /dev/null +++ b/sim/testsuite/sim/frv/swapi.cgs @@ -0,0 +1,39 @@ +# frv testcase for swapi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global swapi +swapi: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + swapi @(sp,-4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + swapi @(sp,0),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + swapi @(sp,4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xbeef,0xdead,gr20 + + pass diff --git a/sim/testsuite/sim/frv/tc.cgs b/sim/testsuite/sim/frv/tc.cgs new file mode 100644 index 00000000000..116190b0f59 --- /dev/null +++ b/sim/testsuite/sim/frv/tc.cgs @@ -0,0 +1,101 @@ +# frv testcase for tc $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tc +tc: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x6 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/teq.cgs b/sim/testsuite/sim/frv/teq.cgs new file mode 100644 index 00000000000..59c60914a7c --- /dev/null +++ b/sim/testsuite/sim/frv/teq.cgs @@ -0,0 +1,101 @@ +# frv testcase for teq $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global teq +teq: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x2 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xa 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/testutils.inc b/sim/testsuite/sim/frv/testutils.inc new file mode 100644 index 00000000000..e9bfd8668af --- /dev/null +++ b/sim/testsuite/sim/frv/testutils.inc @@ -0,0 +1,646 @@ +# gr28-gr31, fr31, icc3, fcc3 are used as tmps. +# consider them call clobbered by these macros. + + .macro start + .data +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + .text + .global _start +_start: + ; enable data and insn caches in copy-back mode + ; Also enable all registers + or_spr_immed 0xc80003c0,hsr0 + and_spr_immed 0xfffff3ff,hsr0 + + ; turn on psr.nem, psr.cm, psr.ef, psr.em, psr.esr, + ; disable external interrupts + or_spr_immed 0x69f8,psr + + ; If fsr exists, enable all fp_exceptions except inexact + movsg psr,gr28 + srli gr28,28,gr28 + subicc gr28,0x2,gr0,icc3 ; is fr400? + beq icc3,0,nofsr0 + or_spr_immed 0x3d000000,fsr0 +nofsr0: + + ; Set the stack pointer + sethi.p 0x7,sp + setlo 0xfffc,sp ; TODO -- what's a good value for this? + + ; Set the TBR address + sethi.p 0xf,gr28 + setlo 0xf000,gr28 + movgs gr28,tbr ; TODO -- what's a good value for this? + + ; Go to user mode -- causes too many problems + ;and_spr_immed 0xfffffffb,psr + .endm + +; Set GR with another GR + .macro set_gr_gr src targ + addi \src,0,\targ + .endm + +; Set GR with immediate value + .macro set_gr_immed val reg + .if (\val >= -32768) && (\val <= 23767) + setlos \val,\reg + .else + setlo.p %lo(\val),\reg + sethi %hi(\val),\reg + .endif + .endm + + .macro set_gr_limmed valh vall reg + sethi.p \valh,\reg + setlo \vall,\reg + .endm + +; Set GR with address value + .macro set_gr_addr addr reg + sethi.p %hi(\addr),\reg + setlo %lo(\addr),\reg + .endm + +; Set GR with SPR + .macro set_gr_spr src targ + movsg \src,\targ + .endm + +; Set GR with a value from memory + .macro set_gr_mem addr reg + set_gr_addr \addr,gr28 + ldi @(gr28,0),\reg + .endm + +; Increment GR with immediate value + .macro inc_gr_immed val reg + .if (\val >= -2048) && (\val <= 2047) + addi \reg,\val,\reg + .else + set_gr_immed \val,gr28 + add \reg,gr28,\reg + .endif + .endm + +; AND GR with immediate value + .macro and_gr_immed val reg + .if (\val >= -2048) && (\val <= 2047) + andi \reg,\val,\reg + .else + set_gr_immed \val,gr28 + and \reg,gr28,\reg + .endif + .endm + +; Set FR with another FR + .macro set_fr_fr src targ + fmovs \src,\targ + .endm + +; Set FR with integer immediate value + .macro set_fr_iimmed valh vall reg + set_gr_limmed \valh,\vall,gr28 + movgf gr28,\reg + .endm + +; Set FR with integer immediate value + .macro set_fr_immed val reg + set_gr_immed \val,gr28 + movgf gr28,\reg + .endm + +; Set FR with a value from memory + .macro set_fr_mem addr reg + set_gr_addr \addr,gr28 + ldfi @(gr28,0),\reg + .endm + +; Set double FR with another double FR + .macro set_dfr_dfr src targ + fmovd \src,\targ + .endm + +; Set double FR with a value from memory + .macro set_dfr_mem addr reg + set_gr_addr \addr,gr28 + lddfi @(gr28,0),\reg + .endm + +; Set CPR with immediate value + .macro set_cpr_immed val reg + addi sp,-4,gr28 + set_gr_immed \val,gr29 + st gr29,@(gr28,gr0) + ldc @(gr28,gr0),\reg + .endm + + .macro set_cpr_limmed valh vall reg + addi sp,-4,gr28 + set_gr_limmed \valh,\vall,gr29 + st gr29,@(gr28,gr0) + ldc @(gr28,gr0),\reg + .endm + +; Set SPR with immediate value + .macro set_spr_immed val reg + set_gr_immed \val,gr28 + movgs gr28,\reg + .endm + + .macro set_spr_limmed valh vall reg + set_gr_limmed \valh,\vall,gr28 + movgs gr28,\reg + .endm + + .macro set_spr_addr addr reg + set_gr_addr \addr,gr28 + movgs gr28,\reg + .endm + +; increment SPR with immediate value + .macro inc_spr_immed val reg + movsg \reg,gr28 + inc_gr_immed \val,gr28 + movgs gr28,\reg + .endm + +; OR spr with immediate value + .macro or_spr_immed val reg + movsg \reg,gr28 + set_gr_immed \val,gr29 + or gr28,gr29,gr28 + movgs gr28,\reg + .endm + +; AND spr with immediate value + .macro and_spr_immed val reg + movsg \reg,gr28 + set_gr_immed \val,gr29 + and gr28,gr29,gr28 + movgs gr28,\reg + .endm + +; Set accumulator with immediate value + .macro set_acc_immed val reg + set_fr_immed \val,fr31 + mwtacc fr31,\reg + .endm + +; Set accumulator guard with immediate value + .macro set_accg_immed val reg + set_fr_immed \val,fr31 + mwtaccg fr31,\reg + .endm + +; Set memory with immediate value + .macro set_mem_immed val base + set_gr_immed \val,gr28 + sti gr28,@(\base,0) + .endm + + .macro set_mem_limmed valh vall base + set_gr_limmed \valh,\vall,gr28 + sti gr28,@(\base,0) + .endm + +; Set memory with GR value + .macro set_mem_gr reg addr + set_gr_addr \addr,gr28 + sti \reg,@(gr28,0) + .endm + +; Test the value of a general register against another general register + .macro test_gr_gr reg1 reg2 + subcc \reg1,\reg2,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Test the value of an immediate against a general register + .macro test_gr_immed val reg + .if (\val >= -512) && (\val <= 511) + subicc \reg,\val,gr0,icc3 + .else + set_gr_immed \val,gr28 + subcc \reg,gr28,gr0,icc3 + .endif + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + + .macro test_gr_limmed valh vall reg + set_gr_limmed \valh,\vall,gr28 + subcc \reg,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Test the value of an floating register against an integer immediate + .macro test_fr_limmed valh vall reg + movfg \reg,gr29 + set_gr_limmed \valh,\vall,gr28 + subcc gr29,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + + .macro test_fr_iimmed val reg + movfg \reg,gr29 + set_gr_immed \val,gr28 + subcc gr29,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Test the value of a floating register against another floating point register + .macro test_fr_fr reg1 reg2 + fcmps \reg1,\reg2,fcc3 + fbeq fcc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Test the value of a double floating register against another +; double floating point register + .macro test_dfr_dfr reg1 reg2 + fcmpd \reg1,\reg2,fcc3 + fbeq fcc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Test the value of a special purpose register against an integer immediate + .macro test_spr_immed val reg + movsg \reg,gr29 + set_gr_immed \val,gr28 + subcc gr29,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + + .macro test_spr_limmed valh vall reg + movsg \reg,gr29 + set_gr_limmed \valh,\vall,gr28 + subcc gr29,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + + .macro test_spr_gr spr gr + movsg \spr,gr28 + test_gr_gr \gr,gr28 + .endm + + .macro test_spr_addr addr reg + movsg \reg,gr29 + set_gr_addr \addr,gr28 + test_gr_gr gr28,gr29 + .endm + +; Test spr bits masked and shifted against the given value + .macro test_spr_bits mask,shift,val,reg + movsg \reg,gr28 + set_gr_immed \mask,gr29 + and gr28,gr29,gr28 + srli gr28,\shift,gr29 + test_gr_immed \val,gr29 + .endm + + +; Test the value of an accumulator against an integer immediate + .macro test_acc_immed val reg + mrdacc \reg,fr31 + test_fr_iimmed \val,fr31 + .endm + +; Test the value of an accumulator against an integer immediate + .macro test_acc_limmed valh vall reg + mrdacc \reg,fr31 + test_fr_limmed \valh,\vall,fr31 + .endm + +; Test the value of an accumulator guard against an integer immediate + .macro test_accg_immed val reg + mrdaccg \reg,fr31 + test_fr_iimmed \val,fr31 + .endm + +; Test CPR agains an immediate value + .macro test_cpr_limmed valh vall reg + addi sp,-4,gr31 + stc \reg,@(gr31,gr0) + test_mem_limmed \valh,\vall,gr31 + .endm + +; Test the value of an immediate against memory + .macro test_mem_immed val base + ldi @(\base,0),gr29 + .if (\val >= -512) && (\val <= 511) + subicc gr29,\val,gr0,icc3 + .else + set_gr_immed \val,gr28 + subcc gr29,gr28,gr0,icc3 + .endif + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + + .macro test_mem_limmed valh vall base + ldi @(\base,0),gr29 + set_gr_limmed \valh,\vall,gr28 + subcc gr29,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Set an integer condition code + .macro set_icc mask iccno + set_gr_immed 4,gr29 + smuli gr29,\iccno,gr30 + addi gr31,16,gr31 + set_gr_immed 0xf,gr28 + sll gr28,gr31,gr28 + not gr28,gr28 + movsg ccr,gr29 + and gr28,gr29,gr29 + set_gr_immed \mask,gr28 + sll gr28,gr31,gr28 + or gr28,gr29,gr29 + movgs gr29,ccr + .endm +; started here +; Test the condition codes + .macro test_icc N Z V C iccno + .if (\N == 1) + bp \iccno,0,fail\@ + .else + bn \iccno,0,fail\@ + .endif + .if (\Z == 1) + bne \iccno,0,fail\@ + .else + beq \iccno,0,fail\@ + .endif + .if (\V == 1) + bnv \iccno,0,fail\@ + .else + bv \iccno,0,fail\@ + .endif + .if (\C == 1) + bnc \iccno,0,fail\@ + .else + bc \iccno,0,fail\@ + .endif + bra test_cc\@ +fail\@: + fail +test_cc\@: + .endm + +; Set an floating point condition code + .macro set_fcc mask fccno + set_gr_immed 4,gr29 + smuli gr29,\fccno,gr30 + set_gr_immed 0xf,gr28 + sll gr28,gr31,gr28 + not gr28,gr28 + movsg ccr,gr29 + and gr28,gr29,gr29 + set_gr_immed \mask,gr28 + sll gr28,gr31,gr28 + or gr28,gr29,gr29 + movgs gr29,ccr + .endm + +; Test the condition codes + .macro test_fcc val fccno + set_gr_immed 4,gr29 + smuli gr29,\fccno,gr30 + movsg ccr,gr29 + srl gr29,gr31,gr29 + andi gr29,0xf,gr29 + test_gr_immed \val,gr29 + .endm + +; Set PSR.ET + .macro set_psr_et val + movsg psr,gr28 + .if (\val == 1) + ori gr28,1,gr28 ; Turn on SPR.ET + .else + andi gr28,0xfffffffe,gr28 ; Turn off SPR.ET + .endif + movgs gr28,psr + .endm + +; Floating point constants + .macro float_constants +f0: .float 0.0 +f1: .float 1.0 +f2: .float 2.0 +f3: .float 3.0 +f6: .float 6.0 +f9: .float 9.0 +fn0: .float -0.0 +fn1: .float -1.0 +finf: .long 0x7f800000 +fninf: .long 0xff800000 +fmax: .long 0x7f7fffff +fmin: .long 0xff7fffff +feps: .long 0x00400000 +fneps: .long 0x80400000 +fnan1: .long 0x7fc00000 +fnan2: .long 0x7f800001 + .endm + + .macro double_constants +d0: .double 0.0 +d1: .double 1.0 +d2: .double 2.0 +d3: .double 3.0 +d6: .double 6.0 +d9: .double 9.0 +dn0: .double -0.0 +dn1: .double -1.0 +dinf: .long 0x7ff00000 + .long 0x00000000 +dninf: .long 0xfff00000 + .long 0x00000000 +dmax: .long 0x7fefffff + .long 0xffffffff +dmin: .long 0xffefffff + .long 0xffffffff +deps: .long 0x00080000 + .long 0x00000000 +dneps: .long 0x80080000 + .long 0x00000000 +dnan1: .long 0x7ff80000 + .long 0x00000000 +dnan2: .long 0x7ff00000 + .long 0x00000001 + .endm + +; Load floating point constants + .macro load_float_constants + set_fr_mem fninf,fr0 + set_fr_mem fmin,fr4 + set_fr_mem fn1,fr8 + set_fr_mem fneps,fr12 + set_fr_mem fn0,fr16 + set_fr_mem f0,fr20 + set_fr_mem feps,fr24 + set_fr_mem f1,fr28 + set_fr_mem f2,fr32 + set_fr_mem f3,fr36 + set_fr_mem f6,fr40 + set_fr_mem f9,fr44 + set_fr_mem fmax,fr48 + set_fr_mem finf,fr52 + set_fr_mem fnan1,fr56 + set_fr_mem fnan2,fr60 + .endm + + .macro load_float_constants1 + set_fr_mem fninf,fr1 + set_fr_mem fmin,fr5 + set_fr_mem fn1,fr9 + set_fr_mem fneps,fr13 + set_fr_mem fn0,fr17 + set_fr_mem f0,fr21 + set_fr_mem feps,fr25 + set_fr_mem f1,fr29 + set_fr_mem f2,fr33 + set_fr_mem f3,fr37 + set_fr_mem f6,fr41 + set_fr_mem f9,fr45 + set_fr_mem fmax,fr49 + set_fr_mem finf,fr53 + set_fr_mem fnan1,fr57 + set_fr_mem fnan2,fr61 + .endm + + .macro load_float_constants2 + set_fr_mem fninf,fr2 + set_fr_mem fmin,fr6 + set_fr_mem fn1,fr10 + set_fr_mem fneps,fr14 + set_fr_mem fn0,fr18 + set_fr_mem f0,fr22 + set_fr_mem feps,fr26 + set_fr_mem f1,fr30 + set_fr_mem f2,fr34 + set_fr_mem f3,fr38 + set_fr_mem f6,fr42 + set_fr_mem f9,fr46 + set_fr_mem fmax,fr50 + set_fr_mem finf,fr54 + set_fr_mem fnan1,fr58 + set_fr_mem fnan2,fr62 + .endm + + .macro load_float_constants3 + set_fr_mem fninf,fr3 + set_fr_mem fmin,fr7 + set_fr_mem fn1,fr11 + set_fr_mem fneps,fr15 + set_fr_mem fn0,fr19 + set_fr_mem f0,fr23 + set_fr_mem feps,fr27 + set_fr_mem f1,fr31 + set_fr_mem f2,fr35 + set_fr_mem f3,fr39 + set_fr_mem f6,fr43 + set_fr_mem f9,fr47 + set_fr_mem fmax,fr51 + set_fr_mem finf,fr55 + set_fr_mem fnan1,fr59 + set_fr_mem fnan2,fr63 + .endm + + .macro load_double_constants + set_dfr_mem dninf,fr0 + set_dfr_mem dmin,fr4 + set_dfr_mem dn1,fr8 + set_dfr_mem dneps,fr12 + set_dfr_mem dn0,fr16 + set_dfr_mem d0,fr20 + set_dfr_mem deps,fr24 + set_dfr_mem d1,fr28 + set_dfr_mem d2,fr32 + set_dfr_mem d3,fr36 + set_dfr_mem d6,fr40 + set_dfr_mem d9,fr44 + set_dfr_mem dmax,fr48 + set_dfr_mem dinf,fr52 + set_dfr_mem dnan1,fr56 + set_dfr_mem dnan2,fr60 + .endm + +; Lock the insn cache at the given address + .macro lock_insn_cache address + icpl \address,gr0,1 + .endm + +; Lock the data cache at the given address + .macro lock_data_cache address + dcpl \address,gr0,1 + .endm + +; Invalidate the data cache at the given address + .macro invalidate_data_cache address + dci @(\address,gr0) + .endm + +; Flush the data cache at the given address + .macro flush_data_cache address + dcf @(\address,gr0) + .endm + +; Write a bctrlr 0,0 insn at the address contained in the given register + .macro set_bctrlr_0_0 address + set_mem_immed 0x80382000,\address ; bctrlr 0,0 + flush_data_cache \address + .endm + +; Exit with return code + .macro exit rc + setlos #1,gr7 + set_gr_immed \rc,gr8 + tira gr0,#0 + .endm + +; Pass the test case + .macro pass +pass\@: + setlos.p #5,gr10 + setlos #1,gr8 + setlos #5,gr7 + set_gr_addr passmsg,gr9 + tira gr0,#0 + exit #0 + .endm + +; Fail the testcase + .macro fail +fail\@: + setlos.p #5,gr10 + setlos #1,gr8 + setlos #5,gr7 + set_gr_addr failmsg,gr9 + tira gr0,#0 + exit #1 + .endm diff --git a/sim/testsuite/sim/frv/tge.cgs b/sim/testsuite/sim/frv/tge.cgs new file mode 100644 index 00000000000..3e12d9245d1 --- /dev/null +++ b/sim/testsuite/sim/frv/tge.cgs @@ -0,0 +1,101 @@ +# frv testcase for tge $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tge +tge: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x6 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x8 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tgt.cgs b/sim/testsuite/sim/frv/tgt.cgs new file mode 100644 index 00000000000..7e01330f031 --- /dev/null +++ b/sim/testsuite/sim/frv/tgt.cgs @@ -0,0 +1,93 @@ +# frv testcase for tgt $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tgt +tgt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x8 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/thi.cgs b/sim/testsuite/sim/frv/thi.cgs new file mode 100644 index 00000000000..36cc9237647 --- /dev/null +++ b/sim/testsuite/sim/frv/thi.cgs @@ -0,0 +1,93 @@ +# frv testcase for thi $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global thi +thi: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_spr_addr bad,lr + set_icc 0x1 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x3 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x9 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_spr_addr bad,lr + set_icc 0xb 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xc 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tic.cgs b/sim/testsuite/sim/frv/tic.cgs new file mode 100644 index 00000000000..8c746f5d29c --- /dev/null +++ b/sim/testsuite/sim/frv/tic.cgs @@ -0,0 +1,100 @@ +# frv testcase for tic $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tic +tic: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x6 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tieq.cgs b/sim/testsuite/sim/frv/tieq.cgs new file mode 100644 index 00000000000..5dfc0e66f19 --- /dev/null +++ b/sim/testsuite/sim/frv/tieq.cgs @@ -0,0 +1,101 @@ +# frv testcase for tieq $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tieq +tieq: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x2 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr bad,lr + set_icc 0x8 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xa 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tige.cgs b/sim/testsuite/sim/frv/tige.cgs new file mode 100644 index 00000000000..cde3ac866c4 --- /dev/null +++ b/sim/testsuite/sim/frv/tige.cgs @@ -0,0 +1,101 @@ +# frv testcase for tige $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tige +tige: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr bad,lr + set_icc 0x6 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x8 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tigt.cgs b/sim/testsuite/sim/frv/tigt.cgs new file mode 100644 index 00000000000..163d92f179f --- /dev/null +++ b/sim/testsuite/sim/frv/tigt.cgs @@ -0,0 +1,92 @@ +# frv testcase for tigt $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tigt +tigt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x8 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tihi.cgs b/sim/testsuite/sim/frv/tihi.cgs new file mode 100644 index 00000000000..e564fc2982d --- /dev/null +++ b/sim/testsuite/sim/frv/tihi.cgs @@ -0,0 +1,92 @@ +# frv testcase for tihi $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tihi +tihi: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_spr_addr bad,lr + set_icc 0x1 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x3 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x9 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_spr_addr bad,lr + set_icc 0xb 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xc 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tile.cgs b/sim/testsuite/sim/frv/tile.cgs new file mode 100644 index 00000000000..7f5ef2a7ab8 --- /dev/null +++ b/sim/testsuite/sim/frv/tile.cgs @@ -0,0 +1,108 @@ +# frv testcase for tile $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tile +tile: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tils.cgs b/sim/testsuite/sim/frv/tils.cgs new file mode 100644 index 00000000000..5713de5cfc5 --- /dev/null +++ b/sim/testsuite/sim/frv/tils.cgs @@ -0,0 +1,108 @@ +# frv testcase for tils $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tils +tils: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tilt.cgs b/sim/testsuite/sim/frv/tilt.cgs new file mode 100644 index 00000000000..4d596b01b9f --- /dev/null +++ b/sim/testsuite/sim/frv/tilt.cgs @@ -0,0 +1,100 @@ +# frv testcase for tilt $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tilt +tilt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tin.cgs b/sim/testsuite/sim/frv/tin.cgs new file mode 100644 index 00000000000..f55c921c012 --- /dev/null +++ b/sim/testsuite/sim/frv/tin.cgs @@ -0,0 +1,100 @@ +# frv testcase for tin $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tin +tin: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x2 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tinc.cgs b/sim/testsuite/sim/frv/tinc.cgs new file mode 100644 index 00000000000..8e99e31531f --- /dev/null +++ b/sim/testsuite/sim/frv/tinc.cgs @@ -0,0 +1,100 @@ +# frv testcase for tinc $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tinc +tinc: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_spr_addr bad,lr + set_icc 0x1 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x3 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x5 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x7 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x9 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_spr_addr bad,lr + set_icc 0xb 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_spr_addr bad,lr + set_icc 0xd 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_spr_addr bad,lr + set_icc 0xf 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tine.cgs b/sim/testsuite/sim/frv/tine.cgs new file mode 100644 index 00000000000..d7e8b005416 --- /dev/null +++ b/sim/testsuite/sim/frv/tine.cgs @@ -0,0 +1,100 @@ +# frv testcase for tine $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tine +tine: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tino.cgs b/sim/testsuite/sim/frv/tino.cgs new file mode 100644 index 00000000000..65a2d6d2835 --- /dev/null +++ b/sim/testsuite/sim/frv/tino.cgs @@ -0,0 +1,53 @@ +# frv testcase for tino +# mach: all + + .include "testutils.inc" + + start + + .global tinev +tinev: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_gr_immed 0,gr7 + + set_icc 0x0 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x1 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x2 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x3 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x4 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x5 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x6 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x7 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x8 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x9 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xa 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xb 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xc 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xd 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xe 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xf 0 + tino ; should branch to tbr + (128 + 4)*16 + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tinv.cgs b/sim/testsuite/sim/frv/tinv.cgs new file mode 100644 index 00000000000..7ec34a42271 --- /dev/null +++ b/sim/testsuite/sim/frv/tinv.cgs @@ -0,0 +1,100 @@ +# frv testcase for tinv $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tinv +tinv: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x6 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tip.cgs b/sim/testsuite/sim/frv/tip.cgs new file mode 100644 index 00000000000..835342292f4 --- /dev/null +++ b/sim/testsuite/sim/frv/tip.cgs @@ -0,0 +1,100 @@ +# frv testcase for tip $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tip +tip: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xa 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xc 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tira.cgs b/sim/testsuite/sim/frv/tira.cgs new file mode 100644 index 00000000000..bd3139e628d --- /dev/null +++ b/sim/testsuite/sim/frv/tira.cgs @@ -0,0 +1,114 @@ +# frv testcase for tira $GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tira +tira: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass diff --git a/sim/testsuite/sim/frv/tiv.cgs b/sim/testsuite/sim/frv/tiv.cgs new file mode 100644 index 00000000000..84a25762eb7 --- /dev/null +++ b/sim/testsuite/sim/frv/tiv.cgs @@ -0,0 +1,100 @@ +# frv testcase for tiv $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tiv +tiv: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tle.cgs b/sim/testsuite/sim/frv/tle.cgs new file mode 100644 index 00000000000..1322821b60e --- /dev/null +++ b/sim/testsuite/sim/frv/tle.cgs @@ -0,0 +1,109 @@ +# frv testcase for tle $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tle +tle: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tls.cgs b/sim/testsuite/sim/frv/tls.cgs new file mode 100644 index 00000000000..708e61735c0 --- /dev/null +++ b/sim/testsuite/sim/frv/tls.cgs @@ -0,0 +1,109 @@ +# frv testcase for tls $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tls +tls: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tlt.cgs b/sim/testsuite/sim/frv/tlt.cgs new file mode 100644 index 00000000000..12ee05b7f97 --- /dev/null +++ b/sim/testsuite/sim/frv/tlt.cgs @@ -0,0 +1,101 @@ +# frv testcase for tlt $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tlt +tlt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tn.cgs b/sim/testsuite/sim/frv/tn.cgs new file mode 100644 index 00000000000..05b04240aa2 --- /dev/null +++ b/sim/testsuite/sim/frv/tn.cgs @@ -0,0 +1,101 @@ +# frv testcase for tn $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tn +tn: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x2 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tnc.cgs b/sim/testsuite/sim/frv/tnc.cgs new file mode 100644 index 00000000000..808db3c2c95 --- /dev/null +++ b/sim/testsuite/sim/frv/tnc.cgs @@ -0,0 +1,101 @@ +# frv testcase for tnc $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tnc +tnc: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_spr_addr bad,lr + set_icc 0x1 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x3 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x5 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x7 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x9 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_spr_addr bad,lr + set_icc 0xb 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_spr_addr bad,lr + set_icc 0xd 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_spr_addr bad,lr + set_icc 0xf 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tne.cgs b/sim/testsuite/sim/frv/tne.cgs new file mode 100644 index 00000000000..880188d2919 --- /dev/null +++ b/sim/testsuite/sim/frv/tne.cgs @@ -0,0 +1,101 @@ +# frv testcase for tne $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tne +tne: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tno.cgs b/sim/testsuite/sim/frv/tno.cgs new file mode 100644 index 00000000000..df499699367 --- /dev/null +++ b/sim/testsuite/sim/frv/tno.cgs @@ -0,0 +1,54 @@ +# frv testcase for tno +# mach: all + + .include "testutils.inc" + + start + + .global tno +tno: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_icc 0x0 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x1 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x2 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x3 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x4 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x5 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x6 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x7 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x8 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x9 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xa 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xb 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xc 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xd 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xe 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xf 0 + tno ; should branch to tbr + (128 + 4)*16 + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tnv.cgs b/sim/testsuite/sim/frv/tnv.cgs new file mode 100644 index 00000000000..d7f9241b05b --- /dev/null +++ b/sim/testsuite/sim/frv/tnv.cgs @@ -0,0 +1,101 @@ +# frv testcase for tnv $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tnv +tnv: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x6 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tp.cgs b/sim/testsuite/sim/frv/tp.cgs new file mode 100644 index 00000000000..2709e31cf2b --- /dev/null +++ b/sim/testsuite/sim/frv/tp.cgs @@ -0,0 +1,101 @@ +# frv testcase for tp $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tp +tp: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xa 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xc 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tra.cgs b/sim/testsuite/sim/frv/tra.cgs new file mode 100644 index 00000000000..368c83acdca --- /dev/null +++ b/sim/testsuite/sim/frv/tra.cgs @@ -0,0 +1,117 @@ +# frv testcase for tra $GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tra +tra: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 +bad0: + fail +ok0: + test_spr_addr bad0,pcsr + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass diff --git a/sim/testsuite/sim/frv/tv.cgs b/sim/testsuite/sim/frv/tv.cgs new file mode 100644 index 00000000000..d173f2994e4 --- /dev/null +++ b/sim/testsuite/sim/frv/tv.cgs @@ -0,0 +1,101 @@ +# frv testcase for tv $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tv +tv: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/udiv.cgs b/sim/testsuite/sim/frv/udiv.cgs new file mode 100644 index 00000000000..30c0715af18 --- /dev/null +++ b/sim/testsuite/sim/frv/udiv.cgs @@ -0,0 +1,48 @@ +# frv testcase for udiv $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global udiv +udiv: + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + udiv gr3,gr2,gr3 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + + ; example 1 from udiv in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + udiv gr3,gr2,gr3 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr + set_gr_addr e1,gr17 +e1: udiv gr1,gr0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/udivi.cgs b/sim/testsuite/sim/frv/udivi.cgs new file mode 100644 index 00000000000..12204a24d2a --- /dev/null +++ b/sim/testsuite/sim/frv/udivi.cgs @@ -0,0 +1,49 @@ +# frv testcase for udivi $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global udivi +udivi: + ; simple division 12 / 3 + set_gr_immed 0x0000000c,gr3 + udivi gr3,3,gr3 + test_gr_immed 0x00000004,gr3 + + ; random example + set_gr_limmed 0xfedc,0xba98,gr3 + udivi gr3,0x7ff,gr3 + test_gr_limmed 0x001f,0xdf93,gr3 + + ; random example + set_gr_limmed 0xffff,0xffff,gr3 + udivi gr3,-2048,gr3 + test_gr_immed 1,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr + set_gr_addr e1,gr17 +e1: udivi gr1,0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/umul.cgs b/sim/testsuite/sim/frv/umul.cgs new file mode 100644 index 00000000000..6c612217036 --- /dev/null +++ b/sim/testsuite/sim/frv/umul.cgs @@ -0,0 +1,76 @@ +# frv testcase for umul $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global umul +umul: + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + umul gr7,gr8,gr8 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + umul gr7,gr8,gr8 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xffff,0xffff,gr7 ; max positive result + set_gr_limmed 0xffff,0xffff,gr8 + umul gr7,gr8,gr8 + test_gr_limmed 0xffff,0xfffe,gr8 + test_gr_immed 1,gr9 + + pass diff --git a/sim/testsuite/sim/frv/umulcc.cgs b/sim/testsuite/sim/frv/umulcc.cgs new file mode 100644 index 00000000000..c2b5cff0ea5 --- /dev/null +++ b/sim/testsuite/sim/frv/umulcc.cgs @@ -0,0 +1,98 @@ +# frv testcase for umulcc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global umulcc +umulcc: + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 1,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xffff,0xffff,gr7 ; max positive result + set_gr_limmed 0xffff,0xffff,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xfffe,gr8 + test_gr_immed 1,gr9 + + pass diff --git a/sim/testsuite/sim/frv/umuli.cgs b/sim/testsuite/sim/frv/umuli.cgs new file mode 100644 index 00000000000..6f1b9c12211 --- /dev/null +++ b/sim/testsuite/sim/frv/umuli.cgs @@ -0,0 +1,87 @@ +# frv testcase for umuli $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global umuli +umuli: + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0x0f,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0x0e,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_icc 0x0f,0 ; Set mask opposite of expected + umuli gr7,1,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0x0b,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_icc 0x0a,0 ; Set mask opposite of expected + umuli gr7,0,gr8 + test_icc 1 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_icc 0x0f,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x0e,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result + set_icc 0x09,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_icc 0x0d,0 ; Set mask opposite of expected + umuli gr7,0x7ff,gr8 + test_icc 1 1 0 1 icc0 + test_gr_immed 0x3ff,gr8 + test_gr_limmed 0x7fff,0xf801,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_icc 0x09,0 ; Set mask opposite of expected + umuli gr7,-2048,gr8 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0x7fff,0xfc00,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0xffff,0xffff,gr7 ; max positive result + set_icc 0x05,0 ; Set mask opposite of expected + umuli gr7,-1,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xffff,0xfffe,gr8 + test_gr_immed 1,gr9 + + pass diff --git a/sim/testsuite/sim/frv/umulicc.cgs b/sim/testsuite/sim/frv/umulicc.cgs new file mode 100644 index 00000000000..0d0d0c1cd0c --- /dev/null +++ b/sim/testsuite/sim/frv/umulicc.cgs @@ -0,0 +1,87 @@ +# frv testcase for umulicc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global umulicc +umulicc: + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0x0f,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0x0e,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_icc 0x0f,0 ; Set mask opposite of expected + umulicc gr7,1,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0x0b,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_icc 0x0a,0 ; Set mask opposite of expected + umulicc gr7,0,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_icc 0x0f,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x0e,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result + set_icc 0x09,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_icc 0x0d,0 ; Set mask opposite of expected + umulicc gr7,0x1ff,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0xff,gr8 + test_gr_limmed 0x7fff,0xfe01,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_icc 0x09,0 ; Set mask opposite of expected + umulicc gr7,-512,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x7fff,0xff00,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0xffff,0xffff,gr7 ; max positive result + set_icc 0x05,0 ; Set mask opposite of expected + umulicc gr7,-1,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xfffe,gr8 + test_gr_immed 1,gr9 + + pass diff --git a/sim/testsuite/sim/frv/xor.cgs b/sim/testsuite/sim/frv/xor.cgs new file mode 100644 index 00000000000..97310e440a7 --- /dev/null +++ b/sim/testsuite/sim/frv/xor.cgs @@ -0,0 +1,38 @@ +# frv testcase for xor $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global xor +xor: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + xor gr7,gr8,gr8 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + xor gr7,gr8,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + xor gr7,gr8,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + xor gr7,gr8,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/xorcc.cgs b/sim/testsuite/sim/frv/xorcc.cgs new file mode 100644 index 00000000000..9516b789153 --- /dev/null +++ b/sim/testsuite/sim/frv/xorcc.cgs @@ -0,0 +1,38 @@ +# frv testcase for xorcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global xorcc +xorcc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + xorcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + xorcc gr7,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + xorcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + xorcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/xorcr.cgs b/sim/testsuite/sim/frv/xorcr.cgs new file mode 100644 index 00000000000..bcb153bc97f --- /dev/null +++ b/sim/testsuite/sim/frv/xorcr.cgs @@ -0,0 +1,59 @@ +# frv testcase for xorcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global xorcr +xorcr: + set_spr_immed 0x1b1b,cccr + xorcr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc7,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc7,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc6,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc6,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc5,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc5,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc5,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + xorcr cc5,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + xorcr cc4,cc7,cc3 + test_spr_immed 0x1bdb,cccr + + xorcr cc4,cc6,cc3 + test_spr_immed 0x1bdb,cccr + + xorcr cc4,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + xorcr cc4,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/sim/frv/xori.cgs b/sim/testsuite/sim/frv/xori.cgs new file mode 100644 index 00000000000..ed26660faf8 --- /dev/null +++ b/sim/testsuite/sim/frv/xori.cgs @@ -0,0 +1,35 @@ +# frv testcase for xori $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global xori +xori: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x07,0 ; Set mask opposite of expected + xori gr7,0x555,gr8 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xaaaa,0xafff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + xori gr7,0,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x0b,0 ; Set mask opposite of expected + xori gr7,0x2aa,gr8 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xa800,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_icc 0x05,0 ; Set mask opposite of expected + xori gr7,-273,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x2152,0xfeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/xoricc.cgs b/sim/testsuite/sim/frv/xoricc.cgs new file mode 100644 index 00000000000..b473620bbf1 --- /dev/null +++ b/sim/testsuite/sim/frv/xoricc.cgs @@ -0,0 +1,36 @@ +# frv testcase for xoricc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global xoricc +xoricc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x07,0 ; Set mask opposite of expected + xoricc gr7,0x155,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xabff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + xoricc gr7,0,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + xoricc gr7,0xaa,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xaa00,gr8 + + set_gr_limmed 0xdead,0xb000,gr7 + set_icc 0x0d,0 ; Set mask opposite of expected + xoricc gr7,-273,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x2152,0x4eef,gr8 + + pass -- 2.30.2