From 4a36a3f164d87fbab8b7058921bffe084993c877 Mon Sep 17 00:00:00 2001 From: Steve Ellcey Date: Wed, 13 Apr 2005 15:57:37 +0000 Subject: [PATCH] re PR target/20924 (inline float divide does not set correct fpu status flags) PR target/20924 * config/ia64/ia64.md (divsf3_internal_lat): Generate frcpa with fpsr 0 instead of fpsr 1. (divsf3_internal_thr): Ditto. (divdf3_internal_lat): Ditto. (divdf3_internal_thr): Ditto. (divxf3_internal_lat): Ditto. (divxf3_internal_thr): Ditto. From-SVN: r98095 --- gcc/ChangeLog | 11 +++++++++++ gcc/config/ia64/ia64.md | 12 ++++++------ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1f484e004f7..4ab243cc703 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2005-04-13 Steve Ellcey + + PR target/20924 + * config/ia64/ia64.md (divsf3_internal_lat): Generate frcpa with + fpsr 0 instead of fpsr 1. + (divsf3_internal_thr): Ditto. + (divdf3_internal_lat): Ditto. + (divdf3_internal_thr): Ditto. + (divxf3_internal_lat): Ditto. + (divxf3_internal_thr): Ditto. + 2005-04-13 Kazu Hirata PR tree-optimization/20913 diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index fc99ce5a91c..485c3ff6023 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -2699,7 +2699,7 @@ [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 5) (const_int 0)) (parallel [(set (match_dup 3) (mult:XF (match_dup 7) (match_dup 6))) (use (const_int 1))])) @@ -2756,7 +2756,7 @@ [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 5) (const_int 0)) (parallel [(set (match_dup 3) (minus:XF (match_dup 10) @@ -3182,7 +3182,7 @@ [(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9))) (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 6) (const_int 0)) (parallel [(set (match_dup 3) (mult:XF (match_dup 8) (match_dup 7))) (use (const_int 1))])) @@ -3262,7 +3262,7 @@ [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 5) (const_int 0)) (parallel [(set (match_dup 3) (minus:XF (match_dup 10) @@ -3847,7 +3847,7 @@ [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 7) (const_int 0)) (parallel [(set (match_dup 3) (minus:XF (match_dup 8) @@ -3925,7 +3925,7 @@ [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 5) (const_int 0)) (parallel [(set (match_dup 3) (minus:XF (match_dup 6) -- 2.30.2