From 4a3e3e228280ebbd6320743c1bc2f1401e70300c Mon Sep 17 00:00:00 2001 From: Przemyslaw Wirkus Date: Mon, 9 Nov 2020 11:30:22 +0000 Subject: [PATCH] aarch64: Update LS64 feature with system register This patch: + Adds new ACCDATA_EL1 (Accelerator Data) system register, see [0]. + Adds LS64 instruction tests. + Update LS64 feature test with new register. + Fix comment for AARCH64_OPND_Rt_LS64. [0] https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/accdata_el1 Note: as this is register only extension we do not want to hide these registers behind -march flag going forward (they should be enabled by default). --- gas/ChangeLog | 6 ++++ gas/config/tc-aarch64.c | 3 +- gas/testsuite/gas/aarch64/ls64.d | 58 ++++++++++++++++++++++++++++++++ gas/testsuite/gas/aarch64/ls64.s | 5 +++ opcodes/ChangeLog | 4 +++ opcodes/aarch64-opc.c | 2 ++ 6 files changed, 77 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/aarch64/ls64.d diff --git a/gas/ChangeLog b/gas/ChangeLog index d14bcc6d031..3c3ce6e6a7b 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2020-11-09 Przemyslaw Wirkus + + * config/tc-aarch64.c: Fix comment. + * testsuite/gas/aarch64/ls64.d: New test. + * testsuite/gas/aarch64/ls64.s: Test for ACCDATA_EL1 register. + 2020-11-09 Przemyslaw Wirkus * config/tc-aarch64.c (process_omitted_operand): Add AARCH64_OPND_Rt_LS64. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 4308ea62663..9ae07276989 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -5652,7 +5652,8 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Rm: po_int_reg_or_fail (REG_TYPE_R_Z); - /* In LS64 load/store instructions Rt register number is . */ + /* In LS64 load/store instructions Rt register number must be even + and <=22. */ if (operands[i] == AARCH64_OPND_Rt_LS64) { /* We've already checked if this is valid register. diff --git a/gas/testsuite/gas/aarch64/ls64.d b/gas/testsuite/gas/aarch64/ls64.d new file mode 100644 index 00000000000..0adcbfd2747 --- /dev/null +++ b/gas/testsuite/gas/aarch64/ls64.d @@ -0,0 +1,58 @@ +#name: LS64 instructions and system register +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: +.*: f83fd020 ld64b x0, \[x1\] +.*: f83fd022 ld64b x2, \[x1\] +.*: f83fd024 ld64b x4, \[x1\] +.*: f83fd026 ld64b x6, \[x1\] +.*: f83fd028 ld64b x8, \[x1\] +.*: f83fd02a ld64b x10, \[x1\] +.*: f83fd02c ld64b x12, \[x1\] +.*: f83fd02e ld64b x14, \[x1\] +.*: f83fd030 ld64b x16, \[x1\] +.*: f83fd032 ld64b x18, \[x1\] +.*: f83fd034 ld64b x20, \[x1\] +.*: f83fd036 ld64b x22, \[x1\] +.*: f83f9020 st64b x0, \[x1\] +.*: f83f9022 st64b x2, \[x1\] +.*: f83f9024 st64b x4, \[x1\] +.*: f83f9026 st64b x6, \[x1\] +.*: f83f9028 st64b x8, \[x1\] +.*: f83f902a st64b x10, \[x1\] +.*: f83f902c st64b x12, \[x1\] +.*: f83f902e st64b x14, \[x1\] +.*: f83f9030 st64b x16, \[x1\] +.*: f83f9032 st64b x18, \[x1\] +.*: f83f9034 st64b x20, \[x1\] +.*: f83f9036 st64b x22, \[x1\] +.*: f821b040 st64bv x1, x0, \[x2\] +.*: f820b042 st64bv x0, x2, \[x2\] +.*: f820b044 st64bv x0, x4, \[x2\] +.*: f820b046 st64bv x0, x6, \[x2\] +.*: f820b048 st64bv x0, x8, \[x2\] +.*: f820b04a st64bv x0, x10, \[x2\] +.*: f820b04c st64bv x0, x12, \[x2\] +.*: f820b04e st64bv x0, x14, \[x2\] +.*: f820b050 st64bv x0, x16, \[x2\] +.*: f820b052 st64bv x0, x18, \[x2\] +.*: f820b054 st64bv x0, x20, \[x2\] +.*: f820b056 st64bv x0, x22, \[x2\] +.*: f821a040 st64bv0 x1, x0, \[x2\] +.*: f820a042 st64bv0 x0, x2, \[x2\] +.*: f820a044 st64bv0 x0, x4, \[x2\] +.*: f820a046 st64bv0 x0, x6, \[x2\] +.*: f820a048 st64bv0 x0, x8, \[x2\] +.*: f820a04a st64bv0 x0, x10, \[x2\] +.*: f820a04c st64bv0 x0, x12, \[x2\] +.*: f820a04e st64bv0 x0, x14, \[x2\] +.*: f820a050 st64bv0 x0, x16, \[x2\] +.*: f820a052 st64bv0 x0, x18, \[x2\] +.*: f820a054 st64bv0 x0, x20, \[x2\] +.*: f820a056 st64bv0 x0, x22, \[x2\] +.*: d538d0a0 mrs x0, accdata_el1 +.*: d518d0a0 msr accdata_el1, x0 diff --git a/gas/testsuite/gas/aarch64/ls64.s b/gas/testsuite/gas/aarch64/ls64.s index d9219249f67..eb1607d0d26 100644 --- a/gas/testsuite/gas/aarch64/ls64.s +++ b/gas/testsuite/gas/aarch64/ls64.s @@ -56,3 +56,8 @@ st64bv0 x0, x18, [x2] st64bv0 x0, x20, [x2] st64bv0 x0, x22, [x2] + +.arch armv8-a +/* Accelerator Data system register. */ + mrs x0, accdata_el1 + msr accdata_el1, x0 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index c90438c1f0d..34b2b62d51f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2020-11-09 Przemyslaw Wirkus + + * aarch64-opc.c: Add ACCDATA_EL1 system register + 2020-11-09 Przemyslaw Wirkus * aarch64-opc.c (aarch64_print_operand): Support operand AARCH64_OPND_Rt_LS64 diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 67429e97206..0a01de77159 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4680,6 +4680,8 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("brbinf30_el1", CPENC (2,1,C8,C14,4), F_REG_READ), SR_CORE ("brbinf31_el1", CPENC (2,1,C8,C15,4), F_REG_READ), + SR_CORE ("accdata_el1", CPENC (3,0,C13,C0,5), 0), + { 0, CPENC (0,0,0,0,0), 0, 0 } }; -- 2.30.2