From 4a4b7da141834c6bcdbab7da7dd8599fab400b04 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Wed, 27 Jul 2016 19:14:41 +0200 Subject: [PATCH] amdgpu/addrlib: Fix invalid access to m_tileTable Sometimes client driver passes valid tile info into address library, in this case, the tile index is computed in function HwlPostCheckTileIndex instead of CiAddrLib::HwlSetupTileCfg. We need to call HwlPostCheckTileIndex to calculate the correct tile index to get tile split bytes for this case. --- src/amd/addrlib/r800/ciaddrlib.cpp | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp index 57416dced16..ccb05282647 100644 --- a/src/amd/addrlib/r800/ciaddrlib.cpp +++ b/src/amd/addrlib/r800/ciaddrlib.cpp @@ -1277,14 +1277,25 @@ VOID CiAddrLib::HwlSetupTileInfo( { if (IsMacroTiled(tileMode)) { - // Non-depth entries store a split factor - UINT_32 sampleSplit = m_tileTable[pOut->tileIndex].info.tileSplitBytes; - UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness); - UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x); + UINT_32 tileIndex = static_cast(pOut->tileIndex); - if (m_rowSize < colorTileSplit) + if ((tileIndex == TileIndexInvalid) && (IsTileInfoAllZero(pTileInfo) == FALSE)) { - pOut->tcCompatible = FALSE; + tileIndex = HwlPostCheckTileIndex(pTileInfo, tileMode, inTileType, tileIndex); + } + + if (tileIndex != TileIndexInvalid) + { + ADDR_ASSERT(tileIndex < TileTableSize); + // Non-depth entries store a split factor + UINT_32 sampleSplit = m_tileTable[tileIndex].info.tileSplitBytes; + UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness); + UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x); + + if (m_rowSize < colorTileSplit) + { + pOut->tcCompatible = FALSE; + } } } else -- 2.30.2