From 4a4e82b5f64649fd459ce816c6edf391412ea5ce Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 11 Feb 2015 20:54:32 +0100
Subject: [PATCH] etherbone: wishbone writes seems OK in simulation

---
 liteeth/core/etherbone/__init__.py |  1 -
 liteeth/core/etherbone/packet.py   |  2 ++
 liteeth/core/etherbone/record.py   |  8 +++++---
 liteeth/test/etherbone_tb.py       | 32 +++++++++++++++++++++++++++++-
 liteeth/test/model/etherbone.py    |  6 ++++--
 5 files changed, 42 insertions(+), 7 deletions(-)

diff --git a/liteeth/core/etherbone/__init__.py b/liteeth/core/etherbone/__init__.py
index b92c23c2..9930eda2 100644
--- a/liteeth/core/etherbone/__init__.py
+++ b/liteeth/core/etherbone/__init__.py
@@ -28,4 +28,3 @@ class LiteEthEtherbone(Module):
 			Record.connect(wishbone.wr_source, record.sender.wr_sink),
 			Record.connect(wishbone.rd_source, record.sender.rd_sink)
 		]
-
diff --git a/liteeth/core/etherbone/packet.py b/liteeth/core/etherbone/packet.py
index 872e8875..e98a6429 100644
--- a/liteeth/core/etherbone/packet.py
+++ b/liteeth/core/etherbone/packet.py
@@ -95,6 +95,8 @@ class LiteEthEtherbonePacketRX(Module):
 			source.pr.eq(depacketizer.source.pr),
 			source.nr.eq(depacketizer.source.nr),
 
+			source.data.eq(depacketizer.source.data),
+
 			source.src_port.eq(sink.src_port),
 			source.dst_port.eq(sink.dst_port),
 			source.ip_address.eq(sink.ip_address),
diff --git a/liteeth/core/etherbone/record.py b/liteeth/core/etherbone/record.py
index ce3e6807..6c3acb0e 100644
--- a/liteeth/core/etherbone/record.py
+++ b/liteeth/core/etherbone/record.py
@@ -37,7 +37,7 @@ class LiteEthEtherboneRecordReceiver(Module):
 			If(sink.stb & sink.sop,
 				base_addr.ce.eq(1),
 				If(sink.wcount,
-					NextState("RECEIVE_READS")
+					NextState("RECEIVE_WRITES")
 				).Elif(sink.rcount,
 					NextState("RECEIVE_READS")
 				)
@@ -139,12 +139,14 @@ class LiteEthEtherboneRecord(Module):
 		self.submodules.receiver = receiver =  LiteEthEtherboneRecordReceiver()
 		self.comb += [
 			Record.connect(sink, depacketizer.sink),
-			Record.connect(depacketizer.source, receiver.sink)
+			Record.connect(depacketizer.source, receiver.sink),
+			receiver.sink.data.eq(reverse_bytes(depacketizer.source.data)) # clarify this
 		]
 
 		self.submodules.sender = sender =  LiteEthEtherboneRecordSender()
 		self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer()
 		self.comb += [
 			Record.connect(sender.source, packetizer.sink),
-			Record.connect(packetizer.source, source)
+			packetizer.sink.data.eq(reverse_bytes(sender.source.data)), # clarify this
+			Record.connect(packetizer.source, source),
 		]
diff --git a/liteeth/test/etherbone_tb.py b/liteeth/test/etherbone_tb.py
index 160189f8..1987e29a 100644
--- a/liteeth/test/etherbone_tb.py
+++ b/liteeth/test/etherbone_tb.py
@@ -25,6 +25,11 @@ class TB(Module):
 		self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
 		self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000)
 
+		self.submodules.sram = wishbone.SRAM(1024)
+		self.submodules.interconnect = wishbone.InterconnectPointToPoint(self.etherbone.wishbone.bus, self.sram.bus)
+
+
+
 		# use sys_clk for each clock_domain
 		self.clock_domains.cd_eth_rx = ClockDomain()
 		self.clock_domains.cd_eth_tx = ClockDomain()
@@ -46,9 +51,34 @@ class TB(Module):
 			yield
 
 		# test probe
+		#packet = etherbone.EtherbonePacket()
+		#packet.pf = 1
+		#self.etherbone_model.send(packet)
+
+		# test writes
+		writes = etherbone.EtherboneWrites(base_addr=0x1000)
+		for i in range(16):
+			writes.add(etherbone.EtherboneWrite(i))
+		record = etherbone.EtherboneRecord()
+		record.writes = writes
+		record.reads = None
+		record.bca = 0
+		record.rca = 0
+		record.rff = 0
+		record.cyc = 0
+		record.wca = 0
+		record.wff = 0
+		record.byte_enable = 0
+		record.wcount = 16
+		record.rcount = 0
+
 		packet = etherbone.EtherbonePacket()
-		packet.pf = 1
+		packet.records = [record]
+		print(packet)
+
 		self.etherbone_model.send(packet)
 
+
+
 if __name__ == "__main__":
 	run_simulation(TB(), ncycles=1024, vcd_name="my.vcd", keep_files=True)
\ No newline at end of file
diff --git a/liteeth/test/model/etherbone.py b/liteeth/test/model/etherbone.py
index 9cf7b33f..b4b3626f 100644
--- a/liteeth/test/model/etherbone.py
+++ b/liteeth/test/model/etherbone.py
@@ -163,8 +163,10 @@ class EtherboneRecord(Packet):
 	def encode(self):
 		if self.encoded:
 			raise ValueError
-		self.set_writes(self.writes)
-		self.set_reads(self.reads)
+		if self.writes is not None:
+			self.set_writes(self.writes)
+		if self.reads is not None:
+			self.set_reads(self.reads)
 		header = 0
 		for k, v in sorted(etherbone_record_header.items()):
 			value = merge_bytes(split_bytes(getattr(self, k), math.ceil(v.width/8)), "little")
-- 
2.30.2