From 4a5e779b5f9d169fd043ffaead1525040af816f3 Mon Sep 17 00:00:00 2001 From: Julien Isorce Date: Thu, 23 Mar 2017 13:43:49 +0000 Subject: [PATCH] si_compute: check NULL return from u_upload_alloc MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Julien Isorce Reviewed-by: Marek Olšák --- src/gallium/drivers/radeonsi/si_compute.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index 46476b68beb..913a2ddbfe6 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -579,7 +579,7 @@ static void si_setup_user_sgprs_co_v2(struct si_context *sctx, } } -static void si_upload_compute_input(struct si_context *sctx, +static bool si_upload_compute_input(struct si_context *sctx, const amd_kernel_code_t *code_object, const struct pipe_grid_info *info) { @@ -602,6 +602,9 @@ static void si_upload_compute_input(struct si_context *sctx, &kernel_args_offset, (struct pipe_resource**)&input_buffer, &kernel_args_ptr); + if (unlikely(!kernel_args_ptr)) + return false; + kernel_args = (uint32_t*)kernel_args_ptr; kernel_args_va = input_buffer->gpu_address + kernel_args_offset; @@ -636,6 +639,8 @@ static void si_upload_compute_input(struct si_context *sctx, } r600_resource_reference(&input_buffer, NULL); + + return true; } static void si_setup_tgsi_grid(struct si_context *sctx, @@ -790,8 +795,11 @@ static void si_launch_grid( si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false); } - if (program->input_size || program->ir_type == PIPE_SHADER_IR_NATIVE) - si_upload_compute_input(sctx, code_object, info); + if ((program->input_size || + program->ir_type == PIPE_SHADER_IR_NATIVE) && + unlikely(!si_upload_compute_input(sctx, code_object, info))) { + return; + } /* Global buffers */ for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) { -- 2.30.2