From 4a60b0c8d2e4890038e1c6a72a7dac3b4cdf996e Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 9 Jun 2011 09:28:19 -0700 Subject: [PATCH] intel: Add block alignment for RGTC textures. We were using the default 4x2 alignment instead of the 4x4 required for RGTC textures. --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 2 +- .../drivers/dri/intel/intel_mipmap_tree.c | 6 +-- src/mesa/drivers/dri/intel/intel_tex_layout.c | 39 +++++++------------ src/mesa/drivers/dri/intel/intel_tex_layout.h | 3 +- 4 files changed, 18 insertions(+), 32 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index 4a3a2bfada2..f462f32b19a 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -88,7 +88,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel, GLuint align_w = 4; mt->total_height = 0; - intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h); + intel_get_texture_alignment_unit(mt->format, &align_w, &align_h); if (mt->compressed) { mt->total_width = ALIGN(width, align_w); diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index a96398cc5de..c8ad1a7d34d 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -402,8 +402,7 @@ intel_miptree_image_data(struct intel_context *intel, if (dst->compressed) { unsigned int align_w, align_h; - intel_get_texture_alignment_unit(dst->internal_format, - &align_w, &align_h); + intel_get_texture_alignment_unit(dst->format, &align_w, &align_h); height = (height + align_h - 1) / align_h; width = ALIGN(width, align_w); } @@ -445,8 +444,7 @@ intel_miptree_image_copy(struct intel_context *intel, if (dst->compressed) { GLuint align_w, align_h; - intel_get_texture_alignment_unit(dst->internal_format, - &align_w, &align_h); + intel_get_texture_alignment_unit(dst->format, &align_w, &align_h); height = (height + 3) / 4; width = ALIGN(width, align_w); } diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c b/src/mesa/drivers/dri/intel/intel_tex_layout.c index d39733b6c5a..32c34dad2b1 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_layout.c +++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c @@ -35,32 +35,19 @@ #include "intel_context.h" #include "main/macros.h" -void intel_get_texture_alignment_unit(GLenum internalFormat, GLuint *w, GLuint *h) +void +intel_get_texture_alignment_unit(gl_format format, + unsigned int *w, unsigned int *h) { - switch (internalFormat) { - case GL_COMPRESSED_RGB_FXT1_3DFX: - case GL_COMPRESSED_RGBA_FXT1_3DFX: - *w = 8; - *h = 4; - break; - - case GL_RGB_S3TC: - case GL_RGB4_S3TC: - case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - case GL_RGBA_S3TC: - case GL_RGBA4_S3TC: - case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - *w = 4; - *h = 4; - break; - - default: - *w = 4; - *h = 2; - break; - } + if (_mesa_is_format_compressed(format)) { + /* The hardware alignment requirements for compressed textures + * happen to match the block boundaries. + */ + _mesa_get_format_block_size(format, w, h); + } else { + *w = 4; + *h = 2; + } } void i945_miptree_layout_2d(struct intel_context *intel, @@ -75,7 +62,7 @@ void i945_miptree_layout_2d(struct intel_context *intel, GLuint height = mt->height0; mt->total_width = mt->width0; - intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h); + intel_get_texture_alignment_unit(mt->format, &align_w, &align_h); if (mt->compressed) { mt->total_width = ALIGN(mt->width0, align_w); diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.h b/src/mesa/drivers/dri/intel/intel_tex_layout.h index 1c8c53e5459..b52e5a48855 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_layout.h +++ b/src/mesa/drivers/dri/intel/intel_tex_layout.h @@ -41,4 +41,5 @@ static INLINE GLuint minify( GLuint d ) extern void i945_miptree_layout_2d(struct intel_context *intel, struct intel_mipmap_tree *mt, uint32_t tiling, int nr_images); -extern void intel_get_texture_alignment_unit(GLenum, GLuint *, GLuint *); +void intel_get_texture_alignment_unit(gl_format format, + unsigned int *w, unsigned int *h); -- 2.30.2