From 4a644767c58754339965cecc5d85853255652a30 Mon Sep 17 00:00:00 2001
From: Nathan Binkert <nate@binkert.org>
Date: Wed, 9 May 2012 11:52:14 -0700
Subject: [PATCH] stats: update stats for no_value -> nan Lots of accumulated
 older changes too.

---
 .../alpha/linux/tsunami-o3-dual/config.ini    |  112 +-
 .../ref/alpha/linux/tsunami-o3-dual/simout    |    9 +-
 .../ref/alpha/linux/tsunami-o3-dual/stats.txt |   44 +-
 .../ref/alpha/linux/tsunami-o3/config.ini     |  104 +-
 .../ref/alpha/linux/tsunami-o3/simout         |    9 +-
 .../ref/alpha/linux/tsunami-o3/stats.txt      |   36 +-
 .../arm/linux/realview-o3-checker/config.ini  |   16 +-
 .../ref/arm/linux/realview-o3-checker/simout  |   10 +-
 .../arm/linux/realview-o3-checker/stats.txt   |   40 +-
 .../ref/arm/linux/realview-o3-dual/config.ini |   16 +-
 .../ref/arm/linux/realview-o3-dual/simout     |   10 +-
 .../ref/arm/linux/realview-o3-dual/stats.txt  |   42 +-
 .../ref/arm/linux/realview-o3-dual/status     |    2 +-
 .../linux/realview-o3-dual/system.terminal    |  Bin 6036 -> 6036 bytes
 .../ref/arm/linux/realview-o3/config.ini      |   16 +-
 .../ref/arm/linux/realview-o3/simout          |   10 +-
 .../ref/arm/linux/realview-o3/stats.txt       |   40 +-
 .../ref/x86/linux/pc-o3-timing/simout         |    6 +-
 .../ref/x86/linux/pc-o3-timing/stats.txt      |   28 +-
 .../config.ini                                |    6 +-
 .../ruby.stats                                |   34 +-
 .../simout                                    |   11 +-
 .../stats.txt                                 |   10 +-
 .../solaris/t1000-simple-atomic/config.ini    |   90 +-
 .../sparc/solaris/t1000-simple-atomic/simout  |   13 +-
 .../solaris/t1000-simple-atomic/stats.txt     |   62 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |   33 +-
 .../ref/alpha/tru64/inorder-timing/simout     |    8 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |   62 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |   31 +-
 .../00.gzip/ref/alpha/tru64/o3-timing/simout  |    8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |   16 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |   19 +-
 .../ref/alpha/tru64/simple-atomic/simout      |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   10 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |   31 +-
 .../ref/alpha/tru64/simple-timing/simout      |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   22 +-
 .../ref/arm/linux/o3-timing/config.ini        |    9 +-
 .../se/00.gzip/ref/arm/linux/o3-timing/simout |    8 +-
 .../00.gzip/ref/arm/linux/o3-timing/stats.txt |   18 +-
 .../ref/arm/linux/simple-atomic/config.ini    |   10 +-
 .../ref/arm/linux/simple-atomic/simout        |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |    9 +-
 .../ref/arm/linux/simple-timing/simout        |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   22 +-
 .../ref/sparc/linux/o3-timing/config.ini      |   31 +-
 .../00.gzip/ref/sparc/linux/o3-timing/simout  |    8 +-
 .../ref/sparc/linux/o3-timing/stats.txt       |   20 +-
 .../ref/sparc/linux/simple-atomic/config.ini  |   19 +-
 .../ref/sparc/linux/simple-atomic/simout      |    8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   10 +-
 .../ref/sparc/linux/simple-timing/config.ini  |   31 +-
 .../ref/sparc/linux/simple-timing/simout      |    8 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   22 +-
 .../ref/x86/linux/o3-timing/config.ini        |   40 +-
 .../se/00.gzip/ref/x86/linux/o3-timing/simout |    8 +-
 .../00.gzip/ref/x86/linux/o3-timing/stats.txt |   22 +-
 .../ref/x86/linux/simple-atomic/config.ini    |   28 +-
 .../ref/x86/linux/simple-atomic/simout        |    8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/x86/linux/simple-timing/config.ini    |   40 +-
 .../ref/x86/linux/simple-timing/simout        |    8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   22 +-
 .../10.mcf/ref/arm/linux/o3-timing/config.ini |   11 +-
 .../se/10.mcf/ref/arm/linux/o3-timing/simout  |    8 +-
 .../10.mcf/ref/arm/linux/o3-timing/stats.txt  |   20 +-
 .../ref/arm/linux/simple-atomic/config.ini    |   12 +-
 .../10.mcf/ref/arm/linux/simple-atomic/simout |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |   11 +-
 .../10.mcf/ref/arm/linux/simple-timing/simout |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   22 +-
 .../ref/sparc/linux/simple-atomic/config.ini  |   19 +-
 .../ref/sparc/linux/simple-atomic/simout      |    8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   10 +-
 .../ref/sparc/linux/simple-timing/config.ini  |   31 +-
 .../ref/sparc/linux/simple-timing/simout      |    8 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   22 +-
 .../10.mcf/ref/x86/linux/o3-timing/config.ini |   40 +-
 .../se/10.mcf/ref/x86/linux/o3-timing/simout  |    8 +-
 .../10.mcf/ref/x86/linux/o3-timing/stats.txt  |   22 +-
 .../ref/x86/linux/simple-atomic/config.ini    |   28 +-
 .../10.mcf/ref/x86/linux/simple-atomic/simout |    8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/x86/linux/simple-timing/config.ini    |   40 +-
 .../10.mcf/ref/x86/linux/simple-timing/simout |    8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   22 +-
 .../ref/arm/linux/o3-timing/config.ini        |   11 +-
 .../20.parser/ref/arm/linux/o3-timing/simout  |   10 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1114 ++++++++--------
 .../ref/arm/linux/simple-atomic/config.ini    |   12 +-
 .../ref/arm/linux/simple-atomic/simout        |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |   11 +-
 .../ref/arm/linux/simple-timing/simout        |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   22 +-
 .../ref/x86/linux/o3-timing/config.ini        |   40 +-
 .../20.parser/ref/x86/linux/o3-timing/simout  |    8 +-
 .../ref/x86/linux/o3-timing/stats.txt         |   22 +-
 .../ref/x86/linux/simple-atomic/config.ini    |   28 +-
 .../ref/x86/linux/simple-atomic/simout        |    8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/x86/linux/simple-timing/config.ini    |   40 +-
 .../ref/x86/linux/simple-timing/simout        |    8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   22 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |   33 +-
 .../ref/alpha/tru64/inorder-timing/simout     |    8 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |   66 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |   31 +-
 .../30.eon/ref/alpha/tru64/o3-timing/simout   |    8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |   20 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |   19 +-
 .../ref/alpha/tru64/simple-atomic/simout      |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   10 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |   31 +-
 .../ref/alpha/tru64/simple-timing/simout      |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   22 +-
 .../30.eon/ref/arm/linux/o3-timing/config.ini |    9 +-
 .../se/30.eon/ref/arm/linux/o3-timing/simout  |    8 +-
 .../30.eon/ref/arm/linux/o3-timing/stats.txt  |   20 +-
 .../ref/arm/linux/simple-atomic/config.ini    |   10 +-
 .../30.eon/ref/arm/linux/simple-atomic/simout |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |    9 +-
 .../30.eon/ref/arm/linux/simple-timing/simout |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   22 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |   31 +-
 .../ref/alpha/tru64/o3-timing/simout          |    8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |   16 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |   19 +-
 .../ref/alpha/tru64/simple-atomic/simout      |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   10 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |   31 +-
 .../ref/alpha/tru64/simple-timing/simout      |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   22 +-
 .../ref/arm/linux/o3-timing/config.ini        |    9 +-
 .../40.perlbmk/ref/arm/linux/o3-timing/simout |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         |   20 +-
 .../ref/arm/linux/simple-atomic/config.ini    |   10 +-
 .../ref/arm/linux/simple-atomic/simout        |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |    9 +-
 .../ref/arm/linux/simple-timing/simout        |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   22 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |   33 +-
 .../ref/alpha/tru64/inorder-timing/simout     |    8 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |   66 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |   31 +-
 .../ref/alpha/tru64/o3-timing/simout          |    8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |   18 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |   19 +-
 .../ref/alpha/tru64/simple-atomic/simout      |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   10 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |   31 +-
 .../ref/alpha/tru64/simple-timing/simout      |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   22 +-
 .../ref/arm/linux/o3-timing/config.ini        |    9 +-
 .../50.vortex/ref/arm/linux/o3-timing/simout  |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         |   20 +-
 .../ref/arm/linux/simple-atomic/config.ini    |   10 +-
 .../ref/arm/linux/simple-atomic/simout        |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |    9 +-
 .../ref/arm/linux/simple-timing/simout        |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   22 +-
 .../ref/sparc/linux/simple-atomic/config.ini  |   19 +-
 .../ref/sparc/linux/simple-atomic/simout      |    8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   10 +-
 .../ref/sparc/linux/simple-timing/config.ini  |   31 +-
 .../ref/sparc/linux/simple-timing/simout      |    8 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   22 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |   33 +-
 .../ref/alpha/tru64/inorder-timing/simout     |    8 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |   62 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |   31 +-
 .../60.bzip2/ref/alpha/tru64/o3-timing/simout |    8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |   16 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |   19 +-
 .../ref/alpha/tru64/simple-atomic/simout      |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   10 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |   31 +-
 .../ref/alpha/tru64/simple-timing/simout      |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   22 +-
 .../ref/arm/linux/o3-timing/config.ini        |    9 +-
 .../60.bzip2/ref/arm/linux/o3-timing/simout   |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         |   16 +-
 .../ref/arm/linux/simple-atomic/config.ini    |   10 +-
 .../ref/arm/linux/simple-atomic/simout        |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |    9 +-
 .../ref/arm/linux/simple-timing/simout        |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   22 +-
 .../ref/x86/linux/simple-atomic/config.ini    |   28 +-
 .../ref/x86/linux/simple-atomic/simout        |    8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/x86/linux/simple-timing/config.ini    |   40 +-
 .../ref/x86/linux/simple-timing/simout        |    8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   22 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |   33 +-
 .../ref/alpha/tru64/inorder-timing/simout     |   12 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |   66 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |   31 +-
 .../70.twolf/ref/alpha/tru64/o3-timing/simout |   12 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |   18 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |   19 +-
 .../ref/alpha/tru64/simple-atomic/simout      |   10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   10 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |   31 +-
 .../ref/alpha/tru64/simple-timing/simout      |   10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   22 +-
 .../ref/arm/linux/o3-timing/config.ini        |    9 +-
 .../70.twolf/ref/arm/linux/o3-timing/simout   |   10 +-
 .../ref/arm/linux/o3-timing/stats.txt         |   20 +-
 .../ref/arm/linux/simple-atomic/config.ini    |   10 +-
 .../ref/arm/linux/simple-atomic/simout        |   10 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |    9 +-
 .../ref/arm/linux/simple-timing/simout        |   10 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   22 +-
 .../ref/sparc/linux/simple-atomic/config.ini  |   19 +-
 .../ref/sparc/linux/simple-atomic/simout      |   10 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   10 +-
 .../ref/sparc/linux/simple-timing/config.ini  |   31 +-
 .../ref/sparc/linux/simple-timing/simout      |   10 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   22 +-
 .../ref/x86/linux/o3-timing/config.ini        |   40 +-
 .../70.twolf/ref/x86/linux/o3-timing/simout   |   12 +-
 .../ref/x86/linux/o3-timing/stats.txt         |   22 +-
 .../ref/x86/linux/simple-atomic/config.ini    |   28 +-
 .../ref/x86/linux/simple-atomic/simout        |   10 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/x86/linux/simple-timing/config.ini    |   40 +-
 .../ref/x86/linux/simple-timing/simout        |   10 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   22 +-
 .../tsunami-simple-atomic-dual/config.ini     |  114 +-
 .../linux/tsunami-simple-atomic-dual/simout   |    9 +-
 .../tsunami-simple-atomic-dual/stats.txt      |   56 +-
 .../linux/tsunami-simple-atomic/config.ini    |  105 +-
 .../alpha/linux/tsunami-simple-atomic/simout  |    9 +-
 .../linux/tsunami-simple-atomic/stats.txt     |   44 +-
 .../tsunami-simple-timing-dual/config.ini     |  112 +-
 .../linux/tsunami-simple-timing-dual/simout   |    9 +-
 .../tsunami-simple-timing-dual/stats.txt      |   54 +-
 .../linux/tsunami-simple-timing/config.ini    |  104 +-
 .../alpha/linux/tsunami-simple-timing/simout  |    9 +-
 .../linux/tsunami-simple-timing/stats.txt     |   42 +-
 .../realview-simple-atomic-dual/config.ini    |   18 +-
 .../linux/realview-simple-atomic-dual/simout  |   10 +-
 .../realview-simple-atomic-dual/stats.txt     |   54 +-
 .../linux/realview-simple-atomic-dual/status  |    2 +-
 .../linux/realview-simple-atomic/config.ini   |   17 +-
 .../arm/linux/realview-simple-atomic/simout   |   10 +-
 .../linux/realview-simple-atomic/stats.txt    |   46 +-
 .../arm/linux/realview-simple-atomic/status   |    2 +-
 .../realview-simple-timing-dual/config.ini    |   16 +-
 .../linux/realview-simple-timing-dual/simout  |   10 +-
 .../realview-simple-timing-dual/stats.txt     |   54 +-
 .../linux/realview-simple-timing-dual/status  |    2 +-
 .../linux/realview-simple-timing/config.ini   |   16 +-
 .../arm/linux/realview-simple-timing/simout   |   10 +-
 .../linux/realview-simple-timing/stats.txt    |   46 +-
 .../arm/linux/realview-simple-timing/status   |    2 +-
 .../ref/x86/linux/pc-simple-atomic/config.ini |   98 +-
 .../ref/x86/linux/pc-simple-atomic/simout     |    9 +-
 .../ref/x86/linux/pc-simple-atomic/stats.txt  |   34 +-
 .../ref/x86/linux/pc-simple-timing/config.ini |   97 +-
 .../ref/x86/linux/pc-simple-timing/simout     |    9 +-
 .../ref/x86/linux/pc-simple-timing/stats.txt  |   32 +-
 .../twosys-tsunami-simple-atomic/config.ini   |  184 +--
 .../linux/twosys-tsunami-simple-atomic/simout |   10 +-
 .../twosys-tsunami-simple-atomic/stats.txt    |   70 +-
 .../ref/alpha/linux/inorder-timing/config.ini |   31 +-
 .../ref/alpha/linux/inorder-timing/simout     |    8 +-
 .../ref/alpha/linux/inorder-timing/stats.txt  |   68 +-
 .../ref/alpha/linux/o3-timing/config.ini      |   29 +-
 .../00.hello/ref/alpha/linux/o3-timing/simout |    8 +-
 .../ref/alpha/linux/o3-timing/stats.txt       |   22 +-
 .../ref/alpha/linux/simple-atomic/config.ini  |   17 +-
 .../ref/alpha/linux/simple-atomic/simout      |    8 +-
 .../ref/alpha/linux/simple-atomic/stats.txt   |   10 +-
 .../config.ini                                |   28 +-
 .../ruby.stats                                |   31 +-
 .../simout                                    |    6 +-
 .../stats.txt                                 |   10 +-
 .../config.ini                                |   26 +-
 .../ruby.stats                                |   30 +-
 .../simout                                    |    8 +-
 .../stats.txt                                 |   10 +-
 .../config.ini                                |   26 +-
 .../ruby.stats                                |   32 +-
 .../simple-timing-ruby-MOESI_CMP_token/simout |    8 +-
 .../stats.txt                                 |    8 +-
 .../config.ini                                |   26 +-
 .../ruby.stats                                |   32 +-
 .../simple-timing-ruby-MOESI_hammer/simout    |    8 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt |   10 +-
 .../alpha/linux/simple-timing-ruby/config.ini |   26 +-
 .../alpha/linux/simple-timing-ruby/ruby.stats |   22 +-
 .../ref/alpha/linux/simple-timing-ruby/simout |    8 +-
 .../alpha/linux/simple-timing-ruby/stats.txt  |   10 +-
 .../ref/alpha/linux/simple-timing/config.ini  |   29 +-
 .../ref/alpha/linux/simple-timing/simout      |    8 +-
 .../ref/alpha/linux/simple-timing/stats.txt   |   22 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |   29 +-
 .../00.hello/ref/alpha/tru64/o3-timing/simout |    8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |   22 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |   17 +-
 .../ref/alpha/tru64/simple-atomic/simout      |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   10 +-
 .../config.ini                                |   28 +-
 .../ruby.stats                                |   21 +-
 .../simout                                    |    6 +-
 .../stats.txt                                 |   10 +-
 .../config.ini                                |   26 +-
 .../ruby.stats                                |   24 +-
 .../simout                                    |    8 +-
 .../stats.txt                                 |   10 +-
 .../config.ini                                |   26 +-
 .../ruby.stats                                |   32 +-
 .../simple-timing-ruby-MOESI_CMP_token/simout |    8 +-
 .../stats.txt                                 |   10 +-
 .../config.ini                                |   26 +-
 .../ruby.stats                                |   22 +-
 .../simple-timing-ruby-MOESI_hammer/simout    |    8 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt |    8 +-
 .../alpha/tru64/simple-timing-ruby/config.ini |   26 +-
 .../alpha/tru64/simple-timing-ruby/ruby.stats |   18 +-
 .../ref/alpha/tru64/simple-timing-ruby/simout |    8 +-
 .../alpha/tru64/simple-timing-ruby/stats.txt  |   10 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |   29 +-
 .../ref/alpha/tru64/simple-timing/simout      |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   20 +-
 .../arm/linux/o3-timing-checker/config.ini    |    7 +-
 .../ref/arm/linux/o3-timing-checker/simout    |    8 +-
 .../ref/arm/linux/o3-timing-checker/stats.txt |   22 +-
 .../ref/arm/linux/o3-timing/config.ini        |    7 +-
 .../00.hello/ref/arm/linux/o3-timing/simout   |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         |   22 +-
 .../simple-atomic-dummychecker/config.ini     |    8 +-
 .../linux/simple-atomic-dummychecker/simout   |    8 +-
 .../simple-atomic-dummychecker/stats.txt      |   10 +-
 .../ref/arm/linux/simple-atomic/config.ini    |    8 +-
 .../ref/arm/linux/simple-atomic/simout        |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |    7 +-
 .../ref/arm/linux/simple-timing/simout        |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   20 +-
 .../ref/mips/linux/inorder-timing/config.ini  |   31 +-
 .../ref/mips/linux/inorder-timing/simout      |    8 +-
 .../ref/mips/linux/inorder-timing/stats.txt   |   66 +-
 .../ref/mips/linux/o3-timing/config.ini       |   29 +-
 .../00.hello/ref/mips/linux/o3-timing/simout  |    8 +-
 .../ref/mips/linux/o3-timing/stats.txt        |   22 +-
 .../ref/mips/linux/simple-atomic/config.ini   |   17 +-
 .../ref/mips/linux/simple-atomic/simout       |    8 +-
 .../ref/mips/linux/simple-atomic/stats.txt    |    8 +-
 .../mips/linux/simple-timing-ruby/config.ini  |   26 +-
 .../ref/mips/linux/simple-timing-ruby/simout  |    8 +-
 .../mips/linux/simple-timing-ruby/stats.txt   |   10 +-
 .../ref/mips/linux/simple-timing/config.ini   |   29 +-
 .../ref/mips/linux/simple-timing/simout       |    8 +-
 .../ref/mips/linux/simple-timing/stats.txt    |   22 +-
 .../ref/power/linux/o3-timing/config.ini      |   29 +-
 .../00.hello/ref/power/linux/o3-timing/simout |    8 +-
 .../ref/power/linux/o3-timing/stats.txt       |   22 +-
 .../ref/power/linux/simple-atomic/config.ini  |   17 +-
 .../ref/power/linux/simple-atomic/simout      |    8 +-
 .../ref/power/linux/simple-atomic/stats.txt   |    8 +-
 .../ref/sparc/linux/inorder-timing/config.ini |   31 +-
 .../ref/sparc/linux/inorder-timing/simout     |    8 +-
 .../ref/sparc/linux/inorder-timing/stats.txt  |   66 +-
 .../ref/sparc/linux/simple-atomic/config.ini  |   17 +-
 .../ref/sparc/linux/simple-atomic/simout      |    8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |    8 +-
 .../sparc/linux/simple-timing-ruby/config.ini |   26 +-
 .../sparc/linux/simple-timing-ruby/ruby.stats |   22 +-
 .../ref/sparc/linux/simple-timing-ruby/simout |    8 +-
 .../sparc/linux/simple-timing-ruby/stats.txt  |   10 +-
 .../ref/sparc/linux/simple-timing/config.ini  |   29 +-
 .../ref/sparc/linux/simple-timing/simout      |    8 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   22 +-
 .../ref/x86/linux/o3-timing/config.ini        |   38 +-
 .../00.hello/ref/x86/linux/o3-timing/simout   |    8 +-
 .../ref/x86/linux/o3-timing/stats.txt         |   22 +-
 .../ref/x86/linux/simple-atomic/config.ini    |   26 +-
 .../ref/x86/linux/simple-atomic/simout        |    8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |    8 +-
 .../x86/linux/simple-timing-ruby/config.ini   |   36 +-
 .../x86/linux/simple-timing-ruby/ruby.stats   |   30 +-
 .../ref/x86/linux/simple-timing-ruby/simout   |    8 +-
 .../x86/linux/simple-timing-ruby/stats.txt    |   10 +-
 .../ref/x86/linux/simple-timing/config.ini    |   38 +-
 .../ref/x86/linux/simple-timing/simout        |    8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   22 +-
 .../ref/alpha/linux/o3-timing/config.ini      |   29 +-
 .../ref/alpha/linux/o3-timing/simout          |    8 +-
 .../ref/alpha/linux/o3-timing/stats.txt       |   20 +-
 .../ref/sparc/linux/inorder-timing/config.ini |   31 +-
 .../ref/sparc/linux/inorder-timing/simout     |    8 +-
 .../ref/sparc/linux/inorder-timing/stats.txt  |   66 +-
 .../ref/sparc/linux/o3-timing/config.ini      |   29 +-
 .../ref/sparc/linux/o3-timing/simout          |    8 +-
 .../ref/sparc/linux/o3-timing/stats.txt       |   22 +-
 .../ref/sparc/linux/simple-atomic/config.ini  |   17 +-
 .../ref/sparc/linux/simple-atomic/simout      |    8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   10 +-
 .../ref/sparc/linux/simple-timing/config.ini  |   29 +-
 .../ref/sparc/linux/simple-timing/simout      |    8 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   22 +-
 .../ref/alpha/eio/simple-atomic/simerr        |   15 +-
 .../ref/alpha/eio/simple-atomic/simout        |   11 +-
 .../ref/alpha/eio/simple-atomic/stats.txt     |   80 --
 .../ref/alpha/eio/simple-timing/simerr        |   15 +-
 .../ref/alpha/eio/simple-timing/simout        |   11 +-
 .../ref/alpha/eio/simple-timing/stats.txt     |  330 -----
 .../ref/alpha/eio/simple-atomic-mp/simerr     |   19 +-
 .../ref/alpha/eio/simple-atomic-mp/simout     |   17 +-
 .../ref/alpha/eio/simple-atomic-mp/stats.txt  |  749 -----------
 .../ref/alpha/eio/simple-timing-mp/simerr     |   19 +-
 .../ref/alpha/eio/simple-timing-mp/simout     |   17 +-
 .../ref/alpha/eio/simple-timing-mp/stats.txt  | 1181 -----------------
 .../ref/sparc/linux/o3-timing-mp/config.ini   |   53 +-
 .../ref/sparc/linux/o3-timing-mp/simout       |    8 +-
 .../ref/sparc/linux/o3-timing-mp/stats.txt    |   40 +-
 .../sparc/linux/simple-atomic-mp/config.ini   |   57 +-
 .../ref/sparc/linux/simple-atomic-mp/simout   |    8 +-
 .../sparc/linux/simple-atomic-mp/stats.txt    |   46 +-
 .../sparc/linux/simple-timing-mp/config.ini   |   53 +-
 .../ref/sparc/linux/simple-timing-mp/simout   |    8 +-
 .../sparc/linux/simple-timing-mp/stats.txt    |   46 +-
 .../config.ini                                |   97 +-
 .../ruby.stats                                |   35 +-
 .../memtest-ruby-MESI_CMP_directory/simout    |    6 +-
 .../memtest-ruby-MESI_CMP_directory/stats.txt |   18 +-
 .../config.ini                                |  120 +-
 .../ruby.stats                                |   34 +-
 .../memtest-ruby-MOESI_CMP_directory/simout   |    8 +-
 .../stats.txt                                 |   18 +-
 .../memtest-ruby-MOESI_CMP_token/config.ini   |  118 +-
 .../memtest-ruby-MOESI_CMP_token/ruby.stats   | 1178 ++++++++--------
 .../linux/memtest-ruby-MOESI_CMP_token/simerr |  146 +-
 .../linux/memtest-ruby-MOESI_CMP_token/simout |   10 +-
 .../memtest-ruby-MOESI_CMP_token/stats.txt    |    6 +-
 .../memtest-ruby-MOESI_hammer/config.ini      |   13 +-
 .../memtest-ruby-MOESI_hammer/ruby.stats      | 1028 +++++++-------
 .../linux/memtest-ruby-MOESI_hammer/simerr    |  146 +-
 .../linux/memtest-ruby-MOESI_hammer/simout    |    8 +-
 .../linux/memtest-ruby-MOESI_hammer/stats.txt |    6 +-
 .../ref/alpha/linux/memtest-ruby/config.ini   |  120 +-
 .../ref/alpha/linux/memtest-ruby/ruby.stats   |   34 +-
 .../ref/alpha/linux/memtest-ruby/simout       |    8 +-
 .../ref/alpha/linux/memtest-ruby/stats.txt    |   18 +-
 .../ref/alpha/linux/memtest/config.ini        |   57 +-
 .../50.memtest/ref/alpha/linux/memtest/simout |    8 +-
 .../ref/alpha/linux/memtest/stats.txt         |   24 +-
 .../ruby.stats                                |   28 +-
 .../rubytest-ruby-MESI_CMP_directory/simout   |    7 +-
 .../stats.txt                                 |    6 +-
 .../ruby.stats                                |   28 +-
 .../rubytest-ruby-MOESI_CMP_directory/simout  |    7 +-
 .../stats.txt                                 |    6 +-
 .../rubytest-ruby-MOESI_CMP_token/ruby.stats  |  413 +++---
 .../rubytest-ruby-MOESI_CMP_token/simout      |    9 +-
 .../rubytest-ruby-MOESI_CMP_token/stats.txt   |    6 +-
 .../rubytest-ruby-MOESI_hammer/ruby.stats     |   24 +-
 .../linux/rubytest-ruby-MOESI_hammer/simout   |    7 +-
 .../rubytest-ruby-MOESI_hammer/stats.txt      |    6 +-
 .../ref/alpha/linux/rubytest-ruby/ruby.stats  |   32 +-
 .../ref/alpha/linux/rubytest-ruby/simout      |    7 +-
 .../ref/alpha/linux/rubytest-ruby/stats.txt   |    6 +-
 472 files changed, 7158 insertions(+), 9014 deletions(-)

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index 62b96c7c4..048f742ca 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -19,7 +19,6 @@ mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 pal=/dist/m5/system/binaries/ts_osfpal
-physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -31,7 +30,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[2]
+system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
@@ -41,8 +40,8 @@ ranges=8796093022208:18446744073709551615
 req_size=16
 resp_size=16
 write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[0]
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
 
 [system.cpu0]
 type=DerivO3CPU
@@ -143,7 +142,7 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -164,7 +163,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
 
 [system.cpu0.dtb]
 type=AlphaTLB
@@ -435,7 +434,7 @@ opLat=3
 
 [system.cpu0.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -456,7 +455,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
 
 [system.cpu0.interrupts]
 type=AlphaInterrupts
@@ -567,7 +566,7 @@ icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -588,7 +587,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[4]
+mem_side=system.toL2Bus.slave[3]
 
 [system.cpu1.dtb]
 type=AlphaTLB
@@ -859,7 +858,7 @@ opLat=3
 
 [system.cpu1.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -880,7 +879,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[3]
+mem_side=system.toL2Bus.slave[2]
 
 [system.cpu1.interrupts]
 type=AlphaInterrupts
@@ -945,11 +944,12 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
+master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
 type=BaseCache
-addr_range=0:8589934591
+addr_ranges=0:8589934591
 assoc=8
 block_size=64
 forward_snoops=false
@@ -969,12 +969,12 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[32]
-mem_side=system.membus.port[3]
+cpu_side=system.iobus.master[29]
+mem_side=system.membus.slave[1]
 
 [system.l2c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
 forward_snoops=true
@@ -994,8 +994,8 @@ tgts_per_mshr=16
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[4]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
 
 [system.membus]
 type=Bus
@@ -1007,7 +1007,8 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
+master=system.bridge.slave system.physmem.port[0]
+slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -1026,14 +1027,16 @@ warn_access=
 pio=system.membus.default
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[1]
 
 [system.simple_disk]
 type=SimpleDisk
@@ -1061,7 +1064,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
 
 [system.tsunami]
 type=Tsunami
@@ -1078,7 +1082,7 @@ pio_latency=1000
 platform=system.tsunami
 system=system
 terminal=system.terminal
-pio=system.iobus.port[25]
+pio=system.iobus.master[24]
 
 [system.tsunami.cchip]
 type=TsunamiCChip
@@ -1086,7 +1090,7 @@ pio_addr=8803072344064
 pio_latency=1000
 system=system
 tsunami=system.tsunami
-pio=system.iobus.port[1]
+pio=system.iobus.master[0]
 
 [system.tsunami.ethernet]
 type=NSGigE
@@ -1155,9 +1159,9 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
-pio=system.iobus.port[29]
+config=system.iobus.master[28]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -1173,7 +1177,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[9]
+pio=system.iobus.master[8]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
@@ -1189,7 +1193,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[20]
+pio=system.iobus.master[19]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
@@ -1205,7 +1209,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[21]
+pio=system.iobus.master[20]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
@@ -1221,7 +1225,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[10]
+pio=system.iobus.master[9]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
@@ -1237,7 +1241,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[12]
+pio=system.iobus.master[11]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
@@ -1253,7 +1257,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[13]
+pio=system.iobus.master[12]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
@@ -1269,7 +1273,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[14]
+pio=system.iobus.master[13]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
@@ -1285,7 +1289,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[15]
+pio=system.iobus.master[14]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
@@ -1301,7 +1305,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[16]
+pio=system.iobus.master[15]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
@@ -1317,7 +1321,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[17]
+pio=system.iobus.master[16]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
@@ -1333,7 +1337,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[18]
+pio=system.iobus.master[17]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
@@ -1349,7 +1353,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[19]
+pio=system.iobus.master[18]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
@@ -1365,7 +1369,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[11]
+pio=system.iobus.master[10]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
@@ -1381,7 +1385,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[8]
+pio=system.iobus.master[7]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
@@ -1397,7 +1401,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[3]
+pio=system.iobus.master[2]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
@@ -1413,7 +1417,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[4]
+pio=system.iobus.master[3]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
@@ -1429,7 +1433,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[5]
+pio=system.iobus.master[4]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
@@ -1445,7 +1449,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[6]
+pio=system.iobus.master[5]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
@@ -1461,7 +1465,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[7]
+pio=system.iobus.master[6]
 
 [system.tsunami.fb]
 type=BadDevice
@@ -1469,7 +1473,7 @@ devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=1000
 system=system
-pio=system.iobus.port[22]
+pio=system.iobus.master[21]
 
 [system.tsunami.ide]
 type=IdeController
@@ -1523,9 +1527,9 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[27]
-dma=system.iobus.port[28]
-pio=system.iobus.port[26]
+config=system.iobus.master[26]
+dma=system.iobus.slave[1]
+pio=system.iobus.master[25]
 
 [system.tsunami.io]
 type=TsunamiIO
@@ -1536,7 +1540,7 @@ system=system
 time=Thu Jan  1 00:00:00 2009
 tsunami=system.tsunami
 year_is_bcd=false
-pio=system.iobus.port[23]
+pio=system.iobus.master[22]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
@@ -1544,7 +1548,7 @@ pio_addr=8802535473152
 pio_latency=1000
 system=system
 tsunami=system.tsunami
-pio=system.iobus.port[2]
+pio=system.iobus.master[1]
 
 [system.tsunami.pciconfig]
 type=PciConfigAll
@@ -1562,5 +1566,5 @@ pio_latency=1000
 platform=system.tsunami
 system=system
 terminal=system.terminal
-pio=system.iobus.port[24]
+pio=system.iobus.master[23]
 
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index da3261384..a7ff9525f 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@@ -1,12 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 18:11:03
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:07
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 107002000
 Exiting @ tick 1899401490000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index af2074343..fbb891fc7 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.899401                       # Nu
 sim_ticks                                1899401490000                       # Number of ticks simulated
 final_tick                               1899401490000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 189434                       # Simulator instruction rate (inst/s)
-host_op_rate                                   189434                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6363739723                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 296196                       # Number of bytes of host memory used
-host_seconds                                   298.47                       # Real time elapsed on the host
+host_inst_rate                                  69911                       # Simulator instruction rate (inst/s)
+host_op_rate                                    69911                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2348556801                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 300512                       # Number of bytes of host memory used
+host_seconds                                   808.75                       # Real time elapsed on the host
 sim_insts                                    56540749                       # Number of instructions simulated
 sim_ops                                      56540749                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    30421696                       # Number of bytes read from this memory
@@ -178,8 +178,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              122679                       # number of writebacks
@@ -339,7 +339,7 @@ system.iocache.blocked_cycles::no_targets            0                       # n
 system.iocache.blocked::no_mshrs                10454                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs  6179.172374                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41520                       # number of writebacks
@@ -691,30 +691,30 @@ system.tsunami.ethernet.descDMAWrites               0                       # Nu
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
 system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
 system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
 system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
 system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
 system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
 system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
 system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
 system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
 system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
 system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
 system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
 system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
 system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
 system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu0.icache.replacements                923652                       # number of replacements
@@ -761,7 +761,7 @@ system.cpu0.icache.blocked_cycles::no_targets            0
 system.cpu0.icache.blocked::no_mshrs              111                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs 10234.225225                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks          196                       # number of writebacks
@@ -1275,7 +1275,7 @@ system.cpu1.icache.blocked_cycles::no_targets            0
 system.cpu1.icache.blocked::no_mshrs               38                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs  9513.157895                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks           52                       # number of writebacks
@@ -1379,7 +1379,7 @@ system.cpu1.dcache.blocked_cycles::no_targets            0
 system.cpu1.dcache.blocked::no_mshrs             8713                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13052.272237                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks       116478                       # number of writebacks
@@ -1522,8 +1522,8 @@ system.cpu0.kern.mode_good::user                 1162
 system.cpu0.kern.mode_good::idle                    0                      
 system.cpu0.kern.mode_switch_good::kernel     0.162038                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_ticks::kernel      1897616401500     99.91%     99.91% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::user          1784230000      0.09%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index ecd4c00a8..a8321f91c 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -19,7 +19,6 @@ mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 pal=/dist/m5/system/binaries/ts_osfpal
-physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -31,7 +30,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[2]
+system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
@@ -41,8 +40,8 @@ ranges=8796093022208:18446744073709551615
 req_size=16
 resp_size=16
 write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[0]
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -143,7 +142,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -164,7 +163,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -435,7 +434,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -456,7 +455,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -521,11 +520,12 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
+master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
 type=BaseCache
-addr_range=0:8589934591
+addr_ranges=0:8589934591
 assoc=8
 block_size=64
 forward_snoops=false
@@ -545,12 +545,12 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[32]
-mem_side=system.membus.port[3]
+cpu_side=system.iobus.master[29]
+mem_side=system.membus.slave[1]
 
 [system.l2c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
 forward_snoops=true
@@ -570,8 +570,8 @@ tgts_per_mshr=16
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[4]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
 
 [system.membus]
 type=Bus
@@ -583,7 +583,8 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
+master=system.bridge.slave system.physmem.port[0]
+slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -602,14 +603,16 @@ warn_access=
 pio=system.membus.default
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[1]
 
 [system.simple_disk]
 type=SimpleDisk
@@ -637,7 +640,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.tsunami]
 type=Tsunami
@@ -654,7 +658,7 @@ pio_latency=1000
 platform=system.tsunami
 system=system
 terminal=system.terminal
-pio=system.iobus.port[25]
+pio=system.iobus.master[24]
 
 [system.tsunami.cchip]
 type=TsunamiCChip
@@ -662,7 +666,7 @@ pio_addr=8803072344064
 pio_latency=1000
 system=system
 tsunami=system.tsunami
-pio=system.iobus.port[1]
+pio=system.iobus.master[0]
 
 [system.tsunami.ethernet]
 type=NSGigE
@@ -731,9 +735,9 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
-pio=system.iobus.port[29]
+config=system.iobus.master[28]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -749,7 +753,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[9]
+pio=system.iobus.master[8]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
@@ -765,7 +769,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[20]
+pio=system.iobus.master[19]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
@@ -781,7 +785,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[21]
+pio=system.iobus.master[20]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
@@ -797,7 +801,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[10]
+pio=system.iobus.master[9]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
@@ -813,7 +817,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[12]
+pio=system.iobus.master[11]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
@@ -829,7 +833,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[13]
+pio=system.iobus.master[12]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
@@ -845,7 +849,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[14]
+pio=system.iobus.master[13]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
@@ -861,7 +865,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[15]
+pio=system.iobus.master[14]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
@@ -877,7 +881,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[16]
+pio=system.iobus.master[15]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
@@ -893,7 +897,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[17]
+pio=system.iobus.master[16]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
@@ -909,7 +913,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[18]
+pio=system.iobus.master[17]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
@@ -925,7 +929,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[19]
+pio=system.iobus.master[18]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
@@ -941,7 +945,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[11]
+pio=system.iobus.master[10]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
@@ -957,7 +961,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[8]
+pio=system.iobus.master[7]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
@@ -973,7 +977,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[3]
+pio=system.iobus.master[2]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
@@ -989,7 +993,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[4]
+pio=system.iobus.master[3]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
@@ -1005,7 +1009,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[5]
+pio=system.iobus.master[4]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
@@ -1021,7 +1025,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[6]
+pio=system.iobus.master[5]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
@@ -1037,7 +1041,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[7]
+pio=system.iobus.master[6]
 
 [system.tsunami.fb]
 type=BadDevice
@@ -1045,7 +1049,7 @@ devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=1000
 system=system
-pio=system.iobus.port[22]
+pio=system.iobus.master[21]
 
 [system.tsunami.ide]
 type=IdeController
@@ -1099,9 +1103,9 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[27]
-dma=system.iobus.port[28]
-pio=system.iobus.port[26]
+config=system.iobus.master[26]
+dma=system.iobus.slave[1]
+pio=system.iobus.master[25]
 
 [system.tsunami.io]
 type=TsunamiIO
@@ -1112,7 +1116,7 @@ system=system
 time=Thu Jan  1 00:00:00 2009
 tsunami=system.tsunami
 year_is_bcd=false
-pio=system.iobus.port[23]
+pio=system.iobus.master[22]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
@@ -1120,7 +1124,7 @@ pio_addr=8802535473152
 pio_latency=1000
 system=system
 tsunami=system.tsunami
-pio=system.iobus.port[2]
+pio=system.iobus.master[1]
 
 [system.tsunami.pciconfig]
 type=PciConfigAll
@@ -1138,5 +1142,5 @@ pio_latency=1000
 platform=system.tsunami
 system=system
 terminal=system.terminal
-pio=system.iobus.port[24]
+pio=system.iobus.master[23]
 
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index 52235dbd6..6b30da191 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -1,11 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 18:10:30
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:06
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1858684403000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index da1fed07c..ae2948145 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.858684                       # Nu
 sim_ticks                                1858684403000                       # Number of ticks simulated
 final_tick                               1858684403000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 192280                       # Simulator instruction rate (inst/s)
-host_op_rate                                   192280                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6731751609                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 292636                       # Number of bytes of host memory used
-host_seconds                                   276.11                       # Real time elapsed on the host
+host_inst_rate                                  73473                       # Simulator instruction rate (inst/s)
+host_op_rate                                    73473                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2572309842                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 296656                       # Number of bytes of host memory used
+host_seconds                                   722.57                       # Real time elapsed on the host
 sim_insts                                    53089851                       # Number of instructions simulated
 sim_ops                                      53089851                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    29847552                       # Number of bytes read from this memory
@@ -117,8 +117,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              117800                       # number of writebacks
@@ -233,7 +233,7 @@ system.iocache.blocked_cycles::no_targets            0                       # n
 system.iocache.blocked::no_mshrs                10476                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs  6169.250477                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
@@ -585,30 +585,30 @@ system.tsunami.ethernet.descDMAWrites               0                       # Nu
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
 system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
 system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
 system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
 system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
 system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
 system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
 system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
 system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
 system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
 system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
 system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
 system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
 system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
 system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu.icache.replacements                1025621                       # number of replacements
@@ -655,7 +655,7 @@ system.cpu.icache.blocked_cycles::no_targets            0
 system.cpu.icache.blocked::no_mshrs               150                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs 11196.646667                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks          238                       # number of writebacks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
index 655130261..b11582c4e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
@@ -10,20 +10,18 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
 atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
-boot_loader_mem=system.realview.nvmem
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
 memories=system.physmem system.realview.nvmem
 midr_regval=890224640
 num_work_ids=16
-physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 work_begin_ckpt_count=0
@@ -63,7 +61,7 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
 [system.cpu]
@@ -662,8 +660,10 @@ warn_access=warn
 pio=system.membus.default
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=true
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
@@ -894,8 +894,10 @@ system=system
 pio=system.iobus.master[22]
 
 [system.realview.nvmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
index 37a41903b..8da57663e 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 18:15:21
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 17:08:48
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2501676293500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index ec9717e88..bf07a31ac 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -4,22 +4,13 @@ sim_seconds                                  2.501676                       # Nu
 sim_ticks                                2501676293500                       # Number of ticks simulated
 final_tick                               2501676293500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  79857                       # Simulator instruction rate (inst/s)
-host_op_rate                                   103150                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3360326389                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 381664                       # Number of bytes of host memory used
-host_seconds                                   744.47                       # Real time elapsed on the host
+host_inst_rate                                  32851                       # Simulator instruction rate (inst/s)
+host_op_rate                                    42433                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1382341341                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 388632                       # Number of bytes of host memory used
+host_seconds                                  1809.74                       # Real time elapsed on the host
 sim_insts                                    59451291                       # Number of instructions simulated
 sim_ops                                      76792341                       # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read                   64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read              64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
-system.realview.nvmem.num_reads                     1                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
-system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
-system.realview.nvmem.bw_read                      26                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read                 26                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total                     26                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read                   129652968                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                1121024                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  9585096                       # Number of bytes written to this memory
@@ -30,6 +21,15 @@ system.physmem.bw_read                       51826437                       # To
 system.physmem.bw_inst_read                    448109                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write                       3831469                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total                      55657906                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read                   64                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read              64                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
+system.realview.nvmem.num_reads                     1                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
+system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
+system.realview.nvmem.bw_read                      26                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read                 26                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total                     26                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        119784                       # number of replacements
 system.l2c.tagsinuse                     25999.615357                       # Cycle average of tags in use
 system.l2c.total_refs                         1826145                       # Total number of references to valid blocks.
@@ -169,8 +169,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              102641                       # number of writebacks
@@ -683,7 +683,7 @@ system.cpu.icache.blocked_cycles::no_targets            0
 system.cpu.icache.blocked::no_mshrs               416                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs  7692.266827                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        59844                       # number of writebacks
@@ -858,14 +858,14 @@ system.iocache.replacements                         0                       # nu
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
+system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296055922339                       # number of ReadReq MSHR uncacheable cycles
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index 54fc0a20c..632f13a19 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -10,20 +10,18 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
 atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
-boot_loader_mem=system.realview.nvmem
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
 memories=system.physmem system.realview.nvmem
 midr_regval=890224640
 num_work_ids=16
-physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 work_begin_ckpt_count=0
@@ -63,7 +61,7 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
 [system.cpu0]
@@ -1045,8 +1043,10 @@ warn_access=warn
 pio=system.membus.default
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=true
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
@@ -1277,8 +1277,10 @@ system=system
 pio=system.iobus.master[22]
 
 [system.realview.nvmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
index b8d0cb88a..6b6706b72 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 18:22:04
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 17:10:02
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2570828403500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index c5e5a6be8..afefe64cd 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -4,22 +4,13 @@ sim_seconds                                  2.570828                       # Nu
 sim_ticks                                2570828403500                       # Number of ticks simulated
 final_tick                               2570828403500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  96885                       # Simulator instruction rate (inst/s)
-host_op_rate                                   125154                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4026902595                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 385208                       # Number of bytes of host memory used
-host_seconds                                   638.41                       # Real time elapsed on the host
+host_inst_rate                                  36466                       # Simulator instruction rate (inst/s)
+host_op_rate                                    47106                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1515652841                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 392156                       # Number of bytes of host memory used
+host_seconds                                  1696.19                       # Real time elapsed on the host
 sim_insts                                    61852501                       # Number of instructions simulated
 sim_ops                                      79899751                       # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read                  384                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read             384                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
-system.realview.nvmem.num_reads                     6                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
-system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
-system.realview.nvmem.bw_read                     149                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read                149                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total                    149                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read                   131418468                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                1192320                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 10172560                       # Number of bytes written to this memory
@@ -30,6 +21,15 @@ system.physmem.bw_read                       51119113                       # To
 system.physmem.bw_inst_read                    463788                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write                       3956919                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total                      55076032                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read                  384                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read             384                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
+system.realview.nvmem.num_reads                     6                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
+system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
+system.realview.nvmem.bw_read                     149                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read                149                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total                    149                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        130877                       # number of replacements
 system.l2c.tagsinuse                     27573.095607                       # Cycle average of tags in use
 system.l2c.total_refs                         1846037                       # Total number of references to valid blocks.
@@ -267,8 +267,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              111616                       # number of writebacks
@@ -812,7 +812,7 @@ system.cpu0.icache.blocked_cycles::no_targets            0
 system.cpu0.icache.blocked::no_mshrs              206                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs  8213.548544                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks        19233                       # number of writebacks
@@ -1345,7 +1345,7 @@ system.cpu1.icache.blocked_cycles::no_targets            0
 system.cpu1.icache.blocked::no_mshrs              234                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs  6555.529915                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks        32964                       # number of writebacks
@@ -1523,14 +1523,14 @@ system.iocache.replacements                         0                       # nu
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
+system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308112364906                       # number of ReadReq MSHR uncacheable cycles
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
index 696134c20..e41fe50a6 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
@@ -1 +1 @@
-build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual FAILED!
+build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual FAILED!
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
index f397106c44404b7faf7531ddbdce5712ab58ad51..92fa179c580f219b0f221c6cc53efecaf0626dfd 100644
GIT binary patch
delta 44
zcmbQDKSh7TYi>rf&2P91*??4>(00bj??v<`+lq)zmKHfNSwVCOqw(gWqURX_ZVM0F

delta 42
xcmbQDKSh7TYi>sK&2P91*??4>(00bjK_cfSbBb6onoO1xUB+m%`Kai5MgT=x4toFq

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index 7b28f6e69..e70ebd6c7 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -10,20 +10,18 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
 atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
-boot_loader_mem=system.realview.nvmem
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
 memories=system.physmem system.realview.nvmem
 midr_regval=890224640
 num_work_ids=16
-physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 work_begin_ckpt_count=0
@@ -63,7 +61,7 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
 [system.cpu]
@@ -603,8 +601,10 @@ warn_access=warn
 pio=system.membus.default
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=true
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
@@ -835,8 +835,10 @@ system=system
 pio=system.iobus.master[22]
 
 [system.realview.nvmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
index 16435a5eb..3751264d1 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 18:11:20
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 17:05:43
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2501676293500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index 356c695d2..97fe75f03 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -4,22 +4,13 @@ sim_seconds                                  2.501676                       # Nu
 sim_ticks                                2501676293500                       # Number of ticks simulated
 final_tick                               2501676293500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  93944                       # Simulator instruction rate (inst/s)
-host_op_rate                                   121345                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3953091411                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 381372                       # Number of bytes of host memory used
-host_seconds                                   632.84                       # Real time elapsed on the host
+host_inst_rate                                  32202                       # Simulator instruction rate (inst/s)
+host_op_rate                                    41595                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1355039119                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 388344                       # Number of bytes of host memory used
+host_seconds                                  1846.20                       # Real time elapsed on the host
 sim_insts                                    59451291                       # Number of instructions simulated
 sim_ops                                      76792341                       # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read                   64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read              64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
-system.realview.nvmem.num_reads                     1                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
-system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
-system.realview.nvmem.bw_read                      26                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read                 26                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total                     26                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read                   129652968                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                1121024                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  9585096                       # Number of bytes written to this memory
@@ -30,6 +21,15 @@ system.physmem.bw_read                       51826437                       # To
 system.physmem.bw_inst_read                    448109                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write                       3831469                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total                      55657906                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read                   64                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read              64                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
+system.realview.nvmem.num_reads                     1                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
+system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
+system.realview.nvmem.bw_read                      26                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read                 26                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total                     26                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        119784                       # number of replacements
 system.l2c.tagsinuse                     25999.615357                       # Cycle average of tags in use
 system.l2c.total_refs                         1826145                       # Total number of references to valid blocks.
@@ -169,8 +169,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              102641                       # number of writebacks
@@ -638,7 +638,7 @@ system.cpu.icache.blocked_cycles::no_targets            0
 system.cpu.icache.blocked::no_mshrs               416                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs  7692.266827                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        59844                       # number of writebacks
@@ -813,14 +813,14 @@ system.iocache.replacements                         0                       # nu
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
+system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296055922339                       # number of ReadReq MSHR uncacheable cycles
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
index 379525fde..e02484e67 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2012 22:41:43
-gem5 started Apr 22 2012 23:27:12
-gem5 executing on burrito
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 16:05:33
+gem5 executing on piton
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index 0afcdd36b..f1c4ffb88 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.169500                       # Nu
 sim_ticks                                5169499540500                       # Number of ticks simulated
 final_tick                               5169499540500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 164266                       # Simulator instruction rate (inst/s)
-host_op_rate                                   323704                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1990886287                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 388036                       # Number of bytes of host memory used
-host_seconds                                  2596.58                       # Real time elapsed on the host
+host_inst_rate                                  77808                       # Simulator instruction rate (inst/s)
+host_op_rate                                   153328                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              943017240                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 366644                       # Number of bytes of host memory used
+host_seconds                                  5481.87                       # Real time elapsed on the host
 sim_insts                                   426530860                       # Number of instructions simulated
 sim_ops                                     840523890                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    15909184                       # Number of bytes read from this memory
@@ -150,8 +150,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              141885                       # number of writebacks
@@ -287,7 +287,7 @@ system.iocache.blocked_cycles::no_targets            0                       # n
 system.iocache.blocked::no_mshrs                11251                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs  6119.680384                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46668                       # number of writebacks
@@ -645,7 +645,7 @@ system.cpu.icache.blocked_cycles::no_targets            0
 system.cpu.icache.blocked::no_mshrs               292                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs  9866.404110                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         1570                       # number of writebacks
@@ -722,8 +722,8 @@ system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
 system.cpu.itb_walker_cache.writebacks::writebacks         1487                       # number of writebacks
@@ -790,8 +790,8 @@ system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
 system.cpu.dtb_walker_cache.writebacks::writebacks        34129                       # number of writebacks
@@ -869,7 +869,7 @@ system.cpu.dcache.blocked_cycles::no_targets            0
 system.cpu.dcache.blocked::no_mshrs              3499                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs  6796.936553                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      1561356                       # number of writebacks
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
index 78474a665..f293cbb8e 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -15,7 +15,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
 load_addr_mask=18446744073709551615
 mem_mode=timing
 memories=system.physmem
@@ -995,7 +995,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1015,7 +1015,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
index f3d58bfdd..5a285fe00 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/30/2012 03:41:58
+Real time: May/08/2012 16:45:52
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 635
-Elapsed_time_in_minutes: 10.5833
-Elapsed_time_in_hours: 0.176389
-Elapsed_time_in_days: 0.00734954
+Elapsed_time_in_seconds: 1474
+Elapsed_time_in_minutes: 24.5667
+Elapsed_time_in_hours: 0.409444
+Elapsed_time_in_days: 0.0170602
 
-Virtual_time_in_seconds: 634.41
-Virtual_time_in_minutes: 10.5735
-Virtual_time_in_hours:   0.176225
-Virtual_time_in_days:    0.00734271
+Virtual_time_in_seconds: 1451.34
+Virtual_time_in_minutes: 24.189
+Virtual_time_in_hours:   0.40315
+Virtual_time_in_days:    0.0167979
 
 Ruby_current_time: 10609379371
 Ruby_start_time: 0
 Ruby_cycles: 10609379371
 
-mbytes_resident: 267.07
-mbytes_total: 511.406
-resident_ratio: 0.522235
+mbytes_resident: 266.27
+mbytes_total: 468.445
+resident_ratio: 0.568411
 
 ruby_cycles_executed: [ 10609379372 10609379372 ]
 
@@ -123,13 +123,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4764816 average: 0.0223746 |
 Resource Usage
 --------------
 page_size: 4096
-user_time: 634
+user_time: 1451
 system_time: 0
-page_reclaims: 70180
-page_faults: 196
+page_reclaims: 69308
+page_faults: 15
 swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 14664
+block_outputs: 768
 
 Network Stats
 -------------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
index 0b014a692..3387e35c8 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,12 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 30 2012 03:31:05
-gem5 started Apr 30 2012 03:31:22
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86_MESI_CMP_directory/gem5.fast -d build/X86_MESI_CMP_directory/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
+gem5 compiled May  8 2012 16:21:06
+gem5 started May  8 2012 16:21:17
+gem5 executing on piton
+command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5304689685500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
index 58a66b232..2c42d3233 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.304690                       # Nu
 sim_ticks                                5304689685500                       # Number of ticks simulated
 final_tick                               5304689685500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 216507                       # Simulator instruction rate (inst/s)
-host_op_rate                                   442292                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8367043691                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 523684                       # Number of bytes of host memory used
-host_seconds                                   634.00                       # Real time elapsed on the host
+host_inst_rate                                  93103                       # Simulator instruction rate (inst/s)
+host_op_rate                                   190197                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3598037208                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 479692                       # Number of bytes of host memory used
+host_seconds                                  1474.33                       # Real time elapsed on the host
 sim_insts                                   137264752                       # Number of instructions simulated
 sim_ops                                     280412254                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  1392025556                       # Number of bytes read from this memory
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index 490c0c72f..acae3dcdb 100644
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -19,7 +19,7 @@ init_param=0
 kernel=
 load_addr_mask=1099511627775
 mem_mode=atomic
-memories=system.rom system.hypervisor_desc system.physmem2 system.nvram system.physmem system.partition_desc
+memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem2 system.rom system.physmem
 num_work_ids=16
 nvram=system.nvram
 nvram_addr=133429198848
@@ -29,7 +29,6 @@ openboot_bin=/dist/m5/system/binaries/openboot_new.bin
 partition_desc=system.partition_desc
 partition_desc_addr=133445976064
 partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
-physmem=system.physmem
 readfile=tests/halt.sh
 reset_addr=1099243192320
 reset_bin=/dist/m5/system/binaries/reset_new.bin
@@ -42,7 +41,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[9]
+system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
@@ -52,8 +51,8 @@ ranges=133412421632:133412421639 134217728000:554050781183 644245094400:65283502
 req_size=16
 resp_size=16
 write_ack=false
-master=system.iobus.port[14]
-slave=system.membus.port[2]
+master=system.iobus.slave[0]
+slave=system.membus.master[2]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -66,6 +65,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -84,8 +84,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=
-dcache_port=system.membus.port[11]
-icache_port=system.membus.port[10]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -108,7 +108,7 @@ image=system.disk0.image
 pio_addr=134217728000
 pio_latency=2
 system=system
-pio=system.iobus.port[15]
+pio=system.iobus.master[14]
 
 [system.disk0.image]
 type=CowDiskImage
@@ -124,14 +124,16 @@ image_file=/dist/m5/system/disks/disk.s10hw2
 read_only=true
 
 [system.hypervisor_desc]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=60
 latency_var=0
 null=false
 range=133446500352:133446508543
 zero=false
-port=system.membus.port[7]
+port=system.membus.master[7]
 
 [system.intrctrl]
 type=IntrControl
@@ -145,7 +147,8 @@ clock=2
 header_cycles=1
 use_default_range=false
 width=64
-port=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.bridge.master system.disk0.pio
+master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio
+slave=system.bridge.master
 
 [system.membus]
 type=Bus
@@ -157,7 +160,8 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] system.system_port system.cpu.icache_port system.cpu.dcache_port
+master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -176,54 +180,64 @@ warn_access=
 pio=system.membus.default
 
 [system.nvram]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=60
 latency_var=0
 null=false
 range=133429198848:133429207039
 zero=false
-port=system.membus.port[6]
+port=system.membus.master[6]
 
 [system.partition_desc]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=60
 latency_var=0
 null=false
 range=133445976064:133445984255
 zero=false
-port=system.membus.port[8]
+port=system.membus.master[8]
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=60
 latency_var=0
 null=false
 range=1048576:68157439
 zero=true
-port=system.membus.port[3]
+port=system.membus.master[3]
 
 [system.physmem2]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=60
 latency_var=0
 null=false
 range=2147483648:2415919103
 zero=true
-port=system.membus.port[4]
+port=system.membus.master[4]
 
 [system.rom]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=60
 latency_var=0
 null=false
 range=1099243192320:1099251580927
 zero=false
-port=system.membus.port[5]
+port=system.membus.master[5]
 
 [system.t1000]
 type=T1000
@@ -245,7 +259,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[0]
+pio=system.iobus.master[0]
 
 [system.t1000.fake_jbi]
 type=IsaFake
@@ -261,7 +275,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[11]
+pio=system.iobus.master[11]
 
 [system.t1000.fake_l2_1]
 type=IsaFake
@@ -277,7 +291,7 @@ ret_data8=255
 system=system
 update_data=true
 warn_access=
-pio=system.iobus.port[2]
+pio=system.iobus.master[2]
 
 [system.t1000.fake_l2_2]
 type=IsaFake
@@ -293,7 +307,7 @@ ret_data8=255
 system=system
 update_data=true
 warn_access=
-pio=system.iobus.port[3]
+pio=system.iobus.master[3]
 
 [system.t1000.fake_l2_3]
 type=IsaFake
@@ -309,7 +323,7 @@ ret_data8=255
 system=system
 update_data=true
 warn_access=
-pio=system.iobus.port[4]
+pio=system.iobus.master[4]
 
 [system.t1000.fake_l2_4]
 type=IsaFake
@@ -325,7 +339,7 @@ ret_data8=255
 system=system
 update_data=true
 warn_access=
-pio=system.iobus.port[5]
+pio=system.iobus.master[5]
 
 [system.t1000.fake_l2esr_1]
 type=IsaFake
@@ -341,7 +355,7 @@ ret_data8=255
 system=system
 update_data=true
 warn_access=
-pio=system.iobus.port[6]
+pio=system.iobus.master[6]
 
 [system.t1000.fake_l2esr_2]
 type=IsaFake
@@ -357,7 +371,7 @@ ret_data8=255
 system=system
 update_data=true
 warn_access=
-pio=system.iobus.port[7]
+pio=system.iobus.master[7]
 
 [system.t1000.fake_l2esr_3]
 type=IsaFake
@@ -373,7 +387,7 @@ ret_data8=255
 system=system
 update_data=true
 warn_access=
-pio=system.iobus.port[8]
+pio=system.iobus.master[8]
 
 [system.t1000.fake_l2esr_4]
 type=IsaFake
@@ -389,7 +403,7 @@ ret_data8=255
 system=system
 update_data=true
 warn_access=
-pio=system.iobus.port[9]
+pio=system.iobus.master[9]
 
 [system.t1000.fake_membnks]
 type=IsaFake
@@ -405,7 +419,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[1]
+pio=system.iobus.master[1]
 
 [system.t1000.fake_ssi]
 type=IsaFake
@@ -421,7 +435,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[10]
+pio=system.iobus.master[10]
 
 [system.t1000.hterm]
 type=Terminal
@@ -436,7 +450,7 @@ pio_addr=1099255906296
 pio_latency=2
 system=system
 time=Thu Jan  1 00:00:00 2009
-pio=system.membus.port[1]
+pio=system.membus.master[1]
 
 [system.t1000.hvuart]
 type=Uart8250
@@ -445,14 +459,14 @@ pio_latency=2
 platform=system.t1000
 system=system
 terminal=system.t1000.hterm
-pio=system.iobus.port[13]
+pio=system.iobus.master[13]
 
 [system.t1000.iob]
 type=Iob
 pio_latency=2
 platform=system.t1000
 system=system
-pio=system.membus.port[0]
+pio=system.membus.master[0]
 
 [system.t1000.pterm]
 type=Terminal
@@ -468,5 +482,5 @@ pio_latency=2
 platform=system.t1000
 system=system
 terminal=system.t1000.pterm
-pio=system.iobus.port[12]
+pio=system.iobus.master[12]
 
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
index c2315f7a1..3dd47139a 100755
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
@@ -1,12 +1,15 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 14:02:46
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/fast/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:49:20
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
 Global frequency set at 2000000000 ticks per second
-info: No kernel set for full system simulation. Assuming you know what you're doing...
+info: No kernel set for full system simulation. Assuming you know what you're doing if not SPARC ISA
+      0: system.t1000.htod: Real-time clock set to Thu Jan  1 00:00:00 2009
+
+      0: system.t1000.htod: Real-time clock set to 1230768000
 info: Entering event queue @ 0.  Starting simulation...
 info: Ignoring write to SPARC ERROR regsiter
 info: Ignoring write to SPARC ERROR regsiter
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
index 26c5818ca..714a7f4dc 100644
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.116889                       # Nu
 sim_ticks                                  2233777512                       # Number of ticks simulated
 final_tick                                 2233777512                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
-host_inst_rate                                4520258                       # Simulator instruction rate (inst/s)
-host_op_rate                                  4522035                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                4531400                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 500812                       # Number of bytes of host memory used
-host_seconds                                   492.96                       # Real time elapsed on the host
+host_inst_rate                                1707325                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1707996                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1711534                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 511008                       # Number of bytes of host memory used
+host_seconds                                  1305.13                       # Real time elapsed on the host
 sim_insts                                  2228284650                       # Number of instructions simulated
 sim_ops                                    2229160714                       # Number of ops (including micro ops) simulated
 system.hypervisor_desc.bytes_read               16792                       # Number of bytes read from this memory
@@ -19,15 +19,23 @@ system.hypervisor_desc.num_writes                   0                       # Nu
 system.hypervisor_desc.num_other                    0                       # Number of other requests responded to by this memory
 system.hypervisor_desc.bw_read                  15035                       # Total read bandwidth from this memory (bytes/s)
 system.hypervisor_desc.bw_total                 15035                       # Total bandwidth to/from this memory (bytes/s)
-system.rom.bytes_read                         1128688                       # Number of bytes read from this memory
-system.rom.bytes_inst_read                     432296                       # Number of instructions bytes read from this memory
-system.rom.bytes_written                            0                       # Number of bytes written to this memory
-system.rom.num_reads                           195123                       # Number of read requests responded to by this memory
-system.rom.num_writes                               0                       # Number of write requests responded to by this memory
-system.rom.num_other                                0                       # Number of other requests responded to by this memory
-system.rom.bw_read                            1010564                       # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_inst_read                        387054                       # Instruction read bandwidth from this memory (bytes/s)
-system.rom.bw_total                           1010564                       # Total bandwidth to/from this memory (bytes/s)
+system.nvram.bytes_read                           284                       # Number of bytes read from this memory
+system.nvram.bytes_inst_read                        0                       # Number of instructions bytes read from this memory
+system.nvram.bytes_written                         92                       # Number of bytes written to this memory
+system.nvram.num_reads                            284                       # Number of read requests responded to by this memory
+system.nvram.num_writes                            92                       # Number of write requests responded to by this memory
+system.nvram.num_other                              0                       # Number of other requests responded to by this memory
+system.nvram.bw_read                              254                       # Total read bandwidth from this memory (bytes/s)
+system.nvram.bw_write                              82                       # Write bandwidth from this memory (bytes/s)
+system.nvram.bw_total                             337                       # Total bandwidth to/from this memory (bytes/s)
+system.partition_desc.bytes_read                 4846                       # Number of bytes read from this memory
+system.partition_desc.bytes_inst_read               0                       # Number of instructions bytes read from this memory
+system.partition_desc.bytes_written                 0                       # Number of bytes written to this memory
+system.partition_desc.num_reads                   608                       # Number of read requests responded to by this memory
+system.partition_desc.num_writes                    0                       # Number of write requests responded to by this memory
+system.partition_desc.num_other                     0                       # Number of other requests responded to by this memory
+system.partition_desc.bw_read                    4339                       # Total read bandwidth from this memory (bytes/s)
+system.partition_desc.bw_total                   4339                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem2.bytes_read                 9813991967                       # Number of bytes read from this memory
 system.physmem2.bytes_inst_read            8318106840                       # Number of instructions bytes read from this memory
 system.physmem2.bytes_written               897268422                       # Number of bytes written to this memory
@@ -38,15 +46,15 @@ system.physmem2.bw_read                    8786901931                       # To
 system.physmem2.bw_inst_read               7447569684                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem2.bw_write                    803364182                       # Write bandwidth from this memory (bytes/s)
 system.physmem2.bw_total                   9590266113                       # Total bandwidth to/from this memory (bytes/s)
-system.nvram.bytes_read                           284                       # Number of bytes read from this memory
-system.nvram.bytes_inst_read                        0                       # Number of instructions bytes read from this memory
-system.nvram.bytes_written                         92                       # Number of bytes written to this memory
-system.nvram.num_reads                            284                       # Number of read requests responded to by this memory
-system.nvram.num_writes                            92                       # Number of write requests responded to by this memory
-system.nvram.num_other                              0                       # Number of other requests responded to by this memory
-system.nvram.bw_read                              254                       # Total read bandwidth from this memory (bytes/s)
-system.nvram.bw_write                              82                       # Write bandwidth from this memory (bytes/s)
-system.nvram.bw_total                             337                       # Total bandwidth to/from this memory (bytes/s)
+system.rom.bytes_read                         1128688                       # Number of bytes read from this memory
+system.rom.bytes_inst_read                     432296                       # Number of instructions bytes read from this memory
+system.rom.bytes_written                            0                       # Number of bytes written to this memory
+system.rom.num_reads                           195123                       # Number of read requests responded to by this memory
+system.rom.num_writes                               0                       # Number of write requests responded to by this memory
+system.rom.num_other                                0                       # Number of other requests responded to by this memory
+system.rom.bw_read                            1010564                       # Total read bandwidth from this memory (bytes/s)
+system.rom.bw_inst_read                        387054                       # Instruction read bandwidth from this memory (bytes/s)
+system.rom.bw_total                           1010564                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read                   709825348                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read              612291324                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 15400223                       # Number of bytes written to this memory
@@ -57,14 +65,6 @@ system.physmem.bw_read                      635538091                       # To
 system.physmem.bw_inst_read                 548211557                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write                      13788502                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total                     649326593                       # Total bandwidth to/from this memory (bytes/s)
-system.partition_desc.bytes_read                 4846                       # Number of bytes read from this memory
-system.partition_desc.bytes_inst_read               0                       # Number of instructions bytes read from this memory
-system.partition_desc.bytes_written                 0                       # Number of bytes written to this memory
-system.partition_desc.num_reads                   608                       # Number of read requests responded to by this memory
-system.partition_desc.num_writes                    0                       # Number of write requests responded to by this memory
-system.partition_desc.num_other                     0                       # Number of other requests responded to by this memory
-system.partition_desc.bw_read                    4339                       # Total read bandwidth from this memory (bytes/s)
-system.partition_desc.bw_total                   4339                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.numCycles                       2233777513                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
index b932d7fd7..37ea66e58 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -41,7 +40,6 @@ choiceCtrBits=2
 choicePredictorSize=8192
 clock=500
 cpu_id=0
-dataMemPort=dcache_port
 defer_registration=false
 div16Latency=1
 div16RepeatRate=1
@@ -56,7 +54,6 @@ do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
-fetchMemPort=icache_port
 functionTrace=false
 functionTraceStart=0
 function_trace=false
@@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -115,7 +112,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -123,7 +120,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -144,7 +141,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -155,7 +152,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -175,8 +172,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -186,7 +183,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -194,7 +192,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
 egid=100
 env=
 errout=cerr
@@ -218,15 +216,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
index f0d94be3d..4bff58d47 100755
--- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 17:33:26
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:38:38
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
index 206fd9b5c..7e649e9a6 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.274300                       # Nu
 sim_ticks                                274300226500                       # Number of ticks simulated
 final_tick                               274300226500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 157937                       # Simulator instruction rate (inst/s)
-host_op_rate                                   157937                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               71980747                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 209892                       # Number of bytes of host memory used
-host_seconds                                  3810.74                       # Real time elapsed on the host
+host_inst_rate                                  71153                       # Simulator instruction rate (inst/s)
+host_op_rate                                    71153                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               32428333                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214868                       # Number of bytes of host memory used
+host_seconds                                  8458.66                       # Real time elapsed on the host
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_ops                                     601856964                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5894080                       # Number of bytes read from this memory
@@ -57,30 +57,6 @@ system.cpu.workload.num_syscalls                   17                       # Nu
 system.cpu.numCycles                        548600454                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                     538371184                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
-system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                          412150                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        59439534                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                        489160920                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         89.165242                       # Percentage of cycles cpu is active
-system.cpu.comLoads                         114514042                       # Number of Load instructions committed
-system.cpu.comStores                         39451321                       # Number of Store instructions committed
-system.cpu.comBranches                       62547159                       # Number of Branches instructions committed
-system.cpu.comNops                           36304520                       # Number of Nop instructions committed
-system.cpu.comNonSpec                              17                       # Number of Non-Speculative instructions committed
-system.cpu.comInts                          349039879                       # Number of Integer instructions committed
-system.cpu.comFloats                               24                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                   601856964                       # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps                     601856964                       # Number of Ops committed (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total             601856964                       # Number of Instructions committed (Total)
-system.cpu.cpi                               0.911513                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         0.911513                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.097077                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         1.097077                       # IPC: Total IPC of All Threads
 system.cpu.branch_predictor.lookups          86318297                       # Number of BP lookups
 system.cpu.branch_predictor.condPredicted     81372201                       # Number of conditional branches predicted
 system.cpu.branch_predictor.condIncorrect     36359139                       # Number of conditional branches incorrect
@@ -107,6 +83,30 @@ system.cpu.execution_unit.mispredictPct     58.122091                       # Pe
 system.cpu.execution_unit.executions        412334574                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies              6482                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.contextSwitches                          1                       # Number of context switches
+system.cpu.threadCycles                     538371184                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled                          412150                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        59439534                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                        489160920                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         89.165242                       # Percentage of cycles cpu is active
+system.cpu.comLoads                         114514042                       # Number of Load instructions committed
+system.cpu.comStores                         39451321                       # Number of Store instructions committed
+system.cpu.comBranches                       62547159                       # Number of Branches instructions committed
+system.cpu.comNops                           36304520                       # Number of Nop instructions committed
+system.cpu.comNonSpec                              17                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                          349039879                       # Number of Integer instructions committed
+system.cpu.comFloats                               24                       # Number of Floating Point instructions committed
+system.cpu.committedInsts                   601856964                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                     601856964                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total             601856964                       # Number of Instructions committed (Total)
+system.cpu.cpi                               0.911513                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
+system.cpu.cpi_total                         0.911513                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.097077                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
+system.cpu.ipc_total                         1.097077                       # IPC: Total IPC of All Threads
 system.cpu.stage0.idleCycles                209725198                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                 338875256                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage0.utilization               61.770867                       # Percentage of cycles stage was utilized (processing insts).
@@ -165,7 +165,7 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets        87500                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
@@ -363,7 +363,7 @@ system.cpu.l2cache.blocked_cycles::no_targets            0
 system.cpu.l2cache.blocked::no_mshrs              127                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10066.929134                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        59346                       # number of writebacks
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index d5e06addc..d7f68c19e 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -419,7 +418,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -440,7 +439,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -451,7 +450,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -471,8 +470,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -482,7 +481,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -490,7 +490,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
 egid=100
 env=
 errout=cerr
@@ -514,15 +514,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
index 2e14d6c64..1f4384270 100755
--- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 17:33:40
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:36:56
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index 001739477..0a8d681a5 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.134621                       # Nu
 sim_ticks                                134621123500                       # Number of ticks simulated
 final_tick                               134621123500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 282179                       # Simulator instruction rate (inst/s)
-host_op_rate                                   282179                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               67168296                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211096                       # Number of bytes of host memory used
-host_seconds                                  2004.24                       # Real time elapsed on the host
+host_inst_rate                                  99995                       # Simulator instruction rate (inst/s)
+host_op_rate                                    99995                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               23802311                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215740                       # Number of bytes of host memory used
+host_seconds                                  5655.80                       # Real time elapsed on the host
 sim_insts                                   565552443                       # Number of instructions simulated
 sim_ops                                     565552443                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5937600                       # Number of bytes read from this memory
@@ -367,8 +367,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          445                       # number of ReadReq MSHR hits
@@ -577,7 +577,7 @@ system.cpu.l2cache.blocked_cycles::no_targets            0
 system.cpu.l2cache.blocked::no_mshrs               49                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs  6928.571429                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        59343                       # number of writebacks
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
index 8be56150d..927f52249 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -77,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
index b88c15875..db142b8a8 100755
--- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:10:30
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:40
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
index 97a3f2734..068e22070 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.300931                       # Nu
 sim_ticks                                300930958000                       # Number of ticks simulated
 final_tick                               300930958000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                5630967                       # Simulator instruction rate (inst/s)
-host_op_rate                                  5630966                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2815505896                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 200704                       # Number of bytes of host memory used
-host_seconds                                   106.88                       # Real time elapsed on the host
+host_inst_rate                                2479447                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2479447                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1239733454                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 205680                       # Number of bytes of host memory used
+host_seconds                                   242.74                       # Real time elapsed on the host
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_ops                                     601856964                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  2782990928                       # Number of bytes read from this memory
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index 83c88fa93..86520ac69 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -120,7 +119,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -159,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
index dfe9fcdd2..5a809a831 100755
--- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:10:31
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:07
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
index 4b454bbcf..fb6f85834 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.765623                       # Nu
 sim_ticks                                765623032000                       # Number of ticks simulated
 final_tick                               765623032000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2698243                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2698243                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3432438217                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 209572                       # Number of bytes of host memory used
-host_seconds                                   223.06                       # Real time elapsed on the host
+host_inst_rate                                 835603                       # Simulator instruction rate (inst/s)
+host_op_rate                                   835603                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1062971026                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214568                       # Number of bytes of host memory used
+host_seconds                                   720.27                       # Real time elapsed on the host
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_ops                                     601856964                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5889984                       # Number of bytes read from this memory
@@ -119,8 +119,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          795                       # number of ReadReq MSHR misses
@@ -195,8 +195,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       408190                       # number of writebacks
@@ -302,8 +302,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        59341                       # number of writebacks
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
index 043132ebd..d2c692362 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -509,12 +508,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
+cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
@@ -537,8 +536,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
index 35fcd0232..6445e3ddc 100755
--- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 16:38:16
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:20:58
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
index 8bc0cbb1b..54f7feb76 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.164248                       # Nu
 sim_ticks                                164248292500                       # Number of ticks simulated
 final_tick                               164248292500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 250614                       # Simulator instruction rate (inst/s)
-host_op_rate                                   264817                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               72208895                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224524                       # Number of bytes of host memory used
-host_seconds                                  2274.63                       # Real time elapsed on the host
+host_inst_rate                                  95192                       # Simulator instruction rate (inst/s)
+host_op_rate                                   100587                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               27427613                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231504                       # Number of bytes of host memory used
+host_seconds                                  5988.43                       # Real time elapsed on the host
 sim_insts                                   570052728                       # Number of instructions simulated
 sim_ops                                     602360935                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5850432                       # Number of bytes read from this memory
@@ -377,8 +377,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          310                       # number of ReadReq MSHR hits
@@ -474,7 +474,7 @@ system.cpu.dcache.blocked_cycles::no_targets            0
 system.cpu.dcache.blocked::no_mshrs              2180                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs  4389.455963                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       394908                       # number of writebacks
@@ -601,7 +601,7 @@ system.cpu.l2cache.blocked_cycles::no_targets            0
 system.cpu.l2cache.blocked::no_mshrs              332                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs  6039.156627                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        58158                       # number of writebacks
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
index 867a31b3a..98278be8c 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -95,12 +95,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic
+cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
@@ -123,8 +123,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
index fda635c2d..aa43ef922 100755
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 16:54:39
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:21:51
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
index 1d050592c..b23b7f871 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.301191                       # Nu
 sim_ticks                                301191370000                       # Number of ticks simulated
 final_tick                               301191370000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2848986                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3010454                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1505284316                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213580                       # Number of bytes of host memory used
-host_seconds                                   200.09                       # Real time elapsed on the host
+host_inst_rate                                1201570                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1269670                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              634859326                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220780                       # Number of bytes of host memory used
+host_seconds                                   474.42                       # Real time elapsed on the host
 sim_insts                                   570051644                       # Number of instructions simulated
 sim_ops                                     602359851                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  2680160157                       # Number of bytes read from this memory
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
index 877a85204..8ba39dd31 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -178,12 +177,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing
+cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
@@ -206,8 +205,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
index 25af6cb73..ec5b6e605 100755
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 16:58:09
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:22:17
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
index f70524856..dd6b444c4 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.796763                       # Nu
 sim_ticks                                796762926000                       # Number of ticks simulated
 final_tick                               796762926000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2008356                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2120897                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2814551305                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222752                       # Number of bytes of host memory used
-host_seconds                                   283.09                       # Real time elapsed on the host
+host_inst_rate                                 606714                       # Simulator instruction rate (inst/s)
+host_op_rate                                   640712                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              850261270                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229976                       # Number of bytes of host memory used
+host_seconds                                   937.08                       # Real time elapsed on the host
 sim_insts                                   568539343                       # Number of instructions simulated
 sim_ops                                     600398281                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5759488                       # Number of bytes read from this memory
@@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          643                       # number of ReadReq MSHR misses
@@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       392392                       # number of writebacks
@@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        57886                       # number of writebacks
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
index 5612e55e7..98314f012 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -419,7 +418,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -440,7 +439,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=SparcInterrupts
@@ -451,7 +450,7 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -471,8 +470,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -482,7 +481,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -490,7 +490,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
+cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
 egid=100
 env=
 errout=cerr
@@ -514,15 +514,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
index 709a4d648..3d27114e4 100755
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:18:12
-gem5 started Feb 12 2012 18:18:25
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:43:17
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index dd253efff..3819069b9 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.388554                       # Nu
 sim_ticks                                388554296500                       # Number of ticks simulated
 final_tick                               388554296500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 229375                       # Simulator instruction rate (inst/s)
-host_op_rate                                   230098                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               63606554                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214136                       # Number of bytes of host memory used
-host_seconds                                  6108.71                       # Real time elapsed on the host
+host_inst_rate                                 119684                       # Simulator instruction rate (inst/s)
+host_op_rate                                   120061                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               33188741                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223864                       # Number of bytes of host memory used
+host_seconds                                 11707.41                       # Real time elapsed on the host
 sim_insts                                  1401188958                       # Number of instructions simulated
 sim_ops                                    1405604152                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5987456                       # Number of bytes read from this memory
@@ -333,8 +333,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          624                       # number of ReadReq MSHR hits
@@ -426,7 +426,7 @@ system.cpu.dcache.blocked_cycles::no_targets            0
 system.cpu.dcache.blocked::no_mshrs                 7                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs  2214.285714                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       413195                       # number of writebacks
@@ -549,8 +549,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        59190                       # number of writebacks
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
index 12208533c..5860d36d4 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -77,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic
+cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
index dd6f18f54..86dd2db54 100755
--- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 13:56:17
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:43:18
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
index 317e75938..a7bbf2f2d 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.744764                       # Nu
 sim_ticks                                744764119000                       # Number of ticks simulated
 final_tick                               744764119000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4631105                       # Simulator instruction rate (inst/s)
-host_op_rate                                  4644873                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2322443893                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 203508                       # Number of bytes of host memory used
-host_seconds                                   320.68                       # Real time elapsed on the host
+host_inst_rate                                1723625                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1728749                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              864377228                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213676                       # Number of bytes of host memory used
+host_seconds                                   861.62                       # Real time elapsed on the host
 sim_insts                                  1485108101                       # Number of instructions simulated
 sim_ops                                    1489523295                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  7326269637                       # Number of bytes read from this memory
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
index 8f915a65c..8e4dd6b01 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=SparcInterrupts
@@ -120,7 +119,7 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -159,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
+cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
index 31dd55bac..0309c0267 100755
--- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 13:56:19
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:43:22
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
index 91253ef89..327f1f99e 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.064259                       # Nu
 sim_ticks                                2064258667000                       # Number of ticks simulated
 final_tick                               2064258667000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2132645                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2138986                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2964317062                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212372                       # Number of bytes of host memory used
-host_seconds                                   696.37                       # Real time elapsed on the host
+host_inst_rate                                 667477                       # Simulator instruction rate (inst/s)
+host_op_rate                                   669461                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              927773801                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222564                       # Number of bytes of host memory used
+host_seconds                                  2224.96                       # Real time elapsed on the host
 sim_insts                                  1485108101                       # Number of instructions simulated
 sim_ops                                    1489523295                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5909952                       # Number of bytes read from this memory
@@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1107                       # number of ReadReq MSHR misses
@@ -173,8 +173,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       407009                       # number of writebacks
@@ -289,8 +289,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        59035                       # number of writebacks
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
index 5b4602be4..ebc83b22f 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -159,7 +158,7 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[3]
+port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.fuPool]
 type=FUPool
@@ -426,7 +425,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -447,7 +446,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -455,8 +454,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[4]
-pio=system.membus.port[3]
+int_master=system.membus.slave[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -467,11 +467,11 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[2]
+port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -491,8 +491,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[4]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -502,7 +502,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -510,7 +511,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
+cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
@@ -534,15 +535,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
index 0aefca8ea..fe3d3cd18 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:18:12
-gem5 started Feb 12 2012 18:30:36
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:50:46
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
index b9dc005fb..7852ddedb 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.637054                       # Nu
 sim_ticks                                637054100000                       # Number of ticks simulated
 final_tick                               637054100000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  99624                       # Simulator instruction rate (inst/s)
-host_op_rate                                   183562                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               72118142                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221144                       # Number of bytes of host memory used
-host_seconds                                  8833.48                       # Real time elapsed on the host
+host_inst_rate                                  56200                       # Simulator instruction rate (inst/s)
+host_op_rate                                   103552                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               40683578                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226404                       # Number of bytes of host memory used
+host_seconds                                 15658.75                       # Real time elapsed on the host
 sim_insts                                   880025312                       # Number of instructions simulated
 sim_ops                                    1621493982                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5835840                       # Number of bytes read from this memory
@@ -330,8 +330,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          428                       # number of ReadReq MSHR hits
@@ -412,8 +412,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       400737                       # number of writebacks
@@ -534,8 +534,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        58331                       # number of writebacks
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
index 6904b6f42..67df96739 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -69,7 +69,7 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.membus.port[5]
+port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -77,8 +77,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[7]
-pio=system.membus.port[6]
+int_master=system.membus.slave[5]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -89,7 +90,7 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.membus.port[4]
+port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -97,7 +98,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic
+cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -121,15 +122,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
index 061803200..7e883d441 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:53
-gem5 started Feb 11 2012 14:08:56
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:50:47
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index 2bdb7b9df..8fa6b9f22 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.963993                       # Nu
 sim_ticks                                963992704000                       # Number of ticks simulated
 final_tick                               963992704000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1632386                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3007760                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1788140018                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 210284                       # Number of bytes of host memory used
-host_seconds                                   539.10                       # Real time elapsed on the host
+host_inst_rate                                 616329                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1135620                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              675136354                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215452                       # Number of bytes of host memory used
+host_seconds                                  1427.85                       # Real time elapsed on the host
 sim_insts                                   880025313                       # Number of instructions simulated
 sim_ops                                    1621493983                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                 11334586825                       # Number of bytes read from this memory
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
index 9097a5047..2b913aed8 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -91,11 +90,11 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[3]
+port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -116,7 +115,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -124,8 +123,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[4]
-pio=system.membus.port[3]
+int_master=system.membus.slave[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -136,11 +136,11 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[2]
+port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -160,8 +160,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[4]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -171,7 +171,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -179,7 +180,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
+cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -203,15 +204,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
index 527d3d172..f955c1c10 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:53
-gem5 started Feb 11 2012 14:11:10
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:52:52
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
index 308cb734c..ef0537a2c 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.803259                       # Nu
 sim_ticks                                1803258587000                       # Number of ticks simulated
 final_tick                               1803258587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 972144                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1791227                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1992018099                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219200                       # Number of bytes of host memory used
-host_seconds                                   905.24                       # Real time elapsed on the host
+host_inst_rate                                 328587                       # Simulator instruction rate (inst/s)
+host_op_rate                                   605440                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              673307954                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224396                       # Number of bytes of host memory used
+host_seconds                                  2678.21                       # Real time elapsed on the host
 sim_insts                                   880025313                       # Number of instructions simulated
 sim_ops                                    1621493983                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5725952                       # Number of bytes read from this memory
@@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          722                       # number of ReadReq MSHR misses
@@ -163,8 +163,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       396372                       # number of writebacks
@@ -270,8 +270,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        58007                       # number of writebacks
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index 71cbbf675..3ea467c54 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -509,14 +508,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
+cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -537,8 +536,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index 2d894fefb..97b90c338 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:02:50
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:22:28
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index a17606260..0a1029305 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.025989                       # Nu
 sim_ticks                                 25988864000                       # Number of ticks simulated
 final_tick                                25988864000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 238212                       # Simulator instruction rate (inst/s)
-host_op_rate                                   239922                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               68332245                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 357212                       # Number of bytes of host memory used
-host_seconds                                   380.33                       # Real time elapsed on the host
+host_inst_rate                                  71403                       # Simulator instruction rate (inst/s)
+host_op_rate                                    71915                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               20482160                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 364344                       # Number of bytes of host memory used
+host_seconds                                  1268.85                       # Real time elapsed on the host
 sim_insts                                    90599356                       # Number of instructions simulated
 sim_ops                                      91249910                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      999040                       # Number of bytes read from this memory
@@ -378,8 +378,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          223                       # number of ReadReq MSHR hits
@@ -475,7 +475,7 @@ system.cpu.dcache.blocked_cycles::no_targets            0
 system.cpu.dcache.blocked::no_mshrs              8078                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs  2860.120698                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       942908                       # number of writebacks
@@ -594,8 +594,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks           32                       # number of writebacks
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
index 4c0e3ba04..0dc5ea994 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -95,14 +95,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic
+cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -123,8 +123,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
index 439b5027c..863d389ca 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:03:02
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:24:24
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index 1ec302d05..6150ebd1b 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.054241                       # Nu
 sim_ticks                                 54240666000                       # Number of ticks simulated
 final_tick                                54240666000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2795699                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2815772                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1673691127                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 346432                       # Number of bytes of host memory used
-host_seconds                                    32.41                       # Real time elapsed on the host
+host_inst_rate                                1203852                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1212496                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              720706000                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 353596                       # Number of bytes of host memory used
+host_seconds                                    75.26                       # Real time elapsed on the host
 sim_insts                                    90602415                       # Number of instructions simulated
 sim_ops                                      91252969                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   521339715                       # Number of bytes read from this memory
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
index f9dbf6b5f..98847a36c 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -178,14 +177,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
+cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -206,8 +205,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
index d8b8bc833..10d881c1d 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:03:45
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:24:48
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index f3ad4a424..d20615e1d 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.148086                       # Nu
 sim_ticks                                148086239000                       # Number of ticks simulated
 final_tick                               148086239000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1876733                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1890189                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3068313156                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 355600                       # Number of bytes of host memory used
-host_seconds                                    48.26                       # Real time elapsed on the host
+host_inst_rate                                 549790                       # Simulator instruction rate (inst/s)
+host_op_rate                                   553732                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              898863423                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 362780                       # Number of bytes of host memory used
+host_seconds                                   164.75                       # Real time elapsed on the host
 sim_insts                                    90576869                       # Number of instructions simulated
 sim_ops                                      91226321                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      986112                       # Number of bytes read from this memory
@@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          599                       # number of ReadReq MSHR misses
@@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       942309                       # number of writebacks
@@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks           32                       # number of writebacks
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index 5d8a4468f..addbca3ec 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -77,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic
+cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:268435455
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
index 019979259..70118299e 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 13:56:49
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:43:24
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index fc2e52856..f04b9260d 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.122216                       # Nu
 sim_ticks                                122215830000                       # Number of ticks simulated
 final_tick                               122215830000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4048457                       # Simulator instruction rate (inst/s)
-host_op_rate                                  4048623                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2029262264                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 335836                       # Number of bytes of host memory used
-host_seconds                                    60.23                       # Real time elapsed on the host
+host_inst_rate                                1503519                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1503581                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              753629165                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 346024                       # Number of bytes of host memory used
+host_seconds                                   162.17                       # Real time elapsed on the host
 sim_insts                                   243825163                       # Number of instructions simulated
 sim_ops                                     243835278                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  1306360053                       # Number of bytes read from this memory
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
index ad77524dc..861290241 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=SparcInterrupts
@@ -120,7 +119,7 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -159,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
+cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:268435455
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
index 0301a7a93..4ee289cc3 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 13:58:00
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:44:07
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 14199b227..300c74bea 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.362431                       # Nu
 sim_ticks                                362430887000                       # Number of ticks simulated
 final_tick                               362430887000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1947938                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1948018                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2895487158                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 344700                       # Number of bytes of host memory used
-host_seconds                                   125.17                       # Real time elapsed on the host
+host_inst_rate                                 628265                       # Simulator instruction rate (inst/s)
+host_op_rate                                   628291                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              933876298                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 354916                       # Number of bytes of host memory used
+host_seconds                                   388.09                       # Real time elapsed on the host
 sim_insts                                   243825163                       # Number of instructions simulated
 sim_ops                                     243835278                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     1001472                       # Number of bytes read from this memory
@@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          882                       # number of ReadReq MSHR misses
@@ -173,8 +173,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       935237                       # number of writebacks
@@ -289,8 +289,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks           40                       # number of writebacks
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index f9591bc5c..fdde370ab 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -159,7 +158,7 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[3]
+port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.fuPool]
 type=FUPool
@@ -426,7 +425,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -447,7 +446,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -455,8 +454,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[4]
-pio=system.membus.port[3]
+int_master=system.membus.slave[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -467,11 +467,11 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[2]
+port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -491,8 +491,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[4]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -502,7 +502,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -510,7 +511,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
+cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
@@ -534,15 +535,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:268435455
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index f02df016b..b77e7822e 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:18:12
-gem5 started Feb 12 2012 18:37:07
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:53:18
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 652133ba6..ce63fccea 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.067367                       # Nu
 sim_ticks                                 67367177000                       # Number of ticks simulated
 final_tick                                67367177000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 124120                       # Simulator instruction rate (inst/s)
-host_op_rate                                   218555                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               52925417                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 355732                       # Number of bytes of host memory used
-host_seconds                                  1272.87                       # Real time elapsed on the host
+host_inst_rate                                  46452                       # Simulator instruction rate (inst/s)
+host_op_rate                                    81794                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               19807267                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 361860                       # Number of bytes of host memory used
+host_seconds                                  3401.13                       # Real time elapsed on the host
 sim_insts                                   157988582                       # Number of instructions simulated
 sim_ops                                     278192519                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     3905024                       # Number of bytes read from this memory
@@ -331,8 +331,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          315                       # number of ReadReq MSHR hits
@@ -413,8 +413,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      1879081                       # number of writebacks
@@ -536,8 +536,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        13993                       # number of writebacks
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
index 15b801d93..de9967710 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -69,7 +69,7 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.membus.port[5]
+port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -77,8 +77,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[7]
-pio=system.membus.port[6]
+int_master=system.membus.slave[5]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -89,7 +90,7 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.membus.port[4]
+port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -97,7 +98,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic
+cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -121,15 +122,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:268435455
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
index a3234c831..356a4d94b 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:53
-gem5 started Feb 11 2012 14:18:06
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:53:55
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index e6ec29e4a..458361cdf 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.168950                       # Nu
 sim_ticks                                168950072000                       # Number of ticks simulated
 final_tick                               168950072000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1605694                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2827368                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1717098424                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 344660                       # Number of bytes of host memory used
-host_seconds                                    98.39                       # Real time elapsed on the host
+host_inst_rate                                 603392                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1062476                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              645256130                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 350676                       # Number of bytes of host memory used
+host_seconds                                   261.83                       # Real time elapsed on the host
 sim_insts                                   157988583                       # Number of instructions simulated
 sim_ops                                     278192520                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  2458815679                       # Number of bytes read from this memory
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
index 426472e17..6201e2d0e 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -91,11 +90,11 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[3]
+port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -116,7 +115,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -124,8 +123,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[4]
-pio=system.membus.port[3]
+int_master=system.membus.slave[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -136,11 +136,11 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[2]
+port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -160,8 +160,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[4]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -171,7 +171,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -179,7 +180,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
+cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -203,15 +204,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:268435455
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
index 064d05227..e263a1050 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:53
-gem5 started Feb 11 2012 14:19:55
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:54:19
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index a57ebe258..763b60bb2 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.370011                       # Nu
 sim_ticks                                370010840000                       # Number of ticks simulated
 final_tick                               370010840000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 912216                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1606265                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2136418129                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 353708                       # Number of bytes of host memory used
-host_seconds                                   173.19                       # Real time elapsed on the host
+host_inst_rate                                 306323                       # Simulator instruction rate (inst/s)
+host_op_rate                                   539385                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              717411215                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 359620                       # Number of bytes of host memory used
+host_seconds                                   515.76                       # Real time elapsed on the host
 sim_insts                                   157988583                       # Number of instructions simulated
 sim_ops                                     278192520                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     4900800                       # Number of bytes read from this memory
@@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          808                       # number of ReadReq MSHR misses
@@ -163,8 +163,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      1437080                       # number of writebacks
@@ -270,8 +270,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        29460                       # number of writebacks
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index d81753d20..08e7e2cb5 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -509,14 +508,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
+cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -537,8 +536,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
index 7c2d8a83b..5e99fb7a2 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:04:44
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:25:50
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -67,4 +67,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 233057542500 because target called exit()
+Exiting @ tick 233090215000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index e5e06c89f..da196343b 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,26 +1,26 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.233058                       # Number of seconds simulated
-sim_ticks                                233057542500                       # Number of ticks simulated
-final_tick                               233057542500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.233090                       # Number of seconds simulated
+sim_ticks                                233090215000                       # Number of ticks simulated
+final_tick                               233090215000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 173099                       # Simulator instruction rate (inst/s)
-host_op_rate                                   194997                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               79264326                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229800                       # Number of bytes of host memory used
-host_seconds                                  2940.26                       # Real time elapsed on the host
-sim_insts                                   508954936                       # Number of instructions simulated
-sim_ops                                     573341497                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    15214144                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 246208                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 10947904                       # Number of bytes written to this memory
-system.physmem.num_reads                       237721                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      171061                       # Number of write requests responded to by this memory
+host_inst_rate                                  75004                       # Simulator instruction rate (inst/s)
+host_op_rate                                    84493                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               34350324                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237136                       # Number of bytes of host memory used
+host_seconds                                  6785.68                       # Real time elapsed on the host
+sim_insts                                   508954971                       # Number of instructions simulated
+sim_ops                                     573341532                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read                    15203328                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 248448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 10942400                       # Number of bytes written to this memory
+system.physmem.num_reads                       237552                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      170975                       # Number of write requests responded to by this memory
 system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       65280633                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                   1056426                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      46975111                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     112255745                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read                       65225080                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   1065888                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      46944914                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     112169994                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -64,604 +64,604 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        466115086                       # number of cpu cycles simulated
+system.cpu.numCycles                        466180431                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                200399400                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          157559949                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           13227368                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             107557824                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 98829929                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                200556895                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          157701783                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           13206687                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             107805920                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 98841530                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                 10084316                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect             2451057                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          137234241                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      896616118                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   200399400                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          108914245                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     197636410                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                54052361                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               88992455                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  124                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1657                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 126860220                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               3882835                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          462293499                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.263975                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.101557                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                 10112840                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect             2450569                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          137282908                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      897241370                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   200556895                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          108954370                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     197651477                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                54011479                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               89011796                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  101                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1558                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 126941311                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               3919273                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          462356637                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.264737                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.102062                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                264670388     57.25%     57.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 16165090      3.50%     60.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 21531844      4.66%     65.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 22983454      4.97%     70.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 24508471      5.30%     75.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 13134616      2.84%     78.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 13371052      2.89%     81.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 12920313      2.79%     84.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 73008271     15.79%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                264718484     57.25%     57.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 16102215      3.48%     60.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 21528039      4.66%     65.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 22972257      4.97%     70.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 24519479      5.30%     75.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 13176471      2.85%     78.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 13363017      2.89%     81.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 12910820      2.79%     84.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 73065855     15.80%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            462293499                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.429935                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.923594                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                152295850                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              84600682                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 182545472                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               4580461                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               38271034                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             32275508                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                160463                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              977106792                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                311018                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               38271034                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                165689191                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 6700759                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       64642468                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 173582675                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              13407372                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              899108485                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1442                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2810546                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               7739563                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              106                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1049429059                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3915911188                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3915906253                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              4935                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             672199832                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                377229227                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            5987863                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        5982547                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  72814411                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            187298810                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            75062120                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          17028922                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         10874751                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  806565254                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             6815793                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 700720615                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1613210                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       237113606                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    598814504                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        3094720                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     462293499                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.515748                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.710183                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            462356637                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.430213                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.924665                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                152349400                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              84610781                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 182515551                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               4600527                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               38280378                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             32264539                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                131208                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              977458438                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                310007                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               38280378                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                165802120                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 6702227                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       64599197                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 173513863                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              13458852                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              899149269                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1570                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2810073                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               7803626                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               65                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1049469958                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3916326628                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3916321968                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              4660                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             672199888                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                377270070                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            5958245                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        5953011                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  72720727                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            187283500                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            75086036                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          17235466                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11153184                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  806543834                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             6798395                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 700450406                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1593652                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       237057994                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    599635413                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        3077315                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     462356637                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.514957                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.708817                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           192936549     41.73%     41.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            75135766     16.25%     57.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            69228865     14.98%     72.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            61089071     13.21%     86.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            35380643      7.65%     93.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            15554118      3.36%     97.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             7568076      1.64%     98.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             4045000      0.87%     99.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1355411      0.29%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           192897981     41.72%     41.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            75235662     16.27%     57.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            69361266     15.00%     72.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            61039846     13.20%     86.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            35358169      7.65%     93.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            15549191      3.36%     97.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             7530638      1.63%     98.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             4060857      0.88%     99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1323027      0.29%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       462293499                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       462356637                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  467117      4.69%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                6749256     67.80%     72.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2738977     27.51%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  463542      4.68%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                6723177     67.88%     72.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2717455     27.44%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             472287152     67.40%     67.40% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               386091      0.06%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 198      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            162565842     23.20%     90.66% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            65481329      9.34%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             472173393     67.41%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               385744      0.06%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 178      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.47% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            162454570     23.19%     90.66% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            65436518      9.34%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              700720615                       # Type of FU issued
-system.cpu.iq.rate                           1.503321                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     9955350                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014207                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1875302857                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1050553482                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    668216510                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 432                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                858                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total              700450406                       # Type of FU issued
+system.cpu.iq.rate                           1.502531                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     9904174                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014140                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1874754883                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1050459229                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    668042045                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 392                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                808                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              710675747                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     218                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          9109880                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              710354382                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     198                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          9116513                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     60525813                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        50692                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        63405                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     17458202                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     60510496                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        49356                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        63473                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     17482111                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        20818                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           376                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        20858                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           384                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               38271034                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2890868                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                175492                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           822161545                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           8144996                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             187298810                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             75062120                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            5327019                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  85808                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  8514                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          63405                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       10568276                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      7702731                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             18271007                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             681861282                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             155223597                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          18859333                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               38280378                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2896329                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                176068                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           822095360                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           8083425                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             187283500                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             75086036                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            5309620                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  85965                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  9347                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          63473                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       10562567                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      7713138                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             18275705                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             681639675                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             155144326                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          18810731                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       8780498                       # number of nop insts executed
-system.cpu.iew.exec_refs                    219185272                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                141958281                       # Number of branches executed
-system.cpu.iew.exec_stores                   63961675                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.462860                       # Inst execution rate
-system.cpu.iew.wb_sent                      673014173                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     668216526                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 381765084                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 656387982                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       8753131                       # number of nop insts executed
+system.cpu.iew.exec_refs                    219063000                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                141943727                       # Number of branches executed
+system.cpu.iew.exec_stores                   63918674                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.462180                       # Inst execution rate
+system.cpu.iew.wb_sent                      672829860                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     668042061                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 381675027                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 656276447                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.433587                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.581615                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.433012                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.581577                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      510298820                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps        574685381                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       247493136                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         3721073                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          15415046                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    424022466                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.355318                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.071268                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      510298855                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        574685416                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       247426936                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         3721080                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          15423001                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    424076260                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.355146                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.070427                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    206316988     48.66%     48.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    102533575     24.18%     72.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     40145036      9.47%     82.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     19513900      4.60%     86.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     17437160      4.11%     91.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7239208      1.71%     92.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      7753458      1.83%     94.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3810522      0.90%     95.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     19272619      4.55%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    206251262     48.64%     48.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    102654685     24.21%     72.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     40133314      9.46%     82.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     19523005      4.60%     86.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     17475751      4.12%     91.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7238789      1.71%     92.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      7738360      1.82%     94.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3820773      0.90%     95.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     19240321      4.54%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    424022466                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            510298820                       # Number of instructions committed
-system.cpu.commit.committedOps              574685381                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    424076260                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            510298855                       # Number of instructions committed
+system.cpu.commit.committedOps              574685416                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      184376915                       # Number of memory references committed
-system.cpu.commit.loads                     126772997                       # Number of loads committed
+system.cpu.commit.refs                      184376929                       # Number of memory references committed
+system.cpu.commit.loads                     126773004                       # Number of loads committed
 system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
-system.cpu.commit.branches                  120192182                       # Number of branches committed
+system.cpu.commit.branches                  120192189                       # Number of branches committed
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 473701465                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 473701493                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              19272619                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              19240321                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1226921226                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1682775882                       # The number of ROB writes
-system.cpu.timesIdled                           98525                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         3821587                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   508954936                       # Number of Instructions Simulated
-system.cpu.committedOps                     573341497                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             508954936                       # Number of Instructions Simulated
-system.cpu.cpi                               0.915828                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.915828                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.091908                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.091908                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3163594515                       # number of integer regfile reads
-system.cpu.int_regfile_writes               777373809                       # number of integer regfile writes
+system.cpu.rob.rob_reads                   1226941153                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1682652305                       # The number of ROB writes
+system.cpu.timesIdled                           99109                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         3823794                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   508954971                       # Number of Instructions Simulated
+system.cpu.committedOps                     573341532                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             508954971                       # Number of Instructions Simulated
+system.cpu.cpi                               0.915956                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.915956                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.091755                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.091755                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3162535433                       # number of integer regfile reads
+system.cpu.int_regfile_writes               777163195                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads              1130092901                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                4463966                       # number of misc regfile writes
-system.cpu.icache.replacements                  16105                       # number of replacements
-system.cpu.icache.tagsinuse               1117.727093                       # Cycle average of tags in use
-system.cpu.icache.total_refs                126840323                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  17981                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                7054.130638                       # Average number of references to valid blocks.
+system.cpu.misc_regfile_reads              1130648260                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                4463980                       # number of misc regfile writes
+system.cpu.icache.replacements                  16198                       # number of replacements
+system.cpu.icache.tagsinuse               1123.010204                       # Cycle average of tags in use
+system.cpu.icache.total_refs                126921132                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  18053                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                7030.473162                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1117.727093                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.545765                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.545765                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    126840329                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       126840329                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     126840329                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        126840329                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    126840329                       # number of overall hits
-system.cpu.icache.overall_hits::total       126840329                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        19891                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         19891                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        19891                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          19891                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        19891                       # number of overall misses
-system.cpu.icache.overall_misses::total         19891                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    267894500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    267894500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    267894500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    267894500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    267894500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    267894500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    126860220                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    126860220                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    126860220                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    126860220                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    126860220                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    126860220                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000157                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000157                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000157                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13468.126288                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13468.126288                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13468.126288                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1123.010204                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.548345                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.548345                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    126921167                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       126921167                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     126921167                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        126921167                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    126921167                       # number of overall hits
+system.cpu.icache.overall_hits::total       126921167                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        20144                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         20144                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        20144                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          20144                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        20144                       # number of overall misses
+system.cpu.icache.overall_misses::total         20144                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    271671500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    271671500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    271671500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    271671500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    271671500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    271671500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    126941311                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    126941311                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    126941311                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    126941311                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    126941311                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    126941311                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000159                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000159                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000159                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13486.472399                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13486.472399                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13486.472399                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks            1                       # number of writebacks
-system.cpu.icache.writebacks::total                 1                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1759                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1759                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1759                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1759                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1759                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1759                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        18132                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        18132                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        18132                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        18132                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        18132                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        18132                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    171640500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    171640500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    171640500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    171640500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    171640500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    171640500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000143                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000143                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000143                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9466.164792                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9466.164792                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9466.164792                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks            8                       # number of writebacks
+system.cpu.icache.writebacks::total                 8                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1838                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1838                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1838                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1838                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1838                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1838                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        18306                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        18306                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        18306                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        18306                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        18306                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        18306                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    173356500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    173356500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    173356500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    173356500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    173356500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    173356500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000144                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000144                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000144                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9469.927892                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9469.927892                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9469.927892                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1204809                       # number of replacements
-system.cpu.dcache.tagsinuse               4052.906677                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                197317737                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1208905                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 163.220217                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                1204660                       # number of replacements
+system.cpu.dcache.tagsinuse               4052.912718                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                197226176                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1208756                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 163.164589                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             5518270000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4052.906677                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.989479                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.989479                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    140063979                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       140063979                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     52782968                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       52782968                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      2238489                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      2238489                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      2231982                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      2231982                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     192846947                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        192846947                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    192846947                       # number of overall hits
-system.cpu.dcache.overall_hits::total       192846947                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1318830                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1318830                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1456338                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1456338                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data           78                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total           78                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2775168                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2775168                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2775168                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2775168                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  15287682000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  15287682000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  25164058992                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  25164058992                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       845500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       845500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  40451740992                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  40451740992                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  40451740992                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  40451740992                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    141382809                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    141382809                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::cpu.data    4052.912718                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.989481                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.989481                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    139976270                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       139976270                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     52778956                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       52778956                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      2238371                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      2238371                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      2231989                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      2231989                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     192755226                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        192755226                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    192755226                       # number of overall hits
+system.cpu.dcache.overall_hits::total       192755226                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1318997                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1318997                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1460350                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1460350                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           74                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           74                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      2779347                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2779347                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2779347                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2779347                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  15287634500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  15287634500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  25192123491                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  25192123491                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       676500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       676500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  40479757991                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  40479757991                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  40479757991                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  40479757991                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    141295267                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    141295267                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      2238567                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      2238567                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      2231982                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      2231982                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    195622115                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    195622115                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    195622115                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    195622115                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009328                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.026850                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000035                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.014186                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.014186                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11591.851869                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17278.996354                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10839.743590                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14576.321503                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14576.321503                       # average overall miss latency
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      2238445                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      2238445                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      2231989                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      2231989                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    195534573                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    195534573                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    195534573                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    195534573                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009335                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.026924                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000033                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.014214                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.014214                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11590.348196                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17250.743651                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9141.891892                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14564.485108                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14564.485108                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       602000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       560500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              92                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets  6543.478261                       # average number of cycles each access was blocked
+system.cpu.dcache.blocked::no_targets              94                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets  5962.765957                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1073322                       # number of writebacks
-system.cpu.dcache.writebacks::total           1073322                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       451055                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       451055                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1115056                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1115056                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           78                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           78                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1566111                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1566111                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1566111                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1566111                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       867775                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       867775                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       341282                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       341282                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1209057                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1209057                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1209057                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1209057                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6208585000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6208585000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4381340497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4381340497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10589925497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  10589925497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10589925497                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10589925497                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006138                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006292                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006181                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006181                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7154.602287                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12837.889185                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8758.830640                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8758.830640                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1073398                       # number of writebacks
+system.cpu.dcache.writebacks::total           1073398                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       451124                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       451124                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1119210                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1119210                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           74                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           74                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1570334                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1570334                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1570334                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1570334                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       867873                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       867873                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       341140                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       341140                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1209013                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1209013                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1209013                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1209013                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6213938000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6213938000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4372891497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4372891497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10586829497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  10586829497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10586829497                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10586829497                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006142                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006290                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006183                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006183                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7159.962345                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12818.466017                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8756.588636                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8756.588636                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                218501                       # number of replacements
-system.cpu.l2cache.tagsinuse             20930.395337                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1557466                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                238907                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  6.519131                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          170551572000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 13694.941090                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    198.526640                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   7036.927606                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.417936                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.006059                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.214750                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.638745                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst        14165                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       742446                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         756611                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1073323                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1073323                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          110                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          110                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       232553                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       232553                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        14165                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       974999                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          989164                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        14165                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       974999                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         989164                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3852                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       124612                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       128464                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           33                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           33                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       109285                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       109285                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3852                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       233897                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        237749                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3852                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       233897                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       237749                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    132071500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   4261496000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   4393567500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       205000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       205000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3742208000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   3742208000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    132071500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   8003704000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   8135775500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    132071500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   8003704000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   8135775500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        18017                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       867058                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       885075                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1073323                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1073323                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          143                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          143                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       341838                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       341838                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        18017                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1208896                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1226913                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        18017                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1208896                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1226913                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.213798                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.143718                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.230769                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.319698                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.213798                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.193480                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.213798                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.193480                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34286.474559                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34198.118961                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  6212.121212                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34242.649952                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34286.474559                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34218.925424                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34286.474559                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34218.925424                       # average overall miss latency
+system.cpu.l2cache.replacements                218347                       # number of replacements
+system.cpu.l2cache.tagsinuse             20950.026820                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1558196                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                238767                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  6.526011                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          170531011000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 13687.762920                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    201.638936                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   7060.624965                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.417717                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.006154                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.215473                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.639344                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        14281                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       742482                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         756763                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1073406                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1073406                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          203                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          203                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       232563                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       232563                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        14281                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       975045                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          989326                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        14281                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       975045                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         989326                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3887                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       124728                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       128615                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           48                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           48                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       108968                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       108968                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3887                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       233696                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        237583                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3887                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       233696                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       237583                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    133254500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   4265335000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   4398589500                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       411500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       411500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3731222000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3731222000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    133254500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   7996557000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   8129811500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    133254500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   7996557000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   8129811500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        18168                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       867210                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       885378                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1073406                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1073406                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          251                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          251                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       341531                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       341531                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        18168                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1208741                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1226909                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        18168                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1208741                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1226909                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.213948                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.143827                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.191235                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.319057                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.213948                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.193338                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.213948                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.193338                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34282.094160                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34197.092874                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  8572.916667                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34241.447030                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34282.094160                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34217.774374                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34282.094160                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34217.774374                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       171061                       # number of writebacks
-system.cpu.l2cache.writebacks::total           171061                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       170975                       # number of writebacks
+system.cpu.l2cache.writebacks::total           170975                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            5                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           22                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           27                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           25                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           30                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           22                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           27                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           25                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           30                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           22                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           27                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3847                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       124590                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       128437                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           33                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           33                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       109285                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       109285                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3847                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       233875                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       237722                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3847                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       233875                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       237722                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    119582500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   3866885000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3986467500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1024500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1024500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3388776000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3388776000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    119582500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7255661000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   7375243500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    119582500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7255661000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   7375243500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.213521                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.143693                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.230769                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.319698                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.213521                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.193462                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.213521                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.193462                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31084.611385                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.880970                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31045.454545                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.610514                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31084.611385                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.670764                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31084.611385                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.670764                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data           25                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           30                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3882                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       124703                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       128585                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           48                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           48                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       108968                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       108968                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3882                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       233671                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       237553                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3882                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       233671                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       237553                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    120642000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   3870272500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3990914500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1489500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1489500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3378939500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3378939500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    120642000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7249212000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   7369854000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    120642000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7249212000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   7369854000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.213672                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.143798                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.191235                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.319057                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.213672                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.193318                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.213672                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.193318                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31077.279753                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31035.921349                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.250000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.548381                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31077.279753                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.156489                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31077.279753                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.156489                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
index c2570b640..6e34c6137 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -95,14 +95,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic
+cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -123,8 +123,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
index 305853526..61ef97f09 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:09:21
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:27:44
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
index b71701baf..4ec8704b3 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.290499                       # Nu
 sim_ticks                                290498972000                       # Number of ticks simulated
 final_tick                               290498972000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2826052                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3185244                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1620598119                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217292                       # Number of bytes of host memory used
-host_seconds                                   179.25                       # Real time elapsed on the host
+host_inst_rate                                1142576                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1287798                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              655209825                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224168                       # Number of bytes of host memory used
+host_seconds                                   443.37                       # Real time elapsed on the host
 sim_insts                                   506581615                       # Number of instructions simulated
 sim_ops                                     570968176                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  2489298238                       # Number of bytes read from this memory
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
index eb4eafcdf..77531d0fb 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -178,14 +177,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
+cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -206,8 +205,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
index 3920067a6..22208540d 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:11:24
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:29:57
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index 97f343640..8678fa0ad 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.722234                       # Nu
 sim_ticks                                722234364000                       # Number of ticks simulated
 final_tick                               722234364000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1807546                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2036799                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2585159889                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226208                       # Number of bytes of host memory used
-host_seconds                                   279.38                       # Real time elapsed on the host
+host_inst_rate                                 593765                       # Simulator instruction rate (inst/s)
+host_op_rate                                   669073                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              849204818                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 233356                       # Number of bytes of host memory used
+host_seconds                                   850.48                       # Real time elapsed on the host
 sim_insts                                   504986861                       # Number of instructions simulated
 sim_ops                                     569034848                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    14797056                       # Number of bytes read from this memory
@@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11521                       # number of ReadReq MSHR misses
@@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      1025440                       # number of writebacks
@@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       172302                       # number of writebacks
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
index 9b1d88e31..1999a5e16 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -159,7 +158,7 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[3]
+port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.fuPool]
 type=FUPool
@@ -426,7 +425,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -447,7 +446,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -455,8 +454,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[4]
-pio=system.membus.port[3]
+int_master=system.membus.slave[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -467,11 +467,11 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[2]
+port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -491,8 +491,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[4]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -502,7 +502,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -510,7 +511,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
+cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
@@ -534,15 +535,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
index 447926c85..17ab966f1 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:18:12
-gem5 started Feb 12 2012 18:44:57
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:55:07
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index 2a0c6a8f9..bb5fef875 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.460108                       # Nu
 sim_ticks                                460107924500                       # Number of ticks simulated
 final_tick                               460107924500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 106471                       # Simulator instruction rate (inst/s)
-host_op_rate                                   196876                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59244607                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 257468                       # Number of bytes of host memory used
-host_seconds                                  7766.24                       # Real time elapsed on the host
+host_inst_rate                                  59697                       # Simulator instruction rate (inst/s)
+host_op_rate                                   110386                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               33217787                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263000                       # Number of bytes of host memory used
+host_seconds                                 13851.25                       # Real time elapsed on the host
 sim_insts                                   826877144                       # Number of instructions simulated
 sim_ops                                    1528988756                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    37486912                       # Number of bytes read from this memory
@@ -331,8 +331,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            8                       # number of writebacks
@@ -415,8 +415,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      2228961                       # number of writebacks
@@ -543,8 +543,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       411215                       # number of writebacks
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
index 304b98194..83c21c0e9 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -69,7 +69,7 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.membus.port[5]
+port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -77,8 +77,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[7]
-pio=system.membus.port[6]
+int_master=system.membus.slave[5]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -89,7 +90,7 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.membus.port[4]
+port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -97,7 +98,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic
+cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -121,15 +122,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
index 80f8eeac5..6ca36871d 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:53
-gem5 started Feb 11 2012 14:26:26
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:55:18
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 8da8b6e9b..4c0e660f2 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.885229                       # Nu
 sim_ticks                                885229360000                       # Number of ticks simulated
 final_tick                               885229360000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1663979                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3076883                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1781404357                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214024                       # Number of bytes of host memory used
-host_seconds                                   496.93                       # Real time elapsed on the host
+host_inst_rate                                 614441                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1136170                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              657801730                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219436                       # Number of bytes of host memory used
+host_seconds                                  1345.74                       # Real time elapsed on the host
 sim_insts                                   826877145                       # Number of instructions simulated
 sim_ops                                    1528988757                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                 10832432532                       # Number of bytes read from this memory
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
index 36ec559e8..557746b22 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -91,11 +90,11 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[3]
+port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -116,7 +115,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -124,8 +123,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[4]
-pio=system.membus.port[3]
+int_master=system.membus.slave[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -136,11 +136,11 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[2]
+port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -160,8 +160,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[4]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -171,7 +171,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -179,7 +180,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
+cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -203,15 +204,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
index a07142e7a..d62454745 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:53
-gem5 started Feb 11 2012 14:34:54
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:56:26
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index aa053a273..235d6de24 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.658730                       # Nu
 sim_ticks                                1658729604000                       # Number of ticks simulated
 final_tick                               1658729604000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1021382                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1888649                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2048908881                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222932                       # Number of bytes of host memory used
-host_seconds                                   809.57                       # Real time elapsed on the host
+host_inst_rate                                 332704                       # Simulator instruction rate (inst/s)
+host_op_rate                                   615206                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              667409022                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228396                       # Number of bytes of host memory used
+host_seconds                                  2485.33                       # Real time elapsed on the host
 sim_insts                                   826877145                       # Number of instructions simulated
 sim_ops                                    1528988757                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    37094976                       # Number of bytes read from this memory
@@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         2814                       # number of ReadReq MSHR misses
@@ -163,8 +163,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      2223170                       # number of writebacks
@@ -273,8 +273,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       411709                       # number of writebacks
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
index 2ad80ff6d..ad08e6373 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -41,7 +40,6 @@ choiceCtrBits=2
 choicePredictorSize=8192
 clock=500
 cpu_id=0
-dataMemPort=dcache_port
 defer_registration=false
 div16Latency=1
 div16RepeatRate=1
@@ -56,7 +54,6 @@ do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
-fetchMemPort=icache_port
 functionTrace=false
 functionTraceStart=0
 function_trace=false
@@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -115,7 +112,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -123,7 +120,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -144,7 +141,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -155,7 +152,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -175,8 +172,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -186,7 +183,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -194,7 +192,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
 egid=100
 env=
 errout=cerr
@@ -218,15 +216,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
index 371dd4693..56d057ebd 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 17:34:00
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:36:55
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
index 6b6e927bf..28e031d9f 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.141175                       # Nu
 sim_ticks                                141175129500                       # Number of ticks simulated
 final_tick                               141175129500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 157275                       # Simulator instruction rate (inst/s)
-host_op_rate                                   157275                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               55694402                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215928                       # Number of bytes of host memory used
-host_seconds                                  2534.82                       # Real time elapsed on the host
+host_inst_rate                                  60144                       # Simulator instruction rate (inst/s)
+host_op_rate                                    60144                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               21298240                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221000                       # Number of bytes of host memory used
+host_seconds                                  6628.49                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      468992                       # Number of bytes read from this memory
@@ -56,30 +56,6 @@ system.cpu.workload.num_syscalls                  215                       # Nu
 system.cpu.numCycles                        282350260                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                     281921224                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
-system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                            6799                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        13475974                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                        268874286                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         95.227214                       # Percentage of cycles cpu is active
-system.cpu.comLoads                          94754489                       # Number of Load instructions committed
-system.cpu.comStores                         73520729                       # Number of Store instructions committed
-system.cpu.comBranches                       44587532                       # Number of Branches instructions committed
-system.cpu.comNops                           23089775                       # Number of Nop instructions committed
-system.cpu.comNonSpec                             215                       # Number of Non-Speculative instructions committed
-system.cpu.comInts                          112239074                       # Number of Integer instructions committed
-system.cpu.comFloats                         50439198                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                   398664595                       # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps                     398664595                       # Number of Ops committed (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total             398664595                       # Number of Instructions committed (Total)
-system.cpu.cpi                               0.708240                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         0.708240                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.411951                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         1.411951                       # IPC: Total IPC of All Threads
 system.cpu.branch_predictor.lookups          53870351                       # Number of BP lookups
 system.cpu.branch_predictor.condPredicted     30921654                       # Number of conditional branches predicted
 system.cpu.branch_predictor.condIncorrect     16037209                       # Number of conditional branches incorrect
@@ -106,6 +82,30 @@ system.cpu.execution_unit.mispredictPct     35.966429                       # Pe
 system.cpu.execution_unit.executions        205750873                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies           2124330                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.contextSwitches                          1                       # Number of context switches
+system.cpu.threadCycles                     281921224                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled                            6799                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        13475974                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                        268874286                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         95.227214                       # Percentage of cycles cpu is active
+system.cpu.comLoads                          94754489                       # Number of Load instructions committed
+system.cpu.comStores                         73520729                       # Number of Store instructions committed
+system.cpu.comBranches                       44587532                       # Number of Branches instructions committed
+system.cpu.comNops                           23089775                       # Number of Nop instructions committed
+system.cpu.comNonSpec                             215                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                          112239074                       # Number of Integer instructions committed
+system.cpu.comFloats                         50439198                       # Number of Floating Point instructions committed
+system.cpu.committedInsts                   398664595                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                     398664595                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total             398664595                       # Number of Instructions committed (Total)
+system.cpu.cpi                               0.708240                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
+system.cpu.cpi_total                         0.708240                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.411951                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
+system.cpu.ipc_total                         1.411951                       # IPC: Total IPC of All Threads
 system.cpu.stage0.idleCycles                 78536322                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                 203813938                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage0.utilization               72.184788                       # Percentage of cycles stage was utilized (processing insts).
@@ -164,7 +164,7 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets        45000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets        45000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
@@ -246,7 +246,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets     82410500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets            1848                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets 44594.426407                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -364,8 +364,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3353                       # number of ReadReq MSHR misses
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
index c359a496a..bf1407a6b 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -419,7 +418,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -440,7 +439,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -451,7 +450,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -471,8 +470,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -482,7 +481,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -490,7 +490,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
 egid=100
 env=
 errout=cerr
@@ -514,15 +514,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
index 39c5315c7..54524760f 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 17:34:05
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:12
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 54f4ab1b0..891e3f52e 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.080257                       # Nu
 sim_ticks                                 80257421500                       # Number of ticks simulated
 final_tick                                80257421500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 261701                       # Simulator instruction rate (inst/s)
-host_op_rate                                   261701                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               55923550                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217092                       # Number of bytes of host memory used
-host_seconds                                  1435.13                       # Real time elapsed on the host
+host_inst_rate                                  93963                       # Simulator instruction rate (inst/s)
+host_op_rate                                    93963                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               20079187                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221872                       # Number of bytes of host memory used
+host_seconds                                  3997.05                       # Real time elapsed on the host
 sim_insts                                   375574808                       # Number of instructions simulated
 sim_ops                                     375574808                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      478528                       # Number of bytes read from this memory
@@ -366,8 +366,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1492                       # number of ReadReq MSHR hits
@@ -453,7 +453,7 @@ system.cpu.dcache.blocked_cycles::no_targets            0
 system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs         2500                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          682                       # number of writebacks
@@ -570,8 +570,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3480                       # number of ReadReq MSHR misses
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index ce995453a..dc447cd7b 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -77,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
index 3f05b7dba..57f8a5318 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:11:11
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:06
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index cdec8f7fd..290084525 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.199332                       # Nu
 sim_ticks                                199332411500                       # Number of ticks simulated
 final_tick                               199332411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4966970                       # Simulator instruction rate (inst/s)
-host_op_rate                                  4966969                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2483485434                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 206672                       # Number of bytes of host memory used
-host_seconds                                    80.26                       # Real time elapsed on the host
+host_inst_rate                                1838180                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1838179                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              919090070                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211568                       # Number of bytes of host memory used
+host_seconds                                   216.88                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  2257107875                       # Number of bytes read from this memory
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
index c8010ddb2..998e07c81 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -120,7 +119,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -159,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
index fe28e85e0..8e7f3829a 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:12:03
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:07
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 0281e5820..852f5134d 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.567343                       # Nu
 sim_ticks                                567343170000                       # Number of ticks simulated
 final_tick                               567343170000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2193403                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2193403                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3121451222                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215564                       # Number of bytes of host memory used
-host_seconds                                   181.76                       # Real time elapsed on the host
+host_inst_rate                                 766770                       # Simulator instruction rate (inst/s)
+host_op_rate                                   766770                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1091197730                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220456                       # Number of bytes of host memory used
+host_seconds                                   519.93                       # Real time elapsed on the host
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_ops                                     398664609                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      459520                       # Number of bytes read from this memory
@@ -118,8 +118,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3673                       # number of ReadReq MSHR misses
@@ -194,8 +194,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          649                       # number of writebacks
@@ -304,8 +304,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3205                       # number of ReadReq MSHR misses
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index 7bb4edd53..1cf41a172 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -509,12 +508,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing
+cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -537,8 +536,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
index 67a784ea7..f0a5e284e 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:12:32
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:35:18
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 12f1040c9..969b86901 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.071775                       # Nu
 sim_ticks                                 71774859500                       # Number of ticks simulated
 final_tick                                71774859500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 200202                       # Simulator instruction rate (inst/s)
-host_op_rate                                   255946                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               52626024                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233120                       # Number of bytes of host memory used
-host_seconds                                  1363.87                       # Real time elapsed on the host
+host_inst_rate                                  69606                       # Simulator instruction rate (inst/s)
+host_op_rate                                    88987                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               18296996                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240272                       # Number of bytes of host memory used
+host_seconds                                  3922.77                       # Real time elapsed on the host
 sim_insts                                   273048474                       # Number of instructions simulated
 sim_ops                                     349076199                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      472896                       # Number of bytes read from this memory
@@ -377,8 +377,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          900                       # number of ReadReq MSHR hits
@@ -473,7 +473,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets       315000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              13                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets 24230.769231                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -598,8 +598,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           10                       # number of ReadReq MSHR hits
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
index dde743a2d..72280076c 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -95,12 +95,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic
+cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -123,8 +123,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
index 7e0d618b4..51d5089a3 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:16:14
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:37:41
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
index e11cb6ba0..30e59a4c3 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.212344                       # Nu
 sim_ticks                                212344048000                       # Number of ticks simulated
 final_tick                               212344048000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1971895                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2520972                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1533561642                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221584                       # Number of bytes of host memory used
-host_seconds                                   138.46                       # Real time elapsed on the host
+host_inst_rate                                 841557                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1075889                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              654486612                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228648                       # Number of bytes of host memory used
+host_seconds                                   324.44                       # Real time elapsed on the host
 sim_insts                                   273037671                       # Number of instructions simulated
 sim_ops                                     349065408                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  1875350709                       # Number of bytes read from this memory
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
index 37b45f338..28132d5a1 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -178,12 +177,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing
+cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -206,8 +205,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
index 0225feba2..85721b4bd 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:16:21
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:38:02
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index 7147319f6..1725766a3 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.525854                       # Nu
 sim_ticks                                525854475000                       # Number of ticks simulated
 final_tick                               525854475000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1189484                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1520711                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2293381880                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230756                       # Number of bytes of host memory used
-host_seconds                                   229.29                       # Real time elapsed on the host
+host_inst_rate                                 425859                       # Simulator instruction rate (inst/s)
+host_op_rate                                   544445                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              821076045                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237820                       # Number of bytes of host memory used
+host_seconds                                   640.45                       # Real time elapsed on the host
 sim_insts                                   272739291                       # Number of instructions simulated
 sim_ops                                     348687131                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      437312                       # Number of bytes read from this memory
@@ -128,8 +128,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15603                       # number of ReadReq MSHR misses
@@ -212,8 +212,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          998                       # number of writebacks
@@ -322,8 +322,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2610                       # number of ReadReq MSHR misses
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index 2d167e65d..16e2e58d3 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -419,7 +418,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -440,7 +439,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -451,7 +450,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -471,8 +470,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -482,7 +481,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -490,7 +490,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
 egid=100
 env=
 errout=cerr
@@ -514,15 +514,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index df01c27da..f9974abd8 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 17:35:37
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:36:56
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 119153a53..936c3a0e4 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.645508                       # Nu
 sim_ticks                                645508416000                       # Number of ticks simulated
 final_tick                               645508416000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 197220                       # Simulator instruction rate (inst/s)
-host_op_rate                                   197220                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               69832178                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217536                       # Number of bytes of host memory used
-host_seconds                                  9243.71                       # Real time elapsed on the host
+host_inst_rate                                 101635                       # Simulator instruction rate (inst/s)
+host_op_rate                                   101635                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               35987047                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222212                       # Number of bytes of host memory used
+host_seconds                                 17937.24                       # Real time elapsed on the host
 sim_insts                                  1823043370                       # Number of instructions simulated
 sim_ops                                    1823043370                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    94795136                       # Number of bytes read from this memory
@@ -367,8 +367,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1356                       # number of ReadReq MSHR hits
@@ -586,7 +586,7 @@ system.cpu.l2cache.blocked_cycles::no_targets            0
 system.cpu.l2cache.blocked::no_mshrs               11                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs  3681.818182                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66898                       # number of writebacks
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index e114fdc81..eadae54f6 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -77,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
index d7926f03a..3888b9787 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:12:42
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:09
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index 4c63884c7..271502b93 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.004711                       # Nu
 sim_ticks                                1004710587000                       # Number of ticks simulated
 final_tick                               1004710587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                5076159                       # Simulator instruction rate (inst/s)
-host_op_rate                                  5076159                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2538627026                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 206544                       # Number of bytes of host memory used
-host_seconds                                   395.77                       # Real time elapsed on the host
+host_inst_rate                                2020056                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2020056                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1010246097                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211516                       # Number of bytes of host memory used
+host_seconds                                   994.52                       # Real time elapsed on the host
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                 11607100996                       # Number of bytes read from this memory
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index 794cf18d1..4f0c26637 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -120,7 +119,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -159,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index 25b995793..c1dffe98f 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:14:25
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:36:56
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index 19236d338..df33397d8 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.813468                       # Nu
 sim_ticks                                2813467842000                       # Number of ticks simulated
 final_tick                               2813467842000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2306294                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2306294                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3229827855                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215660                       # Number of bytes of host memory used
-host_seconds                                   871.09                       # Real time elapsed on the host
+host_inst_rate                                 748813                       # Simulator instruction rate (inst/s)
+host_op_rate                                   748813                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1048668721                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220468                       # Number of bytes of host memory used
+host_seconds                                  2682.89                       # Real time elapsed on the host
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    94708160                       # Number of bytes read from this memory
@@ -119,8 +119,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10596                       # number of ReadReq MSHR misses
@@ -195,8 +195,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       107612                       # number of writebacks
@@ -305,8 +305,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66898                       # number of writebacks
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 131483c9e..046ea4974 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -509,12 +508,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing
+cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -537,8 +536,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
index 310ad361e..5fdff30e2 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:18:43
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:38:05
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 2ea6fdf18..25a59d0b1 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.735495                       # Nu
 sim_ticks                                735495062500                       # Number of ticks simulated
 final_tick                               735495062500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 126424                       # Simulator instruction rate (inst/s)
-host_op_rate                                   172171                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               67166483                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230552                       # Number of bytes of host memory used
-host_seconds                                 10950.33                       # Real time elapsed on the host
+host_inst_rate                                  70506                       # Simulator instruction rate (inst/s)
+host_op_rate                                    96019                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               37458496                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237496                       # Number of bytes of host memory used
+host_seconds                                 19634.93                       # Real time elapsed on the host
 sim_insts                                  1384379503                       # Number of instructions simulated
 sim_ops                                    1885334256                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    94839680                       # Number of bytes read from this memory
@@ -378,8 +378,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          853                       # number of ReadReq MSHR hits
@@ -474,7 +474,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets        81500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets        20375                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -601,8 +601,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66099                       # number of writebacks
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index 0e51a5093..3c449c83d 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -95,12 +95,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic
+cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -123,8 +123,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
index a30e96fb9..d0a53e63c 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:20:21
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:43:17
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index 97c60e977..de6626577 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.945613                       # Nu
 sim_ticks                                945613131000                       # Number of ticks simulated
 final_tick                               945613131000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2176707                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2964374                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1486817392                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218836                       # Number of bytes of host memory used
-host_seconds                                   636.00                       # Real time elapsed on the host
+host_inst_rate                                 910891                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1240507                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              622191267                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 225796                       # Number of bytes of host memory used
+host_seconds                                  1519.81                       # Real time elapsed on the host
 sim_insts                                  1384381614                       # Number of instructions simulated
 sim_ops                                    1885336367                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  8025491315                       # Number of bytes read from this memory
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index 91ae9c597..68de052dd 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -178,12 +177,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing
+cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -206,8 +205,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
index d0e2e4ad0..d3e913037 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:31:08
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:43:48
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index cae7de027..6675fca21 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.369902                       # Nu
 sim_ticks                                2369901960000                       # Number of ticks simulated
 final_tick                               2369901960000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1363943                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1850286                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2339607262                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 227748                       # Number of bytes of host memory used
-host_seconds                                  1012.95                       # Real time elapsed on the host
+host_inst_rate                                 495417                       # Simulator instruction rate (inst/s)
+host_op_rate                                   672068                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              849801430                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 234976                       # Number of bytes of host memory used
+host_seconds                                  2788.77                       # Real time elapsed on the host
 sim_insts                                  1381604347                       # Number of instructions simulated
 sim_ops                                    1874244950                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    94696320                       # Number of bytes read from this memory
@@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19803                       # number of ReadReq MSHR misses
@@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       107259                       # number of writebacks
@@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66099                       # number of writebacks
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index 90c413b65..558bb295e 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -41,7 +40,6 @@ choiceCtrBits=2
 choicePredictorSize=8192
 clock=500
 cpu_id=0
-dataMemPort=dcache_port
 defer_registration=false
 div16Latency=1
 div16RepeatRate=1
@@ -56,7 +54,6 @@ do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
-fetchMemPort=icache_port
 functionTrace=false
 functionTraceStart=0
 function_trace=false
@@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -115,7 +112,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -123,7 +120,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -144,7 +141,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -155,7 +152,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -175,8 +172,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -186,7 +183,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -194,7 +192,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
 egid=100
 env=
 errout=cerr
@@ -218,15 +216,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
index a906c40f3..32687c68b 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 17:38:51
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:07
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index 447e68abd..bbfd1b81d 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.047233                       # Nu
 sim_ticks                                 47232621500                       # Number of ticks simulated
 final_tick                                47232621500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 142426                       # Simulator instruction rate (inst/s)
-host_op_rate                                   142426                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               76149893                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218108                       # Number of bytes of host memory used
-host_seconds                                   620.26                       # Real time elapsed on the host
+host_inst_rate                                  62283                       # Simulator instruction rate (inst/s)
+host_op_rate                                    62283                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               33300358                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223148                       # Number of bytes of host memory used
+host_seconds                                  1418.38                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    11167232                       # Number of bytes read from this memory
@@ -57,30 +57,6 @@ system.cpu.workload.num_syscalls                 4583                       # Nu
 system.cpu.numCycles                         94465244                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                      78066794                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
-system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                          305627                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        24182755                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                         70282489                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         74.400368                       # Percentage of cycles cpu is active
-system.cpu.comLoads                          20276638                       # Number of Load instructions committed
-system.cpu.comStores                         14613377                       # Number of Store instructions committed
-system.cpu.comBranches                       13754477                       # Number of Branches instructions committed
-system.cpu.comNops                            8748916                       # Number of Nop instructions committed
-system.cpu.comNonSpec                            4583                       # Number of Non-Speculative instructions committed
-system.cpu.comInts                           30791227                       # Number of Integer instructions committed
-system.cpu.comFloats                           151453                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                    88340673                       # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps                      88340673                       # Number of Ops committed (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total              88340673                       # Number of Instructions committed (Total)
-system.cpu.cpi                               1.069329                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         1.069329                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.935166                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.935166                       # IPC: Total IPC of All Threads
 system.cpu.branch_predictor.lookups          18828991                       # Number of BP lookups
 system.cpu.branch_predictor.condPredicted     12440560                       # Number of conditional branches predicted
 system.cpu.branch_predictor.condIncorrect      5024685                       # Number of conditional branches incorrect
@@ -107,6 +83,30 @@ system.cpu.execution_unit.mispredictPct     35.681953                       # Pe
 system.cpu.execution_unit.executions         44775654                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies             41107                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.contextSwitches                          1                       # Number of context switches
+system.cpu.threadCycles                      78066794                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled                          305627                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        24182755                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                         70282489                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         74.400368                       # Percentage of cycles cpu is active
+system.cpu.comLoads                          20276638                       # Number of Load instructions committed
+system.cpu.comStores                         14613377                       # Number of Store instructions committed
+system.cpu.comBranches                       13754477                       # Number of Branches instructions committed
+system.cpu.comNops                            8748916                       # Number of Nop instructions committed
+system.cpu.comNonSpec                            4583                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                           30791227                       # Number of Integer instructions committed
+system.cpu.comFloats                           151453                       # Number of Floating Point instructions committed
+system.cpu.committedInsts                    88340673                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                      88340673                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total              88340673                       # Number of Instructions committed (Total)
+system.cpu.cpi                               1.069329                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
+system.cpu.cpi_total                         1.069329                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.935166                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
+system.cpu.ipc_total                         0.935166                       # IPC: Total IPC of All Threads
 system.cpu.stage0.idleCycles                 41039233                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                  53426011                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage0.utilization               56.556262                       # Percentage of cycles stage was utilized (processing insts).
@@ -165,7 +165,7 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets      1485500                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets             122                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets 12176.229508                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
@@ -247,7 +247,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets   6329431500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets          124110                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets 50998.561760                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -365,8 +365,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       120516                       # number of writebacks
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 427d5ea46..e450ba18e 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -419,7 +418,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -440,7 +439,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -451,7 +450,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -471,8 +470,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -482,7 +481,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -490,7 +490,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
 egid=100
 env=
 errout=cerr
@@ -514,15 +514,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
index 4f0567259..9cfde6f31 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 17:42:57
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:40:56
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 3e4315992..451be5b16 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.021303                       # Nu
 sim_ticks                                 21302882000                       # Number of ticks simulated
 final_tick                                21302882000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 238426                       # Simulator instruction rate (inst/s)
-host_op_rate                                   238426                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               63815052                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219800                       # Number of bytes of host memory used
-host_seconds                                   333.82                       # Real time elapsed on the host
+host_inst_rate                                  93477                       # Simulator instruction rate (inst/s)
+host_op_rate                                    93477                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               25019246                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224368                       # Number of bytes of host memory used
+host_seconds                                   851.46                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    11250368                       # Number of bytes read from this memory
@@ -367,8 +367,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4856                       # number of ReadReq MSHR hits
@@ -454,7 +454,7 @@ system.cpu.dcache.blocked_cycles::no_targets            0
 system.cpu.dcache.blocked::no_mshrs                15                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs  6433.333333                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       161705                       # number of writebacks
@@ -572,7 +572,7 @@ system.cpu.l2cache.blocked_cycles::no_targets            0
 system.cpu.l2cache.blocked::no_mshrs               11                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs  2636.363636                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       120528                       # number of writebacks
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index cf8e1051d..a0b57617c 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -77,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
index 0548e6bad..fc113b45a 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:25:10
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-atomic
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:36:56
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index 45c7e3698..d588d935b 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.044221                       # Nu
 sim_ticks                                 44221003000                       # Number of ticks simulated
 final_tick                                44221003000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                5044223                       # Simulator instruction rate (inst/s)
-host_op_rate                                  5044217                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2524999281                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 208636                       # Number of bytes of host memory used
-host_seconds                                    17.51                       # Real time elapsed on the host
+host_inst_rate                                2035147                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2035146                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1018739452                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213644                       # Number of bytes of host memory used
+host_seconds                                    43.41                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   480454939                       # Number of bytes read from this memory
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 4c4894527..7a34ec0b9 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -120,7 +119,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -159,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
index 471c7b55a..10d7a3f16 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:25:32
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:41:54
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index c906eecdf..106052dbf 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.134277                       # Nu
 sim_ticks                                134276988000                       # Number of ticks simulated
 final_tick                               134276988000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2261546                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2261545                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3437525661                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217500                       # Number of bytes of host memory used
-host_seconds                                    39.06                       # Real time elapsed on the host
+host_inst_rate                                 721996                       # Simulator instruction rate (inst/s)
+host_op_rate                                   721996                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1097426166                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222532                       # Number of bytes of host memory used
+host_seconds                                   122.36                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    11121920                       # Number of bytes read from this memory
@@ -119,8 +119,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        76436                       # number of ReadReq MSHR misses
@@ -195,8 +195,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       161222                       # number of writebacks
@@ -305,8 +305,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       120506                       # number of writebacks
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index f2b092df6..9b36bf976 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -509,12 +508,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing
+cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -537,8 +536,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
index 82550ab1e..f9f6b3025 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:35:27
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:44:00
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index aa06eed4d..d1da91b90 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.024561                       # Nu
 sim_ticks                                 24560764000                       # Number of ticks simulated
 final_tick                                24560764000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 175313                       # Simulator instruction rate (inst/s)
-host_op_rate                                   248779                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               60713797                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233096                       # Number of bytes of host memory used
-host_seconds                                   404.53                       # Real time elapsed on the host
+host_inst_rate                                  54926                       # Simulator instruction rate (inst/s)
+host_op_rate                                    77943                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               19021903                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240316                       # Number of bytes of host memory used
+host_seconds                                  1291.18                       # Real time elapsed on the host
 sim_insts                                    70920072                       # Number of instructions simulated
 sim_ops                                     100639320                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     8687232                       # Number of bytes read from this memory
@@ -378,8 +378,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1474                       # number of ReadReq MSHR hits
@@ -474,7 +474,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets       203500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              11                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets        18500                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -604,8 +604,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        88463                       # number of writebacks
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
index 141b1144a..40b740299 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -95,12 +95,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic
+cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -123,8 +123,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
index fe99a5f18..6e02c2f67 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:42:22
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:44:19
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 3df28546e..015123589 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.053932                       # Nu
 sim_ticks                                 53932162000                       # Number of ticks simulated
 final_tick                                53932162000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2274185                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3227279                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1729602132                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221076                       # Number of bytes of host memory used
-host_seconds                                    31.18                       # Real time elapsed on the host
+host_inst_rate                                 956394                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1357212                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              727373394                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228240                       # Number of bytes of host memory used
+host_seconds                                    74.15                       # Real time elapsed on the host
 sim_insts                                    70913189                       # Number of instructions simulated
 sim_ops                                     100632437                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   419153654                       # Number of bytes read from this memory
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
index ddcce578b..6148c904a 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -178,12 +177,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing
+cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -206,8 +205,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
index e1c016ba1..c236a6c17 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:43:04
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:45:44
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index a19c3fe41..f30f52adf 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.133117                       # Nu
 sim_ticks                                133117442000                       # Number of ticks simulated
 final_tick                               133117442000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1304890                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1850368                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2468304183                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230248                       # Number of bytes of host memory used
-host_seconds                                    53.93                       # Real time elapsed on the host
+host_inst_rate                                 457869                       # Simulator instruction rate (inst/s)
+host_op_rate                                   649270                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              866095863                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237424                       # Number of bytes of host memory used
+host_seconds                                   153.70                       # Real time elapsed on the host
 sim_insts                                    70373636                       # Number of instructions simulated
 sim_ops                                      99791663                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     8570688                       # Number of bytes read from this memory
@@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        18908                       # number of ReadReq MSHR misses
@@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       122808                       # number of writebacks
@@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        88449                       # number of writebacks
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 4295b5950..31ea2a719 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -77,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex bendian.raw
-cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic
+cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
index 7e99d8ae7..3e58ac7a5 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 14:00:16
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:45:58
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index 12070ccfb..7d80c12bc 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.068149                       # Nu
 sim_ticks                                 68148678500                       # Number of ticks simulated
 final_tick                                68148678500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3965699                       # Simulator instruction rate (inst/s)
-host_op_rate                                  4017046                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2010855033                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211680                       # Number of bytes of host memory used
-host_seconds                                    33.89                       # Real time elapsed on the host
+host_inst_rate                                1477309                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1496437                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              749087650                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221876                       # Number of bytes of host memory used
+host_seconds                                    90.98                       # Real time elapsed on the host
 sim_insts                                   134398975                       # Number of instructions simulated
 sim_ops                                     136139203                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   685773693                       # Number of bytes read from this memory
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 2507c0ed4..29c16b40d 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=SparcInterrupts
@@ -120,7 +119,7 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -159,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex bendian.raw
-cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing
+cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
index a6a3d32b7..e764a6213 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 14:01:00
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:46:17
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index b24bd2c93..3a7d1778b 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.202942                       # Nu
 sim_ticks                                202941992000                       # Number of ticks simulated
 final_tick                               202941992000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1927976                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1952939                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2911235123                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220544                       # Number of bytes of host memory used
-host_seconds                                    69.71                       # Real time elapsed on the host
+host_inst_rate                                 667455                       # Simulator instruction rate (inst/s)
+host_op_rate                                   676097                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1007854644                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230768                       # Number of bytes of host memory used
+host_seconds                                   201.36                       # Real time elapsed on the host
 sim_insts                                   134398975                       # Number of instructions simulated
 sim_ops                                     136139203                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     8970304                       # Number of bytes read from this memory
@@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst       187024                       # number of ReadReq MSHR misses
@@ -173,8 +173,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       118818                       # number of writebacks
@@ -289,8 +289,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        87265                       # number of writebacks
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
index 103775415..7c9012664 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -41,7 +40,6 @@ choiceCtrBits=2
 choicePredictorSize=8192
 clock=500
 cpu_id=0
-dataMemPort=dcache_port
 defer_registration=false
 div16Latency=1
 div16RepeatRate=1
@@ -56,7 +54,6 @@ do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
-fetchMemPort=icache_port
 functionTrace=false
 functionTraceStart=0
 function_trace=false
@@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -115,7 +112,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -123,7 +120,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -144,7 +141,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -155,7 +152,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -175,8 +172,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -186,7 +183,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -194,7 +192,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
 egid=100
 env=
 errout=cerr
@@ -218,15 +216,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
index b48111dc2..9d80ff74e 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 17:49:22
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:36:59
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
index b53980a02..9080a092b 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.009999                       # Nu
 sim_ticks                                1009998808500                       # Number of ticks simulated
 final_tick                               1009998808500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 135204                       # Simulator instruction rate (inst/s)
-host_op_rate                                   135204                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               75039783                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 209960                       # Number of bytes of host memory used
-host_seconds                                 13459.51                       # Real time elapsed on the host
+host_inst_rate                                  95125                       # Simulator instruction rate (inst/s)
+host_op_rate                                    95125                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               52795470                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214864                       # Number of bytes of host memory used
+host_seconds                                 19130.41                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   172618048                       # Number of bytes read from this memory
@@ -57,30 +57,6 @@ system.cpu.workload.num_syscalls                   29                       # Nu
 system.cpu.numCycles                       2019997618                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                    1746428176                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
-system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                         7533729                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       443112454                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                       1576885164                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         78.063714                       # Percentage of cycles cpu is active
-system.cpu.comLoads                         444595663                       # Number of Load instructions committed
-system.cpu.comStores                        160728502                       # Number of Store instructions committed
-system.cpu.comBranches                      214632552                       # Number of Branches instructions committed
-system.cpu.comNops                           83736345                       # Number of Nop instructions committed
-system.cpu.comNonSpec                              29                       # Number of Non-Speculative instructions committed
-system.cpu.comInts                          916086844                       # Number of Integer instructions committed
-system.cpu.comFloats                              190                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                  1819780127                       # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps                    1819780127                       # Number of Ops committed (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total            1819780127                       # Number of Instructions committed (Total)
-system.cpu.cpi                               1.110023                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         1.110023                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.900882                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.900882                       # IPC: Total IPC of All Threads
 system.cpu.branch_predictor.lookups         328891112                       # Number of BP lookups
 system.cpu.branch_predictor.condPredicted    253883187                       # Number of conditional branches predicted
 system.cpu.branch_predictor.condIncorrect    140042357                       # Number of conditional branches incorrect
@@ -107,6 +83,30 @@ system.cpu.execution_unit.mispredictPct     62.009227                       # Pe
 system.cpu.execution_unit.executions       1139611303                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies                75                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.contextSwitches                          1                       # Number of context switches
+system.cpu.threadCycles                    1746428176                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled                         7533729                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       443112454                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                       1576885164                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         78.063714                       # Percentage of cycles cpu is active
+system.cpu.comLoads                         444595663                       # Number of Load instructions committed
+system.cpu.comStores                        160728502                       # Number of Store instructions committed
+system.cpu.comBranches                      214632552                       # Number of Branches instructions committed
+system.cpu.comNops                           83736345                       # Number of Nop instructions committed
+system.cpu.comNonSpec                              29                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                          916086844                       # Number of Integer instructions committed
+system.cpu.comFloats                              190                       # Number of Floating Point instructions committed
+system.cpu.committedInsts                  1819780127                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                    1819780127                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total            1819780127                       # Number of Instructions committed (Total)
+system.cpu.cpi                               1.110023                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
+system.cpu.cpi_total                         1.110023                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.900882                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
+system.cpu.ipc_total                         0.900882                       # IPC: Total IPC of All Threads
 system.cpu.stage0.idleCycles                829317091                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                1190680527                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage0.utilization               58.944650                       # Percentage of cycles stage was utilized (processing insts).
@@ -165,7 +165,7 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets       125500                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets        31375                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
@@ -363,7 +363,7 @@ system.cpu.l2cache.blocked_cycles::no_targets            0
 system.cpu.l2cache.blocked::no_mshrs               70                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs  8292.857143                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1170911                       # number of writebacks
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index 66f7d63e2..7904554e8 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -419,7 +418,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -440,7 +439,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -451,7 +450,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -471,8 +470,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -482,7 +481,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -490,7 +490,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
 egid=100
 env=
 errout=cerr
@@ -514,15 +514,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
index 6f27fa680..70e725c8b 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 17:50:00
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:19
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 2f0a96bc0..385663c88 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.614317                       # Nu
 sim_ticks                                614317285000                       # Number of ticks simulated
 final_tick                               614317285000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 195309                       # Simulator instruction rate (inst/s)
-host_op_rate                                   195309                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               69112237                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211096                       # Number of bytes of host memory used
-host_seconds                                  8888.69                       # Real time elapsed on the host
+host_inst_rate                                 104366                       # Simulator instruction rate (inst/s)
+host_op_rate                                   104366                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               36931162                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215744                       # Number of bytes of host memory used
+host_seconds                                 16634.12                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   173249728                       # Number of bytes read from this memory
@@ -367,8 +367,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          494                       # number of ReadReq MSHR hits
@@ -583,7 +583,7 @@ system.cpu.l2cache.blocked_cycles::no_targets            0
 system.cpu.l2cache.blocked::no_mshrs             1684                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10404.988124                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1172197                       # number of writebacks
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index d36004a3f..e320bcc80 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -77,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
index 632f371aa..0267f64e9 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:29:07
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-atomic
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:38:02
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
index 2d84c17ba..ce798be64 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.913189                       # Nu
 sim_ticks                                913189263000                       # Number of ticks simulated
 final_tick                               913189263000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                5189226                       # Simulator instruction rate (inst/s)
-host_op_rate                                  5189226                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2604020675                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 200656                       # Number of bytes of host memory used
-host_seconds                                   350.68                       # Real time elapsed on the host
+host_inst_rate                                2012645                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2012645                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1009971108                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 205536                       # Number of bytes of host memory used
+host_seconds                                   904.17                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  9280309971                       # Number of bytes read from this memory
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 70d2dba0c..b8d054f36 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -120,7 +119,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -159,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
index 91c7dc82f..166dc5643 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:35:09
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:38:45
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 52ac717c2..ada639802 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.663444                       # Nu
 sim_ticks                                2663443716000                       # Number of ticks simulated
 final_tick                               2663443716000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2433308                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2433308                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3561407770                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 209524                       # Number of bytes of host memory used
-host_seconds                                   747.86                       # Real time elapsed on the host
+host_inst_rate                                 768706                       # Simulator instruction rate (inst/s)
+host_op_rate                                   768706                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1125083732                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214428                       # Number of bytes of host memory used
+host_seconds                                  2367.33                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   172614208                       # Number of bytes read from this memory
@@ -119,8 +119,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          802                       # number of ReadReq MSHR misses
@@ -195,8 +195,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      3058802                       # number of writebacks
@@ -302,8 +302,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1170923                       # number of writebacks
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index be1f1b29f..11fd3546f 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -509,12 +508,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing
+cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -537,8 +536,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
index e85e89203..35c5c026a 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:44:10
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:46:03
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 45a43d0ac..54d82ede5 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.463994                       # Nu
 sim_ticks                                463993693500                       # Number of ticks simulated
 final_tick                               463993693500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 212934                       # Simulator instruction rate (inst/s)
-host_op_rate                                   237543                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               63966219                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224764                       # Number of bytes of host memory used
-host_seconds                                  7253.73                       # Real time elapsed on the host
+host_inst_rate                                 113228                       # Simulator instruction rate (inst/s)
+host_op_rate                                   126315                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               34014323                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231672                       # Number of bytes of host memory used
+host_seconds                                 13641.13                       # Real time elapsed on the host
 sim_insts                                  1544563066                       # Number of instructions simulated
 sim_ops                                    1723073879                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   189795648                       # Number of bytes read from this memory
@@ -378,8 +378,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          396                       # number of ReadReq MSHR hits
@@ -595,7 +595,7 @@ system.cpu.l2cache.blocked_cycles::no_targets            0
 system.cpu.l2cache.blocked::no_mshrs             6735                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs  8512.175204                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1222221                       # number of writebacks
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index 2b19687c3..e2f8298fd 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -95,12 +95,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic
+cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -123,8 +123,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
index d2789ef63..89e0dc3cd 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:48:11
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:48:29
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index a81ef68d7..991f53624 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.861538                       # Nu
 sim_ticks                                861538205000                       # Number of ticks simulated
 final_tick                               861538205000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2870592                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3202357                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1601180723                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213836                       # Number of bytes of host memory used
-host_seconds                                   538.06                       # Real time elapsed on the host
+host_inst_rate                                1163959                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1298482                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              649242111                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220952                       # Number of bytes of host memory used
+host_seconds                                  1326.99                       # Real time elapsed on the host
 sim_insts                                  1544563049                       # Number of instructions simulated
 sim_ops                                    1723073862                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  7759650064                       # Number of bytes read from this memory
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
index a5aadfde9..745e9eef0 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -178,12 +177,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing
+cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -206,8 +205,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
index cbd722a94..4467d8b99 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:53:56
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:48:54
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index ce1a1d893..47aaa5f47 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.431420                       # Nu
 sim_ticks                                2431419954000                       # Number of ticks simulated
 final_tick                               2431419954000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1812626                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2022908                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2864161367                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223004                       # Number of bytes of host memory used
-host_seconds                                   848.91                       # Real time elapsed on the host
+host_inst_rate                                 629125                       # Simulator instruction rate (inst/s)
+host_op_rate                                   702110                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              994091440                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230132                       # Number of bytes of host memory used
+host_seconds                                  2445.87                       # Real time elapsed on the host
 sim_insts                                  1538759609                       # Number of instructions simulated
 sim_ops                                    1717270343                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   172766016                       # Number of bytes read from this memory
@@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          638                       # number of ReadReq MSHR misses
@@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      3061985                       # number of writebacks
@@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1171980                       # number of writebacks
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index 6cebafbf0..896780d15 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -69,7 +69,7 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.membus.port[5]
+port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -77,8 +77,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[7]
-pio=system.membus.port[6]
+int_master=system.membus.slave[5]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -89,7 +90,7 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.membus.port[4]
+port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -97,7 +98,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic
+cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -121,15 +122,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
index 23e0a7dab..4ac95340c 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:53
-gem5 started Feb 11 2012 14:34:58
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:57:51
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index c4996594d..0122786be 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.846007                       # Nu
 sim_ticks                                2846007259500                       # Number of ticks simulated
 final_tick                               2846007259500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1815306                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2828411                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1717498350                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 210188                       # Number of bytes of host memory used
-host_seconds                                  1657.07                       # Real time elapsed on the host
+host_inst_rate                                 632359                       # Simulator instruction rate (inst/s)
+host_op_rate                                   985272                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              598287574                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215392                       # Number of bytes of host memory used
+host_seconds                                  4756.92                       # Real time elapsed on the host
 sim_insts                                  3008081057                       # Number of instructions simulated
 sim_ops                                    4686862651                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                 37129731755                       # Number of bytes read from this memory
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index a21cde2b2..8676306dc 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -91,11 +90,11 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[3]
+port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -116,7 +115,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -124,8 +123,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[4]
-pio=system.membus.port[3]
+int_master=system.membus.slave[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -136,11 +136,11 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[2]
+port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -160,8 +160,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[4]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -171,7 +171,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -179,7 +180,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
+cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -203,15 +204,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
index 0e700a575..a0492ef0b 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:53
-gem5 started Feb 11 2012 14:48:34
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:58:27
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index aefb42b3b..87097d7a4 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.923548                       # Nu
 sim_ticks                                5923548078000                       # Number of ticks simulated
 final_tick                               5923548078000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1064786                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1659033                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2096788716                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219100                       # Number of bytes of host memory used
-host_seconds                                  2825.06                       # Real time elapsed on the host
+host_inst_rate                                 443317                       # Simulator instruction rate (inst/s)
+host_op_rate                                   690728                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              872984671                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224336                       # Number of bytes of host memory used
+host_seconds                                  6785.40                       # Real time elapsed on the host
 sim_insts                                  3008081057                       # Number of instructions simulated
 sim_ops                                    4686862651                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   173910080                       # Number of bytes read from this memory
@@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          675                       # number of ReadReq MSHR misses
@@ -163,8 +163,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      3053391                       # number of writebacks
@@ -270,8 +270,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1174631                       # number of writebacks
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
index 1763cd3d7..5ef210362 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -41,7 +40,6 @@ choiceCtrBits=2
 choicePredictorSize=8192
 clock=500
 cpu_id=0
-dataMemPort=dcache_port
 defer_registration=false
 div16Latency=1
 div16RepeatRate=1
@@ -56,7 +54,6 @@ do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
-fetchMemPort=icache_port
 functionTrace=false
 functionTraceStart=0
 function_trace=false
@@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -115,7 +112,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -123,7 +120,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -144,7 +141,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -155,7 +152,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -175,8 +172,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -186,7 +183,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -194,7 +192,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
 egid=100
 env=
 errout=cerr
@@ -218,15 +216,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
index 6032e061b..a267cf67d 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 17:58:42
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing
-Couldn't unlink  build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav
-Couldn't unlink  build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:36:56
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index 2e73aee88..46f5e7fc2 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.042005                       # Nu
 sim_ticks                                 42005374000                       # Number of ticks simulated
 final_tick                                42005374000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 147839                       # Simulator instruction rate (inst/s)
-host_op_rate                                   147839                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               67571644                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213560                       # Number of bytes of host memory used
-host_seconds                                   621.64                       # Real time elapsed on the host
+host_inst_rate                                  62394                       # Simulator instruction rate (inst/s)
+host_op_rate                                    62394                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               28517940                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218584                       # Number of bytes of host memory used
+host_seconds                                  1472.95                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      316032                       # Number of bytes read from this memory
@@ -56,30 +56,6 @@ system.cpu.workload.num_syscalls                  389                       # Nu
 system.cpu.numCycles                         84010749                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                      83632403                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
-system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                           11097                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         7735993                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                         76274756                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         90.791663                       # Percentage of cycles cpu is active
-system.cpu.comLoads                          19996198                       # Number of Load instructions committed
-system.cpu.comStores                          6501103                       # Number of Store instructions committed
-system.cpu.comBranches                       10240685                       # Number of Branches instructions committed
-system.cpu.comNops                            7723346                       # Number of Nop instructions committed
-system.cpu.comNonSpec                             389                       # Number of Non-Speculative instructions committed
-system.cpu.comInts                           43665352                       # Number of Integer instructions committed
-system.cpu.comFloats                          3775974                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                    91903056                       # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps                      91903056                       # Number of Ops committed (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total              91903056                       # Number of Instructions committed (Total)
-system.cpu.cpi                               0.914124                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         0.914124                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.093944                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         1.093944                       # IPC: Total IPC of All Threads
 system.cpu.branch_predictor.lookups          13563923                       # Number of BP lookups
 system.cpu.branch_predictor.condPredicted      9779691                       # Number of conditional branches predicted
 system.cpu.branch_predictor.condIncorrect      4496836                       # Number of conditional branches incorrect
@@ -106,6 +82,30 @@ system.cpu.execution_unit.mispredictPct     43.903025                       # Pe
 system.cpu.execution_unit.executions         57471384                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies            458266                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.contextSwitches                          1                       # Number of context switches
+system.cpu.threadCycles                      83632403                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled                           11097                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         7735993                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                         76274756                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         90.791663                       # Percentage of cycles cpu is active
+system.cpu.comLoads                          19996198                       # Number of Load instructions committed
+system.cpu.comStores                          6501103                       # Number of Store instructions committed
+system.cpu.comBranches                       10240685                       # Number of Branches instructions committed
+system.cpu.comNops                            7723346                       # Number of Nop instructions committed
+system.cpu.comNonSpec                             389                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                           43665352                       # Number of Integer instructions committed
+system.cpu.comFloats                          3775974                       # Number of Floating Point instructions committed
+system.cpu.committedInsts                    91903056                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                      91903056                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total              91903056                       # Number of Instructions committed (Total)
+system.cpu.cpi                               0.914124                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
+system.cpu.cpi_total                         0.914124                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.093944                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
+system.cpu.ipc_total                         1.093944                       # IPC: Total IPC of All Threads
 system.cpu.stage0.idleCycles                 27790213                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                  56220536                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage0.utilization               66.920646                       # Percentage of cycles stage was utilized (processing insts).
@@ -164,7 +164,7 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets        97000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               6                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets 16166.666667                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
@@ -246,7 +246,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets     41043500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets             823                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets 49870.595383                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -364,8 +364,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2794                       # number of ReadReq MSHR misses
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 10359186b..ab521397c 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -419,7 +418,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -440,7 +439,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -451,7 +450,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -471,8 +470,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -482,7 +481,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -490,7 +490,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
 egid=100
 env=
 errout=cerr
@@ -514,15 +514,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
index 58e98acc5..ec78af77e 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 18:07:15
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing
-Couldn't unlink  build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
-Couldn't unlink  build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:19
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 8502942e2..9debfab2e 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.023638                       # Nu
 sim_ticks                                 23638033500                       # Number of ticks simulated
 final_tick                                23638033500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 231314                       # Simulator instruction rate (inst/s)
-host_op_rate                                   231314                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               64954124                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214912                       # Number of bytes of host memory used
-host_seconds                                   363.92                       # Real time elapsed on the host
+host_inst_rate                                  91328                       # Simulator instruction rate (inst/s)
+host_op_rate                                    91328                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               25645337                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219700                       # Number of bytes of host memory used
+host_seconds                                   921.73                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      336064                       # Number of bytes read from this memory
@@ -366,8 +366,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1382                       # number of ReadReq MSHR hits
@@ -459,7 +459,7 @@ system.cpu.dcache.blocked_cycles::no_targets            0
 system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs         6500                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          108                       # number of writebacks
@@ -583,7 +583,7 @@ system.cpu.l2cache.blocked_cycles::no_targets            0
 system.cpu.l2cache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs         2000                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3093                       # number of ReadReq MSHR misses
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 452e0175b..d2933f641 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -77,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
index b6a6db444..0cde8149d 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:46:35
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:41:43
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index defa21ce1..47fe26ecb 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.045952                       # Nu
 sim_ticks                                 45951567500                       # Number of ticks simulated
 final_tick                                45951567500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                5286635                       # Simulator instruction rate (inst/s)
-host_op_rate                                  5286630                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2643314521                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 204308                       # Number of bytes of host memory used
-host_seconds                                    17.38                       # Real time elapsed on the host
+host_inst_rate                                2042062                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2042061                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1021030561                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 209388                       # Number of bytes of host memory used
+host_seconds                                    45.01                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   475949877                       # Number of bytes read from this memory
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 16b0989b3..f8f410537 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -120,7 +119,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -159,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
index 1373e7148..de47399fe 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:47:03
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:39:37
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index 244f3ca51..180c17bb1 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.118740                       # Nu
 sim_ticks                                118740049000                       # Number of ticks simulated
 final_tick                               118740049000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2598987                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2598985                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3357924345                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213168                       # Number of bytes of host memory used
-host_seconds                                    35.36                       # Real time elapsed on the host
+host_inst_rate                                 796943                       # Simulator instruction rate (inst/s)
+host_op_rate                                   796942                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1029660597                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218284                       # Number of bytes of host memory used
+host_seconds                                   115.32                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      304960                       # Number of bytes read from this memory
@@ -118,8 +118,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         8510                       # number of ReadReq MSHR misses
@@ -194,8 +194,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          107                       # number of writebacks
@@ -304,8 +304,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2621                       # number of ReadReq MSHR misses
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index 81b928843..0883e5a4a 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -509,12 +508,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing
+cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -537,8 +536,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
index 79676436b..2311bc195 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:57:20
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:50:10
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
+Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index cd7596c98..a127da205 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.076323                       # Nu
 sim_ticks                                 76322764500                       # Number of ticks simulated
 final_tick                                76322764500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 160991                       # Simulator instruction rate (inst/s)
-host_op_rate                                   176268                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               71299389                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228164                       # Number of bytes of host memory used
-host_seconds                                  1070.45                       # Real time elapsed on the host
+host_inst_rate                                  57710                       # Simulator instruction rate (inst/s)
+host_op_rate                                    63186                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               25558377                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235176                       # Number of bytes of host memory used
+host_seconds                                  2986.21                       # Real time elapsed on the host
 sim_insts                                   172333279                       # Number of instructions simulated
 sim_ops                                     188686762                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      246592                       # Number of bytes read from this memory
@@ -377,8 +377,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          804                       # number of ReadReq MSHR hits
@@ -473,7 +473,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets        19500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets         9750                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -593,8 +593,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
index 3c665fa33..bd55e37b1 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -95,12 +95,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic
+cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -123,8 +123,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
index a15e6fee3..1a4090c67 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 18:08:16
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 17:02:03
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
+Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav
+Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index ffec0c1d3..11a4c0835 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.103107                       # Nu
 sim_ticks                                103106771000                       # Number of ticks simulated
 final_tick                               103106771000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2490166                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2726490                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1489999442                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216948                       # Number of bytes of host memory used
-host_seconds                                    69.20                       # Real time elapsed on the host
+host_inst_rate                                1081638                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1184289                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              647201988                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224040                       # Number of bytes of host memory used
+host_seconds                                   159.31                       # Real time elapsed on the host
 sim_insts                                   172317417                       # Number of instructions simulated
 sim_ops                                     188670900                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   869973902                       # Number of bytes read from this memory
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
index a0f7615f4..98e25ecfe 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -178,12 +177,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing
+cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -206,8 +205,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
index 1602e57ed..97209751d 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 18:09:36
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 17:04:54
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
+Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav
+Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 843b32b30..5b0760555 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.232077                       # Nu
 sim_ticks                                232077154000                       # Number of ticks simulated
 final_tick                               232077154000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1841932                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2017113                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2487570299                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226116                       # Number of bytes of host memory used
-host_seconds                                    93.29                       # Real time elapsed on the host
+host_inst_rate                                 578450                       # Simulator instruction rate (inst/s)
+host_op_rate                                   633465                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              781209577                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 233216                       # Number of bytes of host memory used
+host_seconds                                   297.07                       # Real time elapsed on the host
 sim_insts                                   171842491                       # Number of instructions simulated
 sim_ops                                     188185929                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      220992                       # Number of bytes read from this memory
@@ -128,8 +128,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3051                       # number of ReadReq MSHR misses
@@ -212,8 +212,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
@@ -322,8 +322,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1729                       # number of ReadReq MSHR misses
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index bf42eae33..b2ac1c016 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -77,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic
+cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
index 288eec929..fe38fbd1a 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 14:01:49
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:47:40
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index acb9c3a66..417f58ce8 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.096723                       # Nu
 sim_ticks                                 96722951500                       # Number of ticks simulated
 final_tick                                96722951500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4190258                       # Simulator instruction rate (inst/s)
-host_op_rate                                  4190262                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2095142285                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 207744                       # Number of bytes of host memory used
-host_seconds                                    46.17                       # Real time elapsed on the host
+host_inst_rate                                1581365                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1581366                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              790687708                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217932                       # Number of bytes of host memory used
+host_seconds                                   122.33                       # Real time elapsed on the host
 sim_insts                                   193444531                       # Number of instructions simulated
 sim_ops                                     193444769                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   997245606                       # Number of bytes read from this memory
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
index 4355111bc..af9f6c271 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=SparcInterrupts
@@ -120,7 +119,7 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -159,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing
+cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
index cb4fa4440..f7fdf9677 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 14:02:21
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:49:18
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
+Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index fba3d7989..415ede7b3 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.270577                       # Nu
 sim_ticks                                270576960000                       # Number of ticks simulated
 final_tick                               270576960000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2083715                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2083717                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2914556895                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216616                       # Number of bytes of host memory used
-host_seconds                                    92.84                       # Real time elapsed on the host
+host_inst_rate                                 668557                       # Simulator instruction rate (inst/s)
+host_op_rate                                   668558                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              935131366                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226812                       # Number of bytes of host memory used
+host_seconds                                   289.35                       # Real time elapsed on the host
 sim_insts                                   193444531                       # Number of instructions simulated
 sim_ops                                     193444769                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      331072                       # Number of bytes read from this memory
@@ -86,8 +86,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12288                       # number of ReadReq MSHR misses
@@ -172,8 +172,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks            2                       # number of writebacks
@@ -283,8 +283,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3597                       # number of ReadReq MSHR misses
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
index 82a282d96..91cbfaf86 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -159,7 +158,7 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[3]
+port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.fuPool]
 type=FUPool
@@ -426,7 +425,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -447,7 +446,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -455,8 +454,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[4]
-pio=system.membus.port[3]
+int_master=system.membus.slave[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -467,11 +467,11 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[2]
+port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -491,8 +491,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[4]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -502,7 +502,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -510,7 +511,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing
+cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
@@ -534,15 +535,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
index 138f6116a..6d5fbd5bb 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:18:12
-gem5 started Feb 12 2012 19:27:36
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing
-Couldn't unlink  build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sav
-Couldn't unlink  build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 16:00:57
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 7c2d38b1f..19ddbed23 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.087728                       # Nu
 sim_ticks                                 87727531000                       # Number of ticks simulated
 final_tick                                87727531000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 101058                       # Simulator instruction rate (inst/s)
-host_op_rate                                   169383                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               67127344                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229892                       # Number of bytes of host memory used
-host_seconds                                  1306.88                       # Real time elapsed on the host
+host_inst_rate                                  36137                       # Simulator instruction rate (inst/s)
+host_op_rate                                    60569                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               24003841                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 234992                       # Number of bytes of host memory used
+host_seconds                                  3654.73                       # Real time elapsed on the host
 sim_insts                                   132071227                       # Number of instructions simulated
 sim_ops                                     221363017                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      345792                       # Number of bytes read from this memory
@@ -331,8 +331,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1378                       # number of ReadReq MSHR hits
@@ -413,8 +413,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           13                       # number of writebacks
@@ -536,8 +536,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3441                       # number of ReadReq MSHR misses
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
index 1355f971a..8039a1c87 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -69,7 +69,7 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.membus.port[5]
+port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -77,8 +77,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[7]
-pio=system.membus.port[6]
+int_master=system.membus.slave[5]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -89,7 +90,7 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.membus.port[4]
+port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -97,7 +98,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic
+cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -121,15 +122,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
index d61c2b9aa..8d8c9ffed 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:53
-gem5 started Feb 11 2012 15:27:33
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 16:01:40
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 0e7ef2e19..8ac81bf15 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.131393                       # Nu
 sim_ticks                                131393100000                       # Number of ticks simulated
 final_tick                               131393100000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1741959                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2919677                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1733014386                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217356                       # Number of bytes of host memory used
-host_seconds                                    75.82                       # Real time elapsed on the host
+host_inst_rate                                 595335                       # Simulator instruction rate (inst/s)
+host_op_rate                                   997834                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              592278441                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222596                       # Number of bytes of host memory used
+host_seconds                                   221.84                       # Real time elapsed on the host
 sim_insts                                   132071228                       # Number of instructions simulated
 sim_ops                                     221363018                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  1698379042                       # Number of bytes read from this memory
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
index 62a1aa7b0..4785eec61 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -91,11 +90,11 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[3]
+port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -116,7 +115,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -124,8 +123,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[4]
-pio=system.membus.port[3]
+int_master=system.membus.slave[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -136,11 +136,11 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[2]
+port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -160,8 +160,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[4]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -171,7 +171,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -179,7 +180,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing
+cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -203,15 +204,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
index fff65e67f..b246803c9 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:53
-gem5 started Feb 11 2012 15:28:59
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 16:03:05
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 6e3725588..4699fa0ff 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.250961                       # Nu
 sim_ticks                                250960631000                       # Number of ticks simulated
 final_tick                               250960631000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1043901                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1749670                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1983612036                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226268                       # Number of bytes of host memory used
-host_seconds                                   126.52                       # Real time elapsed on the host
+host_inst_rate                                 334930                       # Simulator instruction rate (inst/s)
+host_op_rate                                   561373                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              636431760                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231532                       # Number of bytes of host memory used
+host_seconds                                   394.32                       # Real time elapsed on the host
 sim_insts                                   132071228                       # Number of instructions simulated
 sim_ops                                     221363018                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      303040                       # Number of bytes read from this memory
@@ -86,8 +86,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4694                       # number of ReadReq MSHR misses
@@ -162,8 +162,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks            7                       # number of writebacks
@@ -272,8 +272,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2840                       # number of ReadReq MSHR misses
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index ab088d9ce..631fa3b25 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -19,7 +19,6 @@ mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 pal=/dist/m5/system/binaries/ts_osfpal
-physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -31,7 +30,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[2]
+system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
@@ -41,8 +40,8 @@ ranges=8796093022208:18446744073709551615
 req_size=16
 resp_size=16
 write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[0]
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
 
 [system.cpu0]
 type=AtomicSimpleCPU
@@ -55,6 +54,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu0.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu0.interrupts
@@ -78,7 +78,7 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -99,7 +99,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
 
 [system.cpu0.dtb]
 type=AlphaTLB
@@ -107,7 +107,7 @@ size=64
 
 [system.cpu0.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -128,7 +128,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
 
 [system.cpu0.interrupts]
 type=AlphaInterrupts
@@ -151,6 +151,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu1.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu1.interrupts
@@ -174,7 +175,7 @@ icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -195,7 +196,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[4]
+mem_side=system.toL2Bus.slave[3]
 
 [system.cpu1.dtb]
 type=AlphaTLB
@@ -203,7 +204,7 @@ size=64
 
 [system.cpu1.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -224,7 +225,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[3]
+mem_side=system.toL2Bus.slave[2]
 
 [system.cpu1.interrupts]
 type=AlphaInterrupts
@@ -289,11 +290,12 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
+master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
 type=BaseCache
-addr_range=0:8589934591
+addr_ranges=0:8589934591
 assoc=8
 block_size=64
 forward_snoops=false
@@ -313,12 +315,12 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[32]
-mem_side=system.membus.port[3]
+cpu_side=system.iobus.master[29]
+mem_side=system.membus.slave[1]
 
 [system.l2c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
 forward_snoops=true
@@ -338,8 +340,8 @@ tgts_per_mshr=16
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[4]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
 
 [system.membus]
 type=Bus
@@ -351,7 +353,8 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
+master=system.bridge.slave system.physmem.port[0]
+slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -370,14 +373,16 @@ warn_access=
 pio=system.membus.default
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[1]
 
 [system.simple_disk]
 type=SimpleDisk
@@ -405,7 +410,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
 
 [system.tsunami]
 type=Tsunami
@@ -422,7 +428,7 @@ pio_latency=1000
 platform=system.tsunami
 system=system
 terminal=system.terminal
-pio=system.iobus.port[25]
+pio=system.iobus.master[24]
 
 [system.tsunami.cchip]
 type=TsunamiCChip
@@ -430,7 +436,7 @@ pio_addr=8803072344064
 pio_latency=1000
 system=system
 tsunami=system.tsunami
-pio=system.iobus.port[1]
+pio=system.iobus.master[0]
 
 [system.tsunami.ethernet]
 type=NSGigE
@@ -499,9 +505,9 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
-pio=system.iobus.port[29]
+config=system.iobus.master[28]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -517,7 +523,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[9]
+pio=system.iobus.master[8]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
@@ -533,7 +539,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[20]
+pio=system.iobus.master[19]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
@@ -549,7 +555,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[21]
+pio=system.iobus.master[20]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
@@ -565,7 +571,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[10]
+pio=system.iobus.master[9]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
@@ -581,7 +587,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[12]
+pio=system.iobus.master[11]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
@@ -597,7 +603,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[13]
+pio=system.iobus.master[12]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
@@ -613,7 +619,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[14]
+pio=system.iobus.master[13]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
@@ -629,7 +635,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[15]
+pio=system.iobus.master[14]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
@@ -645,7 +651,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[16]
+pio=system.iobus.master[15]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
@@ -661,7 +667,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[17]
+pio=system.iobus.master[16]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
@@ -677,7 +683,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[18]
+pio=system.iobus.master[17]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
@@ -693,7 +699,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[19]
+pio=system.iobus.master[18]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
@@ -709,7 +715,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[11]
+pio=system.iobus.master[10]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
@@ -725,7 +731,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[8]
+pio=system.iobus.master[7]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
@@ -741,7 +747,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[3]
+pio=system.iobus.master[2]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
@@ -757,7 +763,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[4]
+pio=system.iobus.master[3]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
@@ -773,7 +779,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[5]
+pio=system.iobus.master[4]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
@@ -789,7 +795,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[6]
+pio=system.iobus.master[5]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
@@ -805,7 +811,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[7]
+pio=system.iobus.master[6]
 
 [system.tsunami.fb]
 type=BadDevice
@@ -813,7 +819,7 @@ devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=1000
 system=system
-pio=system.iobus.port[22]
+pio=system.iobus.master[21]
 
 [system.tsunami.ide]
 type=IdeController
@@ -867,9 +873,9 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[27]
-dma=system.iobus.port[28]
-pio=system.iobus.port[26]
+config=system.iobus.master[26]
+dma=system.iobus.slave[1]
+pio=system.iobus.master[25]
 
 [system.tsunami.io]
 type=TsunamiIO
@@ -880,7 +886,7 @@ system=system
 time=Thu Jan  1 00:00:00 2009
 tsunami=system.tsunami
 year_is_bcd=false
-pio=system.iobus.port[23]
+pio=system.iobus.master[22]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
@@ -888,7 +894,7 @@ pio_addr=8802535473152
 pio_latency=1000
 system=system
 tsunami=system.tsunami
-pio=system.iobus.port[2]
+pio=system.iobus.master[1]
 
 [system.tsunami.pciconfig]
 type=PciConfigAll
@@ -906,5 +912,5 @@ pio_latency=1000
 platform=system.tsunami
 system=system
 terminal=system.terminal
-pio=system.iobus.port[24]
+pio=system.iobus.master[23]
 
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index 78e725520..8c9800a70 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -1,12 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:09:36
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:36:56
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 97861500
 Exiting @ tick 1870335522500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index a6953794d..b34633a17 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.870336                       # Nu
 sim_ticks                                1870335522500                       # Number of ticks simulated
 final_tick                               1870335522500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4204751                       # Simulator instruction rate (inst/s)
-host_op_rate                                  4204746                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                           124525337361                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293604                       # Number of bytes of host memory used
-host_seconds                                    15.02                       # Real time elapsed on the host
+host_inst_rate                                1989571                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1989570                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            58921958204                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298304                       # Number of bytes of host memory used
+host_seconds                                    31.74                       # Real time elapsed on the host
 sim_insts                                    63154034                       # Number of instructions simulated
 sim_ops                                      63154034                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    72297472                       # Number of bytes read from this memory
@@ -136,8 +136,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              121798                       # number of writebacks
@@ -176,8 +176,8 @@ system.iocache.blocked_cycles::no_mshrs             0                       # nu
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41520                       # number of writebacks
@@ -332,8 +332,8 @@ system.cpu0.kern.mode_good::user                 1158
 system.cpu0.kern.mode_good::idle                    0                      
 system.cpu0.kern.mode_switch_good::kernel     0.163165                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_ticks::kernel      1869378305000     99.95%     99.95% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::user           957009000      0.05%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
@@ -343,30 +343,30 @@ system.tsunami.ethernet.descDMAWrites               0                       # Nu
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
 system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
 system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
 system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
 system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
 system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
 system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
 system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
 system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
 system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
 system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
 system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
 system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
 system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
 system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu0.icache.replacements                884404                       # number of replacements
@@ -403,8 +403,8 @@ system.cpu0.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks           95                       # number of writebacks
@@ -465,8 +465,8 @@ system.cpu0.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks       771740                       # number of writebacks
@@ -632,8 +632,8 @@ system.cpu1.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks           15                       # number of writebacks
@@ -694,8 +694,8 @@ system.cpu1.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks        39996                       # number of writebacks
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 435421de9..3d4adbd35 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -19,7 +19,6 @@ mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 pal=/dist/m5/system/binaries/ts_osfpal
-physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -31,7 +30,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[2]
+system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
@@ -41,8 +40,8 @@ ranges=8796093022208:18446744073709551615
 req_size=16
 resp_size=16
 write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[0]
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -55,6 +54,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -78,7 +78,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -99,7 +99,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -107,7 +107,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -128,7 +128,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -193,11 +193,12 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
+master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
 type=BaseCache
-addr_range=0:8589934591
+addr_ranges=0:8589934591
 assoc=8
 block_size=64
 forward_snoops=false
@@ -217,12 +218,12 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[32]
-mem_side=system.membus.port[3]
+cpu_side=system.iobus.master[29]
+mem_side=system.membus.slave[1]
 
 [system.l2c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
 forward_snoops=true
@@ -242,8 +243,8 @@ tgts_per_mshr=16
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[4]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
 
 [system.membus]
 type=Bus
@@ -255,7 +256,8 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
+master=system.bridge.slave system.physmem.port[0]
+slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -274,14 +276,16 @@ warn_access=
 pio=system.membus.default
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[1]
 
 [system.simple_disk]
 type=SimpleDisk
@@ -309,7 +313,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.tsunami]
 type=Tsunami
@@ -326,7 +331,7 @@ pio_latency=1000
 platform=system.tsunami
 system=system
 terminal=system.terminal
-pio=system.iobus.port[25]
+pio=system.iobus.master[24]
 
 [system.tsunami.cchip]
 type=TsunamiCChip
@@ -334,7 +339,7 @@ pio_addr=8803072344064
 pio_latency=1000
 system=system
 tsunami=system.tsunami
-pio=system.iobus.port[1]
+pio=system.iobus.master[0]
 
 [system.tsunami.ethernet]
 type=NSGigE
@@ -403,9 +408,9 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
-pio=system.iobus.port[29]
+config=system.iobus.master[28]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -421,7 +426,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[9]
+pio=system.iobus.master[8]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
@@ -437,7 +442,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[20]
+pio=system.iobus.master[19]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
@@ -453,7 +458,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[21]
+pio=system.iobus.master[20]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
@@ -469,7 +474,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[10]
+pio=system.iobus.master[9]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
@@ -485,7 +490,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[12]
+pio=system.iobus.master[11]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
@@ -501,7 +506,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[13]
+pio=system.iobus.master[12]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
@@ -517,7 +522,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[14]
+pio=system.iobus.master[13]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
@@ -533,7 +538,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[15]
+pio=system.iobus.master[14]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
@@ -549,7 +554,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[16]
+pio=system.iobus.master[15]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
@@ -565,7 +570,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[17]
+pio=system.iobus.master[16]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
@@ -581,7 +586,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[18]
+pio=system.iobus.master[17]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
@@ -597,7 +602,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[19]
+pio=system.iobus.master[18]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
@@ -613,7 +618,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[11]
+pio=system.iobus.master[10]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
@@ -629,7 +634,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[8]
+pio=system.iobus.master[7]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
@@ -645,7 +650,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[3]
+pio=system.iobus.master[2]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
@@ -661,7 +666,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[4]
+pio=system.iobus.master[3]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
@@ -677,7 +682,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[5]
+pio=system.iobus.master[4]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
@@ -693,7 +698,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[6]
+pio=system.iobus.master[5]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
@@ -709,7 +714,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[7]
+pio=system.iobus.master[6]
 
 [system.tsunami.fb]
 type=BadDevice
@@ -717,7 +722,7 @@ devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=1000
 system=system
-pio=system.iobus.port[22]
+pio=system.iobus.master[21]
 
 [system.tsunami.ide]
 type=IdeController
@@ -771,9 +776,9 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[27]
-dma=system.iobus.port[28]
-pio=system.iobus.port[26]
+config=system.iobus.master[26]
+dma=system.iobus.slave[1]
+pio=system.iobus.master[25]
 
 [system.tsunami.io]
 type=TsunamiIO
@@ -784,7 +789,7 @@ system=system
 time=Thu Jan  1 00:00:00 2009
 tsunami=system.tsunami
 year_is_bcd=false
-pio=system.iobus.port[23]
+pio=system.iobus.master[22]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
@@ -792,7 +797,7 @@ pio_addr=8802535473152
 pio_latency=1000
 system=system
 tsunami=system.tsunami
-pio=system.iobus.port[2]
+pio=system.iobus.master[1]
 
 [system.tsunami.pciconfig]
 type=PciConfigAll
@@ -810,5 +815,5 @@ pio_latency=1000
 platform=system.tsunami
 system=system
 terminal=system.terminal
-pio=system.iobus.port[24]
+pio=system.iobus.master[23]
 
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index 484a5fec9..f348f1381 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -1,11 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:09:36
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:42:39
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1829332258000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index d300de39a..1b6d7ca40 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.829332                       # Nu
 sim_ticks                                1829332258000                       # Number of ticks simulated
 final_tick                               1829332258000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4111639                       # Simulator instruction rate (inst/s)
-host_op_rate                                  4111633                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                           125278906724                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 291412                       # Number of bytes of host memory used
-host_seconds                                    14.60                       # Real time elapsed on the host
+host_inst_rate                                1921293                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1921291                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            58540553267                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 295828                       # Number of bytes of host memory used
+host_seconds                                    31.25                       # Real time elapsed on the host
 sim_insts                                    60038305                       # Number of instructions simulated
 sim_ops                                      60038305                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    71650816                       # Number of bytes read from this memory
@@ -89,8 +89,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              117189                       # number of writebacks
@@ -129,8 +129,8 @@ system.iocache.blocked_cycles::no_mshrs             0                       # nu
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
@@ -291,30 +291,30 @@ system.tsunami.ethernet.descDMAWrites               0                       # Nu
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
 system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
 system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
 system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
 system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
 system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
 system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
 system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
 system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
 system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
 system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
 system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
 system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
 system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
 system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu.icache.replacements                 919594                       # number of replacements
@@ -351,8 +351,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks          108                       # number of writebacks
@@ -410,8 +410,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       825183                       # number of writebacks
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 110cfac39..6299f010e 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -19,7 +19,6 @@ mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 pal=/dist/m5/system/binaries/ts_osfpal
-physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -31,7 +30,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[2]
+system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
@@ -41,8 +40,8 @@ ranges=8796093022208:18446744073709551615
 req_size=16
 resp_size=16
 write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[0]
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
 
 [system.cpu0]
 type=TimingSimpleCPU
@@ -75,7 +74,7 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -96,7 +95,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
 
 [system.cpu0.dtb]
 type=AlphaTLB
@@ -104,7 +103,7 @@ size=64
 
 [system.cpu0.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -125,7 +124,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
 
 [system.cpu0.interrupts]
 type=AlphaInterrupts
@@ -168,7 +167,7 @@ icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -189,7 +188,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[4]
+mem_side=system.toL2Bus.slave[3]
 
 [system.cpu1.dtb]
 type=AlphaTLB
@@ -197,7 +196,7 @@ size=64
 
 [system.cpu1.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -218,7 +217,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[3]
+mem_side=system.toL2Bus.slave[2]
 
 [system.cpu1.interrupts]
 type=AlphaInterrupts
@@ -283,11 +282,12 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
+master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
 type=BaseCache
-addr_range=0:8589934591
+addr_ranges=0:8589934591
 assoc=8
 block_size=64
 forward_snoops=false
@@ -307,12 +307,12 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[32]
-mem_side=system.membus.port[3]
+cpu_side=system.iobus.master[29]
+mem_side=system.membus.slave[1]
 
 [system.l2c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
 forward_snoops=true
@@ -332,8 +332,8 @@ tgts_per_mshr=16
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[4]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
 
 [system.membus]
 type=Bus
@@ -345,7 +345,8 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
+master=system.bridge.slave system.physmem.port[0]
+slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -364,14 +365,16 @@ warn_access=
 pio=system.membus.default
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[1]
 
 [system.simple_disk]
 type=SimpleDisk
@@ -399,7 +402,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
 
 [system.tsunami]
 type=Tsunami
@@ -416,7 +420,7 @@ pio_latency=1000
 platform=system.tsunami
 system=system
 terminal=system.terminal
-pio=system.iobus.port[25]
+pio=system.iobus.master[24]
 
 [system.tsunami.cchip]
 type=TsunamiCChip
@@ -424,7 +428,7 @@ pio_addr=8803072344064
 pio_latency=1000
 system=system
 tsunami=system.tsunami
-pio=system.iobus.port[1]
+pio=system.iobus.master[0]
 
 [system.tsunami.ethernet]
 type=NSGigE
@@ -493,9 +497,9 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
-pio=system.iobus.port[29]
+config=system.iobus.master[28]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -511,7 +515,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[9]
+pio=system.iobus.master[8]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
@@ -527,7 +531,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[20]
+pio=system.iobus.master[19]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
@@ -543,7 +547,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[21]
+pio=system.iobus.master[20]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
@@ -559,7 +563,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[10]
+pio=system.iobus.master[9]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
@@ -575,7 +579,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[12]
+pio=system.iobus.master[11]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
@@ -591,7 +595,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[13]
+pio=system.iobus.master[12]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
@@ -607,7 +611,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[14]
+pio=system.iobus.master[13]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
@@ -623,7 +627,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[15]
+pio=system.iobus.master[14]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
@@ -639,7 +643,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[16]
+pio=system.iobus.master[15]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
@@ -655,7 +659,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[17]
+pio=system.iobus.master[16]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
@@ -671,7 +675,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[18]
+pio=system.iobus.master[17]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
@@ -687,7 +691,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[19]
+pio=system.iobus.master[18]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
@@ -703,7 +707,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[11]
+pio=system.iobus.master[10]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
@@ -719,7 +723,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[8]
+pio=system.iobus.master[7]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
@@ -735,7 +739,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[3]
+pio=system.iobus.master[2]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
@@ -751,7 +755,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[4]
+pio=system.iobus.master[3]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
@@ -767,7 +771,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[5]
+pio=system.iobus.master[4]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
@@ -783,7 +787,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[6]
+pio=system.iobus.master[5]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
@@ -799,7 +803,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[7]
+pio=system.iobus.master[6]
 
 [system.tsunami.fb]
 type=BadDevice
@@ -807,7 +811,7 @@ devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=1000
 system=system
-pio=system.iobus.port[22]
+pio=system.iobus.master[21]
 
 [system.tsunami.ide]
 type=IdeController
@@ -861,9 +865,9 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[27]
-dma=system.iobus.port[28]
-pio=system.iobus.port[26]
+config=system.iobus.master[26]
+dma=system.iobus.slave[1]
+pio=system.iobus.master[25]
 
 [system.tsunami.io]
 type=TsunamiIO
@@ -874,7 +878,7 @@ system=system
 time=Thu Jan  1 00:00:00 2009
 tsunami=system.tsunami
 year_is_bcd=false
-pio=system.iobus.port[23]
+pio=system.iobus.master[22]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
@@ -882,7 +886,7 @@ pio_addr=8802535473152
 pio_latency=1000
 system=system
 tsunami=system.tsunami
-pio=system.iobus.port[2]
+pio=system.iobus.master[1]
 
 [system.tsunami.pciconfig]
 type=PciConfigAll
@@ -900,5 +904,5 @@ pio_latency=1000
 platform=system.tsunami
 system=system
 terminal=system.terminal
-pio=system.iobus.port[24]
+pio=system.iobus.master[23]
 
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index b1f645266..dc632ce62 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -1,12 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:10:02
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:41:25
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 562628000
 Exiting @ tick 1958647095000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 565674386..7ab3bb0af 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.958647                       # Nu
 sim_ticks                                1958647095000                       # Number of ticks simulated
 final_tick                               1958647095000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1989502                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1989500                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            65650485361                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 290388                       # Number of bytes of host memory used
-host_seconds                                    29.83                       # Real time elapsed on the host
+host_inst_rate                                 669282                       # Simulator instruction rate (inst/s)
+host_op_rate                                   669282                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            22085281308                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 295084                       # Number of bytes of host memory used
+host_seconds                                    88.69                       # Real time elapsed on the host
 sim_insts                                    59355643                       # Number of instructions simulated
 sim_ops                                      59355643                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    30050624                       # Number of bytes read from this memory
@@ -178,8 +178,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              119935                       # number of writebacks
@@ -336,7 +336,7 @@ system.iocache.blocked_cycles::no_targets            0                       # n
 system.iocache.blocked::no_mshrs                10459                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs  6176.122765                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41520                       # number of writebacks
@@ -514,8 +514,8 @@ system.cpu0.kern.mode_good::user                 1283
 system.cpu0.kern.mode_good::idle                    0                      
 system.cpu0.kern.mode_switch_good::kernel     0.175705                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_ticks::kernel      1954355762000     99.83%     99.83% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::user          3390072000      0.17%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
@@ -525,30 +525,30 @@ system.tsunami.ethernet.descDMAWrites               0                       # Nu
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
 system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
 system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
 system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
 system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
 system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
 system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
 system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
 system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
 system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
 system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
 system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
 system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
 system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
 system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu0.icache.replacements                915147                       # number of replacements
@@ -594,8 +594,8 @@ system.cpu0.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks           55                       # number of writebacks
@@ -692,8 +692,8 @@ system.cpu0.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks       786441                       # number of writebacks
@@ -908,8 +908,8 @@ system.cpu1.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks           14                       # number of writebacks
@@ -1006,8 +1006,8 @@ system.cpu1.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks        29784                       # number of writebacks
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index c8fe39e38..d5815e263 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -19,7 +19,6 @@ mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 pal=/dist/m5/system/binaries/ts_osfpal
-physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -31,7 +30,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[2]
+system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
@@ -41,8 +40,8 @@ ranges=8796093022208:18446744073709551615
 req_size=16
 resp_size=16
 write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[0]
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -75,7 +74,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -96,7 +95,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -104,7 +103,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -125,7 +124,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -190,11 +189,12 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
+master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
 type=BaseCache
-addr_range=0:8589934591
+addr_ranges=0:8589934591
 assoc=8
 block_size=64
 forward_snoops=false
@@ -214,12 +214,12 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[32]
-mem_side=system.membus.port[3]
+cpu_side=system.iobus.master[29]
+mem_side=system.membus.slave[1]
 
 [system.l2c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
 forward_snoops=true
@@ -239,8 +239,8 @@ tgts_per_mshr=16
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[4]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
 
 [system.membus]
 type=Bus
@@ -252,7 +252,8 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
+master=system.bridge.slave system.physmem.port[0]
+slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -271,14 +272,16 @@ warn_access=
 pio=system.membus.default
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[1]
 
 [system.simple_disk]
 type=SimpleDisk
@@ -306,7 +309,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.tsunami]
 type=Tsunami
@@ -323,7 +327,7 @@ pio_latency=1000
 platform=system.tsunami
 system=system
 terminal=system.terminal
-pio=system.iobus.port[25]
+pio=system.iobus.master[24]
 
 [system.tsunami.cchip]
 type=TsunamiCChip
@@ -331,7 +335,7 @@ pio_addr=8803072344064
 pio_latency=1000
 system=system
 tsunami=system.tsunami
-pio=system.iobus.port[1]
+pio=system.iobus.master[0]
 
 [system.tsunami.ethernet]
 type=NSGigE
@@ -400,9 +404,9 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
-pio=system.iobus.port[29]
+config=system.iobus.master[28]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -418,7 +422,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[9]
+pio=system.iobus.master[8]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
@@ -434,7 +438,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[20]
+pio=system.iobus.master[19]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
@@ -450,7 +454,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[21]
+pio=system.iobus.master[20]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
@@ -466,7 +470,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[10]
+pio=system.iobus.master[9]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
@@ -482,7 +486,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[12]
+pio=system.iobus.master[11]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
@@ -498,7 +502,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[13]
+pio=system.iobus.master[12]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
@@ -514,7 +518,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[14]
+pio=system.iobus.master[13]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
@@ -530,7 +534,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[15]
+pio=system.iobus.master[14]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
@@ -546,7 +550,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[16]
+pio=system.iobus.master[15]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
@@ -562,7 +566,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[17]
+pio=system.iobus.master[16]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
@@ -578,7 +582,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[18]
+pio=system.iobus.master[17]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
@@ -594,7 +598,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[19]
+pio=system.iobus.master[18]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
@@ -610,7 +614,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[11]
+pio=system.iobus.master[10]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
@@ -626,7 +630,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[8]
+pio=system.iobus.master[7]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
@@ -642,7 +646,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[3]
+pio=system.iobus.master[2]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
@@ -658,7 +662,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[4]
+pio=system.iobus.master[3]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
@@ -674,7 +678,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[5]
+pio=system.iobus.master[4]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
@@ -690,7 +694,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[6]
+pio=system.iobus.master[5]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
@@ -706,7 +710,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[7]
+pio=system.iobus.master[6]
 
 [system.tsunami.fb]
 type=BadDevice
@@ -714,7 +718,7 @@ devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=1000
 system=system
-pio=system.iobus.port[22]
+pio=system.iobus.master[21]
 
 [system.tsunami.ide]
 type=IdeController
@@ -768,9 +772,9 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[27]
-dma=system.iobus.port[28]
-pio=system.iobus.port[26]
+config=system.iobus.master[26]
+dma=system.iobus.slave[1]
+pio=system.iobus.master[25]
 
 [system.tsunami.io]
 type=TsunamiIO
@@ -781,7 +785,7 @@ system=system
 time=Thu Jan  1 00:00:00 2009
 tsunami=system.tsunami
 year_is_bcd=false
-pio=system.iobus.port[23]
+pio=system.iobus.master[22]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
@@ -789,7 +793,7 @@ pio_addr=8802535473152
 pio_latency=1000
 system=system
 tsunami=system.tsunami
-pio=system.iobus.port[2]
+pio=system.iobus.master[1]
 
 [system.tsunami.pciconfig]
 type=PciConfigAll
@@ -807,5 +811,5 @@ pio_latency=1000
 platform=system.tsunami
 system=system
 terminal=system.terminal
-pio=system.iobus.port[24]
+pio=system.iobus.master[23]
 
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index e3d6e41ac..7b3033c70 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -1,11 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:09:47
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:07
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1915548867000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 713b264a4..d0852c317 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.915549                       # Nu
 sim_ticks                                1915548867000                       # Number of ticks simulated
 final_tick                               1915548867000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1998214                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1998212                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            68184353129                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 288188                       # Number of bytes of host memory used
-host_seconds                                    28.09                       # Real time elapsed on the host
+host_inst_rate                                 646342                       # Simulator instruction rate (inst/s)
+host_op_rate                                   646342                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            22054916762                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 292620                       # Number of bytes of host memory used
+host_seconds                                    86.85                       # Real time elapsed on the host
 sim_insts                                    56137087                       # Number of instructions simulated
 sim_ops                                      56137087                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    29663360                       # Number of bytes read from this memory
@@ -110,8 +110,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              116650                       # number of writebacks
@@ -214,7 +214,7 @@ system.iocache.blocked_cycles::no_targets            0                       # n
 system.iocache.blocked::no_mshrs                10476                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs  6166.863307                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
@@ -399,30 +399,30 @@ system.tsunami.ethernet.descDMAWrites               0                       # Nu
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
 system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
 system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
 system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
 system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
 system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
 system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
 system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
 system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
 system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
 system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
 system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
 system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
 system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
 system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu.icache.replacements                 927683                       # number of replacements
@@ -468,8 +468,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks           85                       # number of writebacks
@@ -560,8 +560,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       826586                       # number of writebacks
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index 78c29faa1..b18e2b725 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -10,20 +10,18 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
 atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
-boot_loader_mem=system.realview.nvmem
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
 memories=system.physmem system.realview.nvmem
 midr_regval=890224640
 num_work_ids=16
-physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 work_begin_ckpt_count=0
@@ -63,7 +61,7 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
 [system.cpu0]
@@ -77,6 +75,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu0.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu0.interrupts
@@ -191,6 +190,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu1.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu1.interrupts
@@ -389,8 +389,10 @@ warn_access=warn
 pio=system.membus.default
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=true
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
@@ -621,8 +623,10 @@ system=system
 pio=system.iobus.master[22]
 
 [system.realview.nvmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
index 8b688fa3a..e36b1902c 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 16:34:57
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:20:57
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2411694099500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index f44938962..505cf865e 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -4,22 +4,13 @@ sim_seconds                                  2.411694                       # Nu
 sim_ticks                                2411694099500                       # Number of ticks simulated
 final_tick                               2411694099500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2019241                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2610327                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            79123006525                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 377328                       # Number of bytes of host memory used
-host_seconds                                    30.48                       # Real time elapsed on the host
+host_inst_rate                                 781676                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1010494                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            30629621173                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 383944                       # Number of bytes of host memory used
+host_seconds                                    78.74                       # Real time elapsed on the host
 sim_insts                                    61547057                       # Number of instructions simulated
 sim_ops                                      79563547                       # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read                   68                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read              68                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
-system.realview.nvmem.num_reads                    17                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
-system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
-system.realview.nvmem.bw_read                      28                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read                 28                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total                     28                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read                   123270308                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                1011392                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 10185232                       # Number of bytes written to this memory
@@ -30,6 +21,15 @@ system.physmem.bw_read                       51113575                       # To
 system.physmem.bw_inst_read                    419370                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write                       4223269                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total                      55336844                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read                   68                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read              68                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
+system.realview.nvmem.num_reads                    17                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
+system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
+system.realview.nvmem.bw_read                      28                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read                 28                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total                     28                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        127720                       # number of replacements
 system.l2c.tagsinuse                     25547.920882                       # Cycle average of tags in use
 system.l2c.total_refs                         1498993                       # Total number of references to valid blocks.
@@ -201,8 +201,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              111818                       # number of writebacks
@@ -314,8 +314,8 @@ system.cpu0.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks        24728                       # number of writebacks
@@ -376,8 +376,8 @@ system.cpu0.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks       339627                       # number of writebacks
@@ -483,8 +483,8 @@ system.cpu1.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks        13905                       # number of writebacks
@@ -545,8 +545,8 @@ system.cpu1.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks       202202                       # number of writebacks
@@ -556,14 +556,14 @@ system.iocache.replacements                         0                       # nu
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
+system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
index 877c03770..7edf5b1c7 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
@@ -1 +1 @@
-build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual passed.
+build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual FAILED!
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 81760af9f..720edf3cb 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -10,20 +10,18 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
 atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
-boot_loader_mem=system.realview.nvmem
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
 memories=system.physmem system.realview.nvmem
 midr_regval=890224640
 num_work_ids=16
-physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 work_begin_ckpt_count=0
@@ -63,7 +61,7 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
 [system.cpu]
@@ -77,6 +75,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -275,8 +274,10 @@ warn_access=warn
 pio=system.membus.default
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=true
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
@@ -507,8 +508,10 @@ system=system
 pio=system.iobus.master[22]
 
 [system.realview.nvmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index 60dab884c..d76ea9eaa 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 16:34:16
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:20:57
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2332316587000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index c2b68c5b8..75b897a18 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -4,22 +4,13 @@ sim_seconds                                  2.332317                       # Nu
 sim_ticks                                2332316587000                       # Number of ticks simulated
 final_tick                               2332316587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1994377                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2575566                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            78489486028                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 377288                       # Number of bytes of host memory used
-host_seconds                                    29.72                       # Real time elapsed on the host
+host_inst_rate                                 864582                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1116533                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            34025972839                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 383900                       # Number of bytes of host memory used
+host_seconds                                    68.55                       # Real time elapsed on the host
 sim_insts                                    59262896                       # Number of instructions simulated
 sim_ops                                      76532951                       # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read                   20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read              20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
-system.realview.nvmem.num_reads                     5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
-system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
-system.realview.nvmem.bw_read                       9                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read                  9                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total                      9                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read                   122663536                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 941280                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  9577800                       # Number of bytes written to this memory
@@ -30,6 +21,15 @@ system.physmem.bw_read                       52593004                       # To
 system.physmem.bw_inst_read                    403582                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write                       4106561                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total                      56699565                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read                   20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read              20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
+system.realview.nvmem.num_reads                     5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
+system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
+system.realview.nvmem.bw_read                       9                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read                  9                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total                      9                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        116822                       # number of replacements
 system.l2c.tagsinuse                     24240.388395                       # Cycle average of tags in use
 system.l2c.total_refs                         1520830                       # Total number of references to valid blocks.
@@ -126,8 +126,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              102531                       # number of writebacks
@@ -239,8 +239,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        44721                       # number of writebacks
@@ -298,8 +298,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       559892                       # number of writebacks
@@ -309,14 +309,14 @@ system.iocache.replacements                         0                       # nu
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
+system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
index 3643c334f..5d3e81846 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
@@ -1 +1 @@
-build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic passed.
+build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index d4b7d32fd..e58e54e5c 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -10,20 +10,18 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
 atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
-boot_loader_mem=system.realview.nvmem
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
 memories=system.physmem system.realview.nvmem
 midr_regval=890224640
 num_work_ids=16
-physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 work_begin_ckpt_count=0
@@ -63,7 +61,7 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
 [system.cpu0]
@@ -383,8 +381,10 @@ warn_access=warn
 pio=system.membus.default
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=true
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
@@ -615,8 +615,10 @@ system=system
 pio=system.iobus.master[22]
 
 [system.realview.nvmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
index 79a5c7d79..ae01846e4 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 16:36:56
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:20:58
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2669611225000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index ed51beca1..0ac70eccc 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -4,22 +4,13 @@ sim_seconds                                  2.669611                       # Nu
 sim_ticks                                2669611225000                       # Number of ticks simulated
 final_tick                               2669611225000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 887100                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1134851                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            38636092154                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 379132                       # Number of bytes of host memory used
-host_seconds                                    69.10                       # Real time elapsed on the host
+host_inst_rate                                 280373                       # Simulator instruction rate (inst/s)
+host_op_rate                                   358676                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            12211141498                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 385748                       # Number of bytes of host memory used
+host_seconds                                   218.62                       # Real time elapsed on the host
 sim_insts                                    61295282                       # Number of instructions simulated
 sim_ops                                      78413979                       # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read                   68                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read              68                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
-system.realview.nvmem.num_reads                    17                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
-system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
-system.realview.nvmem.bw_read                      25                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read                 25                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total                     25                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read                   134334820                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                1003520                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 10194256                       # Number of bytes written to this memory
@@ -30,6 +21,15 @@ system.physmem.bw_read                       50319994                       # To
 system.physmem.bw_inst_read                    375905                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write                       3818629                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total                      54138623                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read                   68                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read              68                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
+system.realview.nvmem.num_reads                    17                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
+system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
+system.realview.nvmem.bw_read                      25                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read                 25                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total                     25                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        127749                       # number of replacements
 system.l2c.tagsinuse                     26172.513447                       # Cycle average of tags in use
 system.l2c.total_refs                         1540413                       # Total number of references to valid blocks.
@@ -267,8 +267,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              111955                       # number of writebacks
@@ -553,8 +553,8 @@ system.cpu0.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks        12960                       # number of writebacks
@@ -657,8 +657,8 @@ system.cpu0.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks       294891                       # number of writebacks
@@ -821,8 +821,8 @@ system.cpu1.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks        27998                       # number of writebacks
@@ -925,8 +925,8 @@ system.cpu1.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks       253551                       # number of writebacks
@@ -981,14 +981,14 @@ system.iocache.replacements                         0                       # nu
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
+system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342252853622                       # number of ReadReq MSHR uncacheable cycles
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
index d529dbd88..8ae0da5a8 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
@@ -1 +1 @@
-build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual passed.
+build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual FAILED!
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index cb6ee4aa9..bdfa88421 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -10,20 +10,18 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
 atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
-boot_loader_mem=system.realview.nvmem
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
 memories=system.physmem system.realview.nvmem
 midr_regval=890224640
 num_work_ids=16
-physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 work_begin_ckpt_count=0
@@ -63,7 +61,7 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
 [system.cpu]
@@ -272,8 +270,10 @@ warn_access=warn
 pio=system.membus.default
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=true
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
@@ -504,8 +504,10 @@ system=system
 pio=system.iobus.master[22]
 
 [system.realview.nvmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index 1758a0df6..480141f03 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 16:35:38
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:20:58
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2591441692000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index 2c94df23b..4b750a42d 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -4,22 +4,13 @@ sim_seconds                                  2.591442                       # Nu
 sim_ticks                                2591441692000                       # Number of ticks simulated
 final_tick                               2591441692000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 879685                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1123921                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            38588641896                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 377580                       # Number of bytes of host memory used
-host_seconds                                    67.16                       # Real time elapsed on the host
+host_inst_rate                                 302887                       # Simulator instruction rate (inst/s)
+host_op_rate                                   386981                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            13286578938                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 384192                       # Number of bytes of host memory used
+host_seconds                                   195.04                       # Real time elapsed on the host
 sim_insts                                    59075703                       # Number of instructions simulated
 sim_ops                                      75477535                       # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read                   20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read              20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
-system.realview.nvmem.num_reads                     5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
-system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
-system.realview.nvmem.bw_read                       8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read                  8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total                      8                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read                   133655408                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 949920                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  9634312                       # Number of bytes written to this memory
@@ -30,6 +21,15 @@ system.physmem.bw_read                       51575696                       # To
 system.physmem.bw_inst_read                    366560                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write                       3717742                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total                      55293438                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read                   20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read              20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
+system.realview.nvmem.num_reads                     5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
+system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
+system.realview.nvmem.bw_read                       8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read                  8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total                      8                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        117809                       # number of replacements
 system.l2c.tagsinuse                     24929.234619                       # Cycle average of tags in use
 system.l2c.total_refs                         1535239                       # Total number of references to valid blocks.
@@ -159,8 +159,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              103410                       # number of writebacks
@@ -360,8 +360,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        45661                       # number of writebacks
@@ -458,8 +458,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       564388                       # number of writebacks
@@ -508,14 +508,14 @@ system.iocache.replacements                         0                       # nu
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
+system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341941439938                       # number of ReadReq MSHR uncacheable cycles
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
index 48ab2f520..4523c3c36 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
@@ -1 +1 @@
-build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing FAILED!
+build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing FAILED!
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index 1885ca8f8..d5bc006d3 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -20,7 +20,6 @@ load_addr_mask=18446744073709551615
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=tests/halt.sh
 smbios_table=system.smbios_table
 symbolfile=
@@ -31,7 +30,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[3]
+system_port=system.membus.slave[1]
 
 [system.acpi_description_table_pointer]
 type=X86ACPIRSDP
@@ -58,8 +57,8 @@ ranges=11529215046068469760:11529215046068473855
 req_size=16
 resp_size=16
 write_ack=false
-master=system.membus.port[2]
-slave=system.iobus.port[1]
+master=system.membus.slave[0]
+slave=system.iobus.master[0]
 
 [system.bridge]
 type=Bridge
@@ -69,8 +68,8 @@ ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 1383505805
 req_size=16
 resp_size=16
 write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[1]
+master=system.iobus.slave[0]
+slave=system.membus.master[1]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -83,6 +82,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -106,7 +106,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -127,7 +127,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -142,7 +142,7 @@ port=system.cpu.dtb_walker_cache.cpu_side
 
 [system.cpu.dtb_walker_cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -163,11 +163,11 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dtb.walker.port
-mem_side=system.toL2Bus.port[4]
+mem_side=system.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -188,7 +188,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -196,8 +196,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[7]
-pio=system.membus.port[6]
+int_master=system.membus.slave[4]
+int_slave=system.membus.master[3]
+pio=system.membus.master[2]
 
 [system.cpu.itb]
 type=X86TLB
@@ -212,7 +213,7 @@ port=system.cpu.itb_walker_cache.cpu_side
 
 [system.cpu.itb_walker_cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -233,7 +234,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.itb.walker.port
-mem_side=system.toL2Bus.port[3]
+mem_side=system.toL2Bus.slave[2]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -610,11 +611,12 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.pc.pciconfig.pio
-port=system.bridge.master system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
 
 [system.iocache]
 type=BaseCache
-addr_range=0:134217727
+addr_ranges=0:134217727
 assoc=8
 block_size=64
 forward_snoops=false
@@ -634,12 +636,12 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[21]
-mem_side=system.membus.port[4]
+cpu_side=system.iobus.master[18]
+mem_side=system.membus.slave[2]
 
 [system.l2c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
 forward_snoops=true
@@ -659,8 +661,8 @@ tgts_per_mshr=16
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[5]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[3]
 
 [system.membus]
 type=Bus
@@ -672,7 +674,8 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.slave system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -710,7 +713,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[15]
+pio=system.iobus.master[12]
 
 [system.pc.com_1]
 type=Uart8250
@@ -720,7 +723,7 @@ pio_latency=1000
 platform=system.pc
 system=system
 terminal=system.pc.com_1.terminal
-pio=system.iobus.port[16]
+pio=system.iobus.master[13]
 
 [system.pc.com_1.terminal]
 type=Terminal
@@ -750,7 +753,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[17]
+pio=system.iobus.master[14]
 
 [system.pc.fake_com_3]
 type=IsaFake
@@ -766,7 +769,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[18]
+pio=system.iobus.master[15]
 
 [system.pc.fake_com_4]
 type=IsaFake
@@ -782,7 +785,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[19]
+pio=system.iobus.master[16]
 
 [system.pc.fake_floppy]
 type=IsaFake
@@ -798,7 +801,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[20]
+pio=system.iobus.master[17]
 
 [system.pc.i_dont_exist]
 type=IsaFake
@@ -814,7 +817,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[14]
+pio=system.iobus.master[11]
 
 [system.pc.pciconfig]
 type=PciConfigAll
@@ -847,7 +850,7 @@ pio_addr=9223372036854775920
 pio_latency=1000
 system=system
 time=Sun Jan  1 00:00:00 2012
-pio=system.iobus.port[2]
+pio=system.iobus.master[1]
 
 [system.pc.south_bridge.cmos.int_pin]
 type=X86IntSourcePin
@@ -857,7 +860,7 @@ type=I8237
 pio_addr=9223372036854775808
 pio_latency=1000
 system=system
-pio=system.iobus.port[3]
+pio=system.iobus.master[2]
 
 [system.pc.south_bridge.ide]
 type=IdeController
@@ -912,9 +915,9 @@ pci_func=0
 pio_latency=1000
 platform=system.pc
 system=system
-config=system.iobus.port[5]
-dma=system.iobus.port[6]
-pio=system.iobus.port[4]
+config=system.iobus.master[4]
+dma=system.iobus.slave[1]
+pio=system.iobus.master[3]
 
 [system.pc.south_bridge.ide.disks0]
 type=IdeDisk
@@ -1041,8 +1044,8 @@ int_latency=1000
 pio_addr=4273995776
 pio_latency=1000
 system=system
-int_port=system.iobus.port[13]
-pio=system.iobus.port[12]
+int_master=system.iobus.slave[2]
+pio=system.iobus.master[10]
 
 [system.pc.south_bridge.keyboard]
 type=I8042
@@ -1054,7 +1057,7 @@ mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
 pio_addr=0
 pio_latency=1000
 system=system
-pio=system.iobus.port[7]
+pio=system.iobus.master[5]
 
 [system.pc.south_bridge.keyboard.keyboard_int_pin]
 type=X86IntSourcePin
@@ -1071,7 +1074,7 @@ pio_addr=9223372036854775840
 pio_latency=1000
 slave=system.pc.south_bridge.pic2
 system=system
-pio=system.iobus.port[8]
+pio=system.iobus.master[6]
 
 [system.pc.south_bridge.pic1.output]
 type=X86IntSourcePin
@@ -1085,7 +1088,7 @@ pio_addr=9223372036854775968
 pio_latency=1000
 slave=Null
 system=system
-pio=system.iobus.port[9]
+pio=system.iobus.master[7]
 
 [system.pc.south_bridge.pic2.output]
 type=X86IntSourcePin
@@ -1097,7 +1100,7 @@ int_pin=system.pc.south_bridge.pit.int_pin
 pio_addr=9223372036854775872
 pio_latency=1000
 system=system
-pio=system.iobus.port[10]
+pio=system.iobus.master[8]
 
 [system.pc.south_bridge.pit.int_pin]
 type=X86IntSourcePin
@@ -1108,17 +1111,19 @@ i8254=system.pc.south_bridge.pit
 pio_addr=9223372036854775905
 pio_latency=1000
 system=system
-pio=system.iobus.port[11]
+pio=system.iobus.master[9]
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.master[0]
 
 [system.smbios_table]
 type=X86SMBiosSMBiosTable
@@ -1149,5 +1154,6 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
 
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
index e4d0a5032..f8c61dd9a 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
@@ -1,12 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:53
-gem5 started Feb 11 2012 14:04:48
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:50:18
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5112043255000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 21f7dfc5d..03b343541 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.112043                       # Nu
 sim_ticks                                5112043255000                       # Number of ticks simulated
 final_tick                               5112043255000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1772716                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3629762                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            45353186641                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 350348                       # Number of bytes of host memory used
-host_seconds                                   112.72                       # Real time elapsed on the host
+host_inst_rate                                 720353                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1474974                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            18429520570                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 355156                       # Number of bytes of host memory used
+host_seconds                                   277.38                       # Real time elapsed on the host
 sim_insts                                   199813913                       # Number of instructions simulated
 sim_ops                                     409133277                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    15568704                       # Number of bytes read from this memory
@@ -117,8 +117,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              144472                       # number of writebacks
@@ -157,8 +157,8 @@ system.iocache.blocked_cycles::no_mshrs             0                       # nu
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
@@ -234,8 +234,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks          809                       # number of writebacks
@@ -279,8 +279,8 @@ system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
 system.cpu.itb_walker_cache.writebacks::writebacks          518                       # number of writebacks
@@ -320,8 +320,8 @@ system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
 system.cpu.dtb_walker_cache.writebacks::writebacks         2517                       # number of writebacks
@@ -368,8 +368,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      1525559                       # number of writebacks
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index baa9c805b..5b2a3d4f5 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -20,7 +20,6 @@ load_addr_mask=18446744073709551615
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=tests/halt.sh
 smbios_table=system.smbios_table
 symbolfile=
@@ -31,7 +30,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[3]
+system_port=system.membus.slave[1]
 
 [system.acpi_description_table_pointer]
 type=X86ACPIRSDP
@@ -58,8 +57,8 @@ ranges=11529215046068469760:11529215046068473855
 req_size=16
 resp_size=16
 write_ack=false
-master=system.membus.port[2]
-slave=system.iobus.port[1]
+master=system.membus.slave[0]
+slave=system.iobus.master[0]
 
 [system.bridge]
 type=Bridge
@@ -69,8 +68,8 @@ ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 1383505805
 req_size=16
 resp_size=16
 write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[1]
+master=system.iobus.slave[0]
+slave=system.membus.master[1]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -103,7 +102,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -124,7 +123,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -139,7 +138,7 @@ port=system.cpu.dtb_walker_cache.cpu_side
 
 [system.cpu.dtb_walker_cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -160,11 +159,11 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dtb.walker.port
-mem_side=system.toL2Bus.port[4]
+mem_side=system.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -185,7 +184,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -193,8 +192,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[7]
-pio=system.membus.port[6]
+int_master=system.membus.slave[4]
+int_slave=system.membus.master[3]
+pio=system.membus.master[2]
 
 [system.cpu.itb]
 type=X86TLB
@@ -209,7 +209,7 @@ port=system.cpu.itb_walker_cache.cpu_side
 
 [system.cpu.itb_walker_cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -230,7 +230,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.itb.walker.port
-mem_side=system.toL2Bus.port[3]
+mem_side=system.toL2Bus.slave[2]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -607,11 +607,12 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.pc.pciconfig.pio
-port=system.bridge.master system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
 
 [system.iocache]
 type=BaseCache
-addr_range=0:134217727
+addr_ranges=0:134217727
 assoc=8
 block_size=64
 forward_snoops=false
@@ -631,12 +632,12 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[21]
-mem_side=system.membus.port[4]
+cpu_side=system.iobus.master[18]
+mem_side=system.membus.slave[2]
 
 [system.l2c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
 forward_snoops=true
@@ -656,8 +657,8 @@ tgts_per_mshr=16
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[5]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[3]
 
 [system.membus]
 type=Bus
@@ -669,7 +670,8 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.slave system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -707,7 +709,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[15]
+pio=system.iobus.master[12]
 
 [system.pc.com_1]
 type=Uart8250
@@ -717,7 +719,7 @@ pio_latency=1000
 platform=system.pc
 system=system
 terminal=system.pc.com_1.terminal
-pio=system.iobus.port[16]
+pio=system.iobus.master[13]
 
 [system.pc.com_1.terminal]
 type=Terminal
@@ -747,7 +749,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[17]
+pio=system.iobus.master[14]
 
 [system.pc.fake_com_3]
 type=IsaFake
@@ -763,7 +765,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[18]
+pio=system.iobus.master[15]
 
 [system.pc.fake_com_4]
 type=IsaFake
@@ -779,7 +781,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[19]
+pio=system.iobus.master[16]
 
 [system.pc.fake_floppy]
 type=IsaFake
@@ -795,7 +797,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[20]
+pio=system.iobus.master[17]
 
 [system.pc.i_dont_exist]
 type=IsaFake
@@ -811,7 +813,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[14]
+pio=system.iobus.master[11]
 
 [system.pc.pciconfig]
 type=PciConfigAll
@@ -844,7 +846,7 @@ pio_addr=9223372036854775920
 pio_latency=1000
 system=system
 time=Sun Jan  1 00:00:00 2012
-pio=system.iobus.port[2]
+pio=system.iobus.master[1]
 
 [system.pc.south_bridge.cmos.int_pin]
 type=X86IntSourcePin
@@ -854,7 +856,7 @@ type=I8237
 pio_addr=9223372036854775808
 pio_latency=1000
 system=system
-pio=system.iobus.port[3]
+pio=system.iobus.master[2]
 
 [system.pc.south_bridge.ide]
 type=IdeController
@@ -909,9 +911,9 @@ pci_func=0
 pio_latency=1000
 platform=system.pc
 system=system
-config=system.iobus.port[5]
-dma=system.iobus.port[6]
-pio=system.iobus.port[4]
+config=system.iobus.master[4]
+dma=system.iobus.slave[1]
+pio=system.iobus.master[3]
 
 [system.pc.south_bridge.ide.disks0]
 type=IdeDisk
@@ -1038,8 +1040,8 @@ int_latency=1000
 pio_addr=4273995776
 pio_latency=1000
 system=system
-int_port=system.iobus.port[13]
-pio=system.iobus.port[12]
+int_master=system.iobus.slave[2]
+pio=system.iobus.master[10]
 
 [system.pc.south_bridge.keyboard]
 type=I8042
@@ -1051,7 +1053,7 @@ mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
 pio_addr=0
 pio_latency=1000
 system=system
-pio=system.iobus.port[7]
+pio=system.iobus.master[5]
 
 [system.pc.south_bridge.keyboard.keyboard_int_pin]
 type=X86IntSourcePin
@@ -1068,7 +1070,7 @@ pio_addr=9223372036854775840
 pio_latency=1000
 slave=system.pc.south_bridge.pic2
 system=system
-pio=system.iobus.port[8]
+pio=system.iobus.master[6]
 
 [system.pc.south_bridge.pic1.output]
 type=X86IntSourcePin
@@ -1082,7 +1084,7 @@ pio_addr=9223372036854775968
 pio_latency=1000
 slave=Null
 system=system
-pio=system.iobus.port[9]
+pio=system.iobus.master[7]
 
 [system.pc.south_bridge.pic2.output]
 type=X86IntSourcePin
@@ -1094,7 +1096,7 @@ int_pin=system.pc.south_bridge.pit.int_pin
 pio_addr=9223372036854775872
 pio_latency=1000
 system=system
-pio=system.iobus.port[10]
+pio=system.iobus.master[8]
 
 [system.pc.south_bridge.pit.int_pin]
 type=X86IntSourcePin
@@ -1105,17 +1107,19 @@ i8254=system.pc.south_bridge.pit
 pio_addr=9223372036854775905
 pio_latency=1000
 system=system
-pio=system.iobus.port[11]
+pio=system.iobus.master[9]
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.master[0]
 
 [system.smbios_table]
 type=X86SMBiosSMBiosTable
@@ -1146,5 +1150,6 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
 
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index 9ff593dd3..5fdad8343 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@@ -1,12 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:53
-gem5 started Feb 11 2012 14:06:52
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:50:18
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5195470393000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 6ded30fe7..68bf4f343 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.195470                       # Nu
 sim_ticks                                5195470393000                       # Number of ticks simulated
 final_tick                               5195470393000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1225094                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2351489                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            46076516791                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 346880                       # Number of bytes of host memory used
-host_seconds                                   112.76                       # Real time elapsed on the host
+host_inst_rate                                 387917                       # Simulator instruction rate (inst/s)
+host_op_rate                                   744582                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            14589799311                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 351980                       # Number of bytes of host memory used
+host_seconds                                   356.10                       # Real time elapsed on the host
 sim_insts                                   138138472                       # Number of instructions simulated
 sim_ops                                     265147881                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    13764096                       # Number of bytes read from this memory
@@ -150,8 +150,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              116255                       # number of writebacks
@@ -278,7 +278,7 @@ system.iocache.blocked_cycles::no_targets            0                       # n
 system.iocache.blocked::no_mshrs                11299                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs  6156.708027                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46668                       # number of writebacks
@@ -387,8 +387,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks          805                       # number of writebacks
@@ -459,8 +459,8 @@ system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
 system.cpu.itb_walker_cache.writebacks::writebacks          826                       # number of writebacks
@@ -527,8 +527,8 @@ system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
 system.cpu.dtb_walker_cache.writebacks::writebacks         2985                       # number of writebacks
@@ -605,8 +605,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      1529951                       # number of writebacks
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index 7a0c1d8ae..fdc643fe0 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -11,8 +11,7 @@ mem_mode=atomic
 memories=drivesys.physmem
 num_work_ids=16
 pal=/dist/m5/system/binaries/ts_osfpal
-physmem=drivesys.physmem
-readfile=/tmp/gem5.ali/configs/boot/netperf-server.rcS
+readfile=/n/piton/z/nate/work/m5/work/configs/boot/netperf-server.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -23,7 +22,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=drivesys.membus.port[2]
+system_port=drivesys.membus.slave[0]
 
 [drivesys.bridge]
 type=Bridge
@@ -33,8 +32,8 @@ ranges=8796093022208:18446744073709551615
 req_size=16
 resp_size=16
 write_ack=false
-master=drivesys.iobus.port[0]
-slave=drivesys.membus.port[0]
+master=drivesys.iobus.slave[0]
+slave=drivesys.membus.master[0]
 
 [drivesys.cpu]
 type=AtomicSimpleCPU
@@ -47,6 +46,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=drivesys.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=drivesys.cpu.interrupts
@@ -65,8 +65,8 @@ system=drivesys
 tracer=drivesys.cpu.tracer
 width=1
 workload=
-dcache_port=drivesys.membus.port[4]
-icache_port=drivesys.membus.port[3]
+dcache_port=drivesys.membus.slave[2]
+icache_port=drivesys.membus.slave[1]
 
 [drivesys.cpu.dtb]
 type=AlphaTLB
@@ -134,8 +134,8 @@ ranges=0:8589934592
 req_size=16
 resp_size=16
 write_ack=false
-master=drivesys.membus.port[5]
-slave=drivesys.iobus.port[32]
+master=drivesys.membus.slave[3]
+slave=drivesys.iobus.master[29]
 
 [drivesys.iobus]
 type=Bus
@@ -146,7 +146,8 @@ header_cycles=1
 use_default_range=true
 width=64
 default=drivesys.tsunami.pciconfig.pio
-port=drivesys.bridge.master drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ide.config drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.tsunami.ethernet.dma drivesys.iobridge.slave
+master=drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ide.config drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.iobridge.slave
+slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.dma
 
 [drivesys.membus]
 type=Bus
@@ -158,7 +159,8 @@ header_cycles=1
 use_default_range=false
 width=64
 default=drivesys.membus.badaddr_responder.pio
-port=drivesys.bridge.slave drivesys.physmem.port[0] drivesys.system_port drivesys.cpu.icache_port drivesys.cpu.dcache_port drivesys.iobridge.master
+master=drivesys.bridge.slave drivesys.physmem.port[0]
+slave=drivesys.system_port drivesys.cpu.icache_port drivesys.cpu.dcache_port drivesys.iobridge.master
 
 [drivesys.membus.badaddr_responder]
 type=IsaFake
@@ -177,14 +179,16 @@ warn_access=
 pio=drivesys.membus.default
 
 [drivesys.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=drivesys.membus.port[1]
+port=drivesys.membus.master[1]
 
 [drivesys.simple_disk]
 type=SimpleDisk
@@ -219,7 +223,7 @@ pio_latency=1000
 platform=drivesys.tsunami
 system=drivesys
 terminal=drivesys.terminal
-pio=drivesys.iobus.port[25]
+pio=drivesys.iobus.master[24]
 
 [drivesys.tsunami.cchip]
 type=TsunamiCChip
@@ -227,7 +231,7 @@ pio_addr=8803072344064
 pio_latency=1000
 system=drivesys
 tsunami=drivesys.tsunami
-pio=drivesys.iobus.port[1]
+pio=drivesys.iobus.master[0]
 
 [drivesys.tsunami.ethernet]
 type=NSGigE
@@ -296,10 +300,10 @@ system=drivesys
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=drivesys.iobus.port[30]
-dma=drivesys.iobus.port[31]
+config=drivesys.iobus.master[28]
+dma=drivesys.iobus.slave[2]
 interface=etherlink.int1
-pio=drivesys.iobus.port[29]
+pio=drivesys.iobus.master[27]
 
 [drivesys.tsunami.fake_OROM]
 type=IsaFake
@@ -315,7 +319,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[9]
+pio=drivesys.iobus.master[8]
 
 [drivesys.tsunami.fake_ata0]
 type=IsaFake
@@ -331,7 +335,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[20]
+pio=drivesys.iobus.master[19]
 
 [drivesys.tsunami.fake_ata1]
 type=IsaFake
@@ -347,7 +351,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[21]
+pio=drivesys.iobus.master[20]
 
 [drivesys.tsunami.fake_pnp_addr]
 type=IsaFake
@@ -363,7 +367,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[10]
+pio=drivesys.iobus.master[9]
 
 [drivesys.tsunami.fake_pnp_read0]
 type=IsaFake
@@ -379,7 +383,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[12]
+pio=drivesys.iobus.master[11]
 
 [drivesys.tsunami.fake_pnp_read1]
 type=IsaFake
@@ -395,7 +399,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[13]
+pio=drivesys.iobus.master[12]
 
 [drivesys.tsunami.fake_pnp_read2]
 type=IsaFake
@@ -411,7 +415,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[14]
+pio=drivesys.iobus.master[13]
 
 [drivesys.tsunami.fake_pnp_read3]
 type=IsaFake
@@ -427,7 +431,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[15]
+pio=drivesys.iobus.master[14]
 
 [drivesys.tsunami.fake_pnp_read4]
 type=IsaFake
@@ -443,7 +447,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[16]
+pio=drivesys.iobus.master[15]
 
 [drivesys.tsunami.fake_pnp_read5]
 type=IsaFake
@@ -459,7 +463,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[17]
+pio=drivesys.iobus.master[16]
 
 [drivesys.tsunami.fake_pnp_read6]
 type=IsaFake
@@ -475,7 +479,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[18]
+pio=drivesys.iobus.master[17]
 
 [drivesys.tsunami.fake_pnp_read7]
 type=IsaFake
@@ -491,7 +495,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[19]
+pio=drivesys.iobus.master[18]
 
 [drivesys.tsunami.fake_pnp_write]
 type=IsaFake
@@ -507,7 +511,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[11]
+pio=drivesys.iobus.master[10]
 
 [drivesys.tsunami.fake_ppc]
 type=IsaFake
@@ -523,7 +527,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[8]
+pio=drivesys.iobus.master[7]
 
 [drivesys.tsunami.fake_sm_chip]
 type=IsaFake
@@ -539,7 +543,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[3]
+pio=drivesys.iobus.master[2]
 
 [drivesys.tsunami.fake_uart1]
 type=IsaFake
@@ -555,7 +559,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[4]
+pio=drivesys.iobus.master[3]
 
 [drivesys.tsunami.fake_uart2]
 type=IsaFake
@@ -571,7 +575,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[5]
+pio=drivesys.iobus.master[4]
 
 [drivesys.tsunami.fake_uart3]
 type=IsaFake
@@ -587,7 +591,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[6]
+pio=drivesys.iobus.master[5]
 
 [drivesys.tsunami.fake_uart4]
 type=IsaFake
@@ -603,7 +607,7 @@ ret_data8=255
 system=drivesys
 update_data=false
 warn_access=
-pio=drivesys.iobus.port[7]
+pio=drivesys.iobus.master[6]
 
 [drivesys.tsunami.fb]
 type=BadDevice
@@ -611,7 +615,7 @@ devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=1000
 system=drivesys
-pio=drivesys.iobus.port[22]
+pio=drivesys.iobus.master[21]
 
 [drivesys.tsunami.ide]
 type=IdeController
@@ -665,9 +669,9 @@ pci_func=0
 pio_latency=1000
 platform=drivesys.tsunami
 system=drivesys
-config=drivesys.iobus.port[27]
-dma=drivesys.iobus.port[28]
-pio=drivesys.iobus.port[26]
+config=drivesys.iobus.master[26]
+dma=drivesys.iobus.slave[1]
+pio=drivesys.iobus.master[25]
 
 [drivesys.tsunami.io]
 type=TsunamiIO
@@ -678,7 +682,7 @@ system=drivesys
 time=Thu Jan  1 00:00:00 2009
 tsunami=drivesys.tsunami
 year_is_bcd=false
-pio=drivesys.iobus.port[23]
+pio=drivesys.iobus.master[22]
 
 [drivesys.tsunami.pchip]
 type=TsunamiPChip
@@ -686,7 +690,7 @@ pio_addr=8802535473152
 pio_latency=1000
 system=drivesys
 tsunami=drivesys.tsunami
-pio=drivesys.iobus.port[2]
+pio=drivesys.iobus.master[1]
 
 [drivesys.tsunami.pciconfig]
 type=PciConfigAll
@@ -704,7 +708,7 @@ pio_latency=1000
 platform=drivesys.tsunami
 system=drivesys
 terminal=drivesys.terminal
-pio=drivesys.iobus.port[24]
+pio=drivesys.iobus.master[23]
 
 [etherdump]
 type=EtherDump
@@ -741,8 +745,7 @@ mem_mode=atomic
 memories=testsys.physmem
 num_work_ids=16
 pal=/dist/m5/system/binaries/ts_osfpal
-physmem=testsys.physmem
-readfile=/tmp/gem5.ali/configs/boot/netperf-stream-client.rcS
+readfile=/n/piton/z/nate/work/m5/work/configs/boot/netperf-stream-client.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -753,7 +756,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=testsys.membus.port[2]
+system_port=testsys.membus.slave[0]
 
 [testsys.bridge]
 type=Bridge
@@ -763,8 +766,8 @@ ranges=8796093022208:18446744073709551615
 req_size=16
 resp_size=16
 write_ack=false
-master=testsys.iobus.port[0]
-slave=testsys.membus.port[0]
+master=testsys.iobus.slave[0]
+slave=testsys.membus.master[0]
 
 [testsys.cpu]
 type=AtomicSimpleCPU
@@ -777,6 +780,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=testsys.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=testsys.cpu.interrupts
@@ -795,8 +799,8 @@ system=testsys
 tracer=testsys.cpu.tracer
 width=1
 workload=
-dcache_port=testsys.membus.port[4]
-icache_port=testsys.membus.port[3]
+dcache_port=testsys.membus.slave[2]
+icache_port=testsys.membus.slave[1]
 
 [testsys.cpu.dtb]
 type=AlphaTLB
@@ -864,8 +868,8 @@ ranges=0:8589934592
 req_size=16
 resp_size=16
 write_ack=false
-master=testsys.membus.port[5]
-slave=testsys.iobus.port[32]
+master=testsys.membus.slave[3]
+slave=testsys.iobus.master[29]
 
 [testsys.iobus]
 type=Bus
@@ -876,7 +880,8 @@ header_cycles=1
 use_default_range=true
 width=64
 default=testsys.tsunami.pciconfig.pio
-port=testsys.bridge.master testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ide.config testsys.tsunami.ide.dma testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.tsunami.ethernet.dma testsys.iobridge.slave
+master=testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ide.config testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.iobridge.slave
+slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma
 
 [testsys.membus]
 type=Bus
@@ -888,7 +893,8 @@ header_cycles=1
 use_default_range=false
 width=64
 default=testsys.membus.badaddr_responder.pio
-port=testsys.bridge.slave testsys.physmem.port[0] testsys.system_port testsys.cpu.icache_port testsys.cpu.dcache_port testsys.iobridge.master
+master=testsys.bridge.slave testsys.physmem.port[0]
+slave=testsys.system_port testsys.cpu.icache_port testsys.cpu.dcache_port testsys.iobridge.master
 
 [testsys.membus.badaddr_responder]
 type=IsaFake
@@ -907,14 +913,16 @@ warn_access=
 pio=testsys.membus.default
 
 [testsys.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=testsys.membus.port[1]
+port=testsys.membus.master[1]
 
 [testsys.simple_disk]
 type=SimpleDisk
@@ -949,7 +957,7 @@ pio_latency=1000
 platform=testsys.tsunami
 system=testsys
 terminal=testsys.terminal
-pio=testsys.iobus.port[25]
+pio=testsys.iobus.master[24]
 
 [testsys.tsunami.cchip]
 type=TsunamiCChip
@@ -957,7 +965,7 @@ pio_addr=8803072344064
 pio_latency=1000
 system=testsys
 tsunami=testsys.tsunami
-pio=testsys.iobus.port[1]
+pio=testsys.iobus.master[0]
 
 [testsys.tsunami.ethernet]
 type=NSGigE
@@ -1026,10 +1034,10 @@ system=testsys
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=testsys.iobus.port[30]
-dma=testsys.iobus.port[31]
+config=testsys.iobus.master[28]
+dma=testsys.iobus.slave[2]
 interface=etherlink.int0
-pio=testsys.iobus.port[29]
+pio=testsys.iobus.master[27]
 
 [testsys.tsunami.fake_OROM]
 type=IsaFake
@@ -1045,7 +1053,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[9]
+pio=testsys.iobus.master[8]
 
 [testsys.tsunami.fake_ata0]
 type=IsaFake
@@ -1061,7 +1069,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[20]
+pio=testsys.iobus.master[19]
 
 [testsys.tsunami.fake_ata1]
 type=IsaFake
@@ -1077,7 +1085,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[21]
+pio=testsys.iobus.master[20]
 
 [testsys.tsunami.fake_pnp_addr]
 type=IsaFake
@@ -1093,7 +1101,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[10]
+pio=testsys.iobus.master[9]
 
 [testsys.tsunami.fake_pnp_read0]
 type=IsaFake
@@ -1109,7 +1117,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[12]
+pio=testsys.iobus.master[11]
 
 [testsys.tsunami.fake_pnp_read1]
 type=IsaFake
@@ -1125,7 +1133,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[13]
+pio=testsys.iobus.master[12]
 
 [testsys.tsunami.fake_pnp_read2]
 type=IsaFake
@@ -1141,7 +1149,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[14]
+pio=testsys.iobus.master[13]
 
 [testsys.tsunami.fake_pnp_read3]
 type=IsaFake
@@ -1157,7 +1165,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[15]
+pio=testsys.iobus.master[14]
 
 [testsys.tsunami.fake_pnp_read4]
 type=IsaFake
@@ -1173,7 +1181,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[16]
+pio=testsys.iobus.master[15]
 
 [testsys.tsunami.fake_pnp_read5]
 type=IsaFake
@@ -1189,7 +1197,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[17]
+pio=testsys.iobus.master[16]
 
 [testsys.tsunami.fake_pnp_read6]
 type=IsaFake
@@ -1205,7 +1213,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[18]
+pio=testsys.iobus.master[17]
 
 [testsys.tsunami.fake_pnp_read7]
 type=IsaFake
@@ -1221,7 +1229,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[19]
+pio=testsys.iobus.master[18]
 
 [testsys.tsunami.fake_pnp_write]
 type=IsaFake
@@ -1237,7 +1245,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[11]
+pio=testsys.iobus.master[10]
 
 [testsys.tsunami.fake_ppc]
 type=IsaFake
@@ -1253,7 +1261,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[8]
+pio=testsys.iobus.master[7]
 
 [testsys.tsunami.fake_sm_chip]
 type=IsaFake
@@ -1269,7 +1277,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[3]
+pio=testsys.iobus.master[2]
 
 [testsys.tsunami.fake_uart1]
 type=IsaFake
@@ -1285,7 +1293,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[4]
+pio=testsys.iobus.master[3]
 
 [testsys.tsunami.fake_uart2]
 type=IsaFake
@@ -1301,7 +1309,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[5]
+pio=testsys.iobus.master[4]
 
 [testsys.tsunami.fake_uart3]
 type=IsaFake
@@ -1317,7 +1325,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[6]
+pio=testsys.iobus.master[5]
 
 [testsys.tsunami.fake_uart4]
 type=IsaFake
@@ -1333,7 +1341,7 @@ ret_data8=255
 system=testsys
 update_data=false
 warn_access=
-pio=testsys.iobus.port[7]
+pio=testsys.iobus.master[6]
 
 [testsys.tsunami.fb]
 type=BadDevice
@@ -1341,7 +1349,7 @@ devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=1000
 system=testsys
-pio=testsys.iobus.port[22]
+pio=testsys.iobus.master[21]
 
 [testsys.tsunami.ide]
 type=IdeController
@@ -1395,9 +1403,9 @@ pci_func=0
 pio_latency=1000
 platform=testsys.tsunami
 system=testsys
-config=testsys.iobus.port[27]
-dma=testsys.iobus.port[28]
-pio=testsys.iobus.port[26]
+config=testsys.iobus.master[26]
+dma=testsys.iobus.slave[1]
+pio=testsys.iobus.master[25]
 
 [testsys.tsunami.io]
 type=TsunamiIO
@@ -1408,7 +1416,7 @@ system=testsys
 time=Thu Jan  1 00:00:00 2009
 tsunami=testsys.tsunami
 year_is_bcd=false
-pio=testsys.iobus.port[23]
+pio=testsys.iobus.master[22]
 
 [testsys.tsunami.pchip]
 type=TsunamiPChip
@@ -1416,7 +1424,7 @@ pio_addr=8802535473152
 pio_latency=1000
 system=testsys
 tsunami=testsys.tsunami
-pio=testsys.iobus.port[2]
+pio=testsys.iobus.master[1]
 
 [testsys.tsunami.pciconfig]
 type=PciConfigAll
@@ -1434,5 +1442,5 @@ pio_latency=1000
 platform=testsys.tsunami
 system=testsys
 terminal=testsys.terminal
-pio=testsys.iobus.port[24]
+pio=testsys.iobus.master[23]
 
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
index ca565fefc..03a60d922 100755
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
@@ -1,12 +1,14 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:10:02
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:38:53
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 4300236804024 because checkpoint
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
index 4f6f5ddfe..7cbeb04be 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.200001                       # Nu
 sim_ticks                                200000789468                       # Number of ticks simulated
 final_tick                               4300236018046                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                              238054601                       # Simulator instruction rate (inst/s)
-host_op_rate                                238047910                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                           174152914765                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 476544                       # Number of bytes of host memory used
-host_seconds                                     1.15                       # Real time elapsed on the host
+host_inst_rate                              158529438                       # Simulator instruction rate (inst/s)
+host_op_rate                                158527026                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                           115976612682                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 480288                       # Number of bytes of host memory used
+host_seconds                                     1.72                       # Real time elapsed on the host
 sim_insts                                   273374833                       # Number of instructions simulated
 sim_ops                                     273374833                       # Number of ops (including micro ops) simulated
 testsys.physmem.bytes_read                   19104208                       # Number of bytes read from this memory
@@ -395,10 +395,10 @@ sim_seconds                                  0.000001                       # Nu
 sim_ticks                                      785978                       # Number of ticks simulated
 final_tick                               4300236804024                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                           826237832724                       # Simulator instruction rate (inst/s)
-host_op_rate                             785322914063                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2155916043                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 476544                       # Number of bytes of host memory used
+host_inst_rate                           518678770918                       # Simulator instruction rate (inst/s)
+host_op_rate                             495238879650                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1368243673                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 480288                       # Number of bytes of host memory used
 host_seconds                                     0.00                       # Real time elapsed on the host
 sim_insts                                   273374833                       # Number of instructions simulated
 sim_ops                                     273374833                       # Number of ops (including micro ops) simulated
@@ -483,10 +483,10 @@ testsys.cpu.kern.mode_switch::idle                  0                       # nu
 testsys.cpu.kern.mode_good::kernel                  0                      
 testsys.cpu.kern.mode_good::user                    0                      
 testsys.cpu.kern.mode_good::idle                    0                      
-testsys.cpu.kern.mode_switch_good::kernel     no_value                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::user      no_value                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
 testsys.cpu.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
 testsys.cpu.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
 testsys.cpu.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
@@ -496,30 +496,30 @@ testsys.tsunami.ethernet.descDMAWrites              0                       # Nu
 testsys.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 testsys.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
 testsys.tsunami.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedSwi        no_value                       # average number of Swi's coalesced into each post
+testsys.tsunami.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
 testsys.tsunami.ethernet.totalSwi                   0                       # total number of Swi written to ISR
 testsys.tsunami.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxIdle     no_value                       # average number of RxIdle's coalesced into each post
+testsys.tsunami.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
 testsys.tsunami.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
 testsys.tsunami.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxOk       no_value                       # average number of RxOk's coalesced into each post
+testsys.tsunami.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
 testsys.tsunami.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
 testsys.tsunami.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxDesc     no_value                       # average number of RxDesc's coalesced into each post
+testsys.tsunami.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
 testsys.tsunami.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
 testsys.tsunami.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxOk       no_value                       # average number of TxOk's coalesced into each post
+testsys.tsunami.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
 testsys.tsunami.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
 testsys.tsunami.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxIdle     no_value                       # average number of TxIdle's coalesced into each post
+testsys.tsunami.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
 testsys.tsunami.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
 testsys.tsunami.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxDesc     no_value                       # average number of TxDesc's coalesced into each post
+testsys.tsunami.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
 testsys.tsunami.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
 testsys.tsunami.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-testsys.tsunami.ethernet.coalescedRxOrn      no_value                       # average number of RxOrn's coalesced into each post
+testsys.tsunami.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
 testsys.tsunami.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-testsys.tsunami.ethernet.coalescedTotal      no_value                       # average number of interrupts coalesced into each post
+testsys.tsunami.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 testsys.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 testsys.tsunami.ethernet.droppedPackets             0                       # number of packets dropped
 drivesys.physmem.bytes_read                         0                       # Number of bytes read from this memory
@@ -603,10 +603,10 @@ drivesys.cpu.kern.mode_switch::idle                 0                       # nu
 drivesys.cpu.kern.mode_good::kernel                 0                      
 drivesys.cpu.kern.mode_good::user                   0                      
 drivesys.cpu.kern.mode_good::idle                   0                      
-drivesys.cpu.kern.mode_switch_good::kernel     no_value                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::user     no_value                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::idle     no_value                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::user          nan                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::idle          nan                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
 drivesys.cpu.kern.mode_ticks::kernel                0                       # number of ticks spent at the given mode
 drivesys.cpu.kern.mode_ticks::user                  0                       # number of ticks spent at the given mode
 drivesys.cpu.kern.mode_ticks::idle                  0                       # number of ticks spent at the given mode
@@ -616,30 +616,30 @@ drivesys.tsunami.ethernet.descDMAWrites             0                       # Nu
 drivesys.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 drivesys.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
 drivesys.tsunami.ethernet.postedSwi                 0                       # number of software interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedSwi       no_value                       # average number of Swi's coalesced into each post
+drivesys.tsunami.ethernet.coalescedSwi            nan                       # average number of Swi's coalesced into each post
 drivesys.tsunami.ethernet.totalSwi                  0                       # total number of Swi written to ISR
 drivesys.tsunami.ethernet.postedRxIdle              0                       # number of rxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxIdle     no_value                       # average number of RxIdle's coalesced into each post
+drivesys.tsunami.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
 drivesys.tsunami.ethernet.totalRxIdle               0                       # total number of RxIdle written to ISR
 drivesys.tsunami.ethernet.postedRxOk                0                       # number of RxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxOk      no_value                       # average number of RxOk's coalesced into each post
+drivesys.tsunami.ethernet.coalescedRxOk           nan                       # average number of RxOk's coalesced into each post
 drivesys.tsunami.ethernet.totalRxOk                 0                       # total number of RxOk written to ISR
 drivesys.tsunami.ethernet.postedRxDesc              0                       # number of RxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxDesc     no_value                       # average number of RxDesc's coalesced into each post
+drivesys.tsunami.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
 drivesys.tsunami.ethernet.totalRxDesc               0                       # total number of RxDesc written to ISR
 drivesys.tsunami.ethernet.postedTxOk                0                       # number of TxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxOk      no_value                       # average number of TxOk's coalesced into each post
+drivesys.tsunami.ethernet.coalescedTxOk           nan                       # average number of TxOk's coalesced into each post
 drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
 drivesys.tsunami.ethernet.postedTxIdle              0                       # number of TxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxIdle     no_value                       # average number of TxIdle's coalesced into each post
+drivesys.tsunami.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
 drivesys.tsunami.ethernet.totalTxIdle               0                       # total number of TxIdle written to ISR
 drivesys.tsunami.ethernet.postedTxDesc              0                       # number of TxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxDesc     no_value                       # average number of TxDesc's coalesced into each post
+drivesys.tsunami.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
 drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
 drivesys.tsunami.ethernet.postedRxOrn               0                       # number of RxOrn posted to CPU
-drivesys.tsunami.ethernet.coalescedRxOrn     no_value                       # average number of RxOrn's coalesced into each post
+drivesys.tsunami.ethernet.coalescedRxOrn          nan                       # average number of RxOrn's coalesced into each post
 drivesys.tsunami.ethernet.totalRxOrn                0                       # total number of RxOrn written to ISR
-drivesys.tsunami.ethernet.coalescedTotal     no_value                       # average number of interrupts coalesced into each post
+drivesys.tsunami.ethernet.coalescedTotal          nan                       # average number of interrupts coalesced into each post
 drivesys.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 drivesys.tsunami.ethernet.droppedPackets            0                       # number of packets dropped
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
index afc8aa811..1a7fdb0b3 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -41,7 +40,6 @@ choiceCtrBits=2
 choicePredictorSize=8192
 clock=500
 cpu_id=0
-dataMemPort=dcache_port
 defer_registration=false
 div16Latency=1
 div16RepeatRate=1
@@ -56,7 +54,6 @@ do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
-fetchMemPort=icache_port
 functionTrace=false
 functionTraceStart=0
 function_trace=false
@@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -115,7 +112,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -123,7 +120,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -144,7 +141,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -155,7 +152,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -175,8 +172,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -186,7 +183,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -218,15 +216,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
index 89a25c4c1..69eabeb32 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 17:33:02
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:08
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index fdd02b36e..c4f4b062b 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000021                       # Nu
 sim_ticks                                    21234500                       # Number of ticks simulated
 final_tick                                   21234500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  95244                       # Simulator instruction rate (inst/s)
-host_op_rate                                    95219                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              315647941                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 209384                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  37422                       # Simulator instruction rate (inst/s)
+host_op_rate                                    37415                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              124041463                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214024                       # Number of bytes of host memory used
+host_seconds                                     0.17                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       30016                       # Number of bytes read from this memory
@@ -56,30 +56,6 @@ system.cpu.workload.num_syscalls                   17                       # Nu
 system.cpu.numCycles                            42470                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                         11434                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
-system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             443                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           35079                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                             7391                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         17.402873                       # Percentage of cycles cpu is active
-system.cpu.comLoads                              1185                       # Number of Load instructions committed
-system.cpu.comStores                              865                       # Number of Store instructions committed
-system.cpu.comBranches                           1051                       # Number of Branches instructions committed
-system.cpu.comNops                                 17                       # Number of Nop instructions committed
-system.cpu.comNonSpec                              17                       # Number of Non-Speculative instructions committed
-system.cpu.comInts                               3265                       # Number of Integer instructions committed
-system.cpu.comFloats                                2                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                        6404                       # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps                          6404                       # Number of Ops committed (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total                  6404                       # Number of Instructions committed (Total)
-system.cpu.cpi                               6.631793                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         6.631793                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.150789                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.150789                       # IPC: Total IPC of All Threads
 system.cpu.branch_predictor.lookups              1608                       # Number of BP lookups
 system.cpu.branch_predictor.condPredicted         1127                       # Number of conditional branches predicted
 system.cpu.branch_predictor.condIncorrect          712                       # Number of conditional branches incorrect
@@ -106,6 +82,30 @@ system.cpu.execution_unit.mispredictPct     61.882129                       # Pe
 system.cpu.execution_unit.executions             4474                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies                 1                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.contextSwitches                          1                       # Number of context switches
+system.cpu.threadCycles                         11434                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled                             443                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           35079                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                             7391                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         17.402873                       # Percentage of cycles cpu is active
+system.cpu.comLoads                              1185                       # Number of Load instructions committed
+system.cpu.comStores                              865                       # Number of Store instructions committed
+system.cpu.comBranches                           1051                       # Number of Branches instructions committed
+system.cpu.comNops                                 17                       # Number of Nop instructions committed
+system.cpu.comNonSpec                              17                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                               3265                       # Number of Integer instructions committed
+system.cpu.comFloats                                2                       # Number of Floating Point instructions committed
+system.cpu.committedInsts                        6404                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                          6404                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total                  6404                       # Number of Instructions committed (Total)
+system.cpu.cpi                               6.631793                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
+system.cpu.cpi_total                         6.631793                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.150789                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
+system.cpu.ipc_total                         0.150789                       # IPC: Total IPC of All Threads
 system.cpu.stage0.idleCycles                    37550                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                      4920                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage0.utilization               11.584648                       # Percentage of cycles stage was utilized (processing insts).
@@ -164,8 +164,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst           48                       # number of ReadReq MSHR hits
@@ -246,7 +246,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets      1656000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              36                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets        46000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -351,8 +351,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          301                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
index 79efc9749..f1e336f90 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -419,7 +418,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -440,7 +439,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -451,7 +450,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -471,8 +470,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -482,7 +481,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -514,15 +514,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
index 16153e12a..a5a801059 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 17:33:02
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:41:05
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index bfc4cc915..ff51eef95 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000012                       # Nu
 sim_ticks                                    12450500                       # Number of ticks simulated
 final_tick                                   12450500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  87465                       # Simulator instruction rate (inst/s)
-host_op_rate                                    87444                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              170447462                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 210080                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  42940                       # Simulator instruction rate (inst/s)
+host_op_rate                                    42933                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               83690683                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215012                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
 sim_insts                                        6386                       # Number of instructions simulated
 sim_ops                                          6386                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       31360                       # Number of bytes read from this memory
@@ -365,8 +365,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          143                       # number of ReadReq MSHR hits
@@ -447,8 +447,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           40                       # number of ReadReq MSHR hits
@@ -552,8 +552,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          314                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
index f91bbd9dc..73aad5a2d 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
index 2f9b31423..fcc8cf92e 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:09:12
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-atomic
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:36:56
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index 97b8faa6b..d2827f261 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     3215000                       # Number of ticks simulated
 final_tick                                    3215000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  35037                       # Simulator instruction rate (inst/s)
-host_op_rate                                    35032                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               17585099                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 199940                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
+host_inst_rate                                 399216                       # Simulator instruction rate (inst/s)
+host_op_rate                                   398861                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              200076048                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 204908                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
index dd4aa648f..3be58b836 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -54,8 +53,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.slave[1]
+icache_port=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -79,7 +78,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -178,13 +177,14 @@ dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+slave=system.cpu.icache_port system.cpu.dcache_port
 
 [system.l2_cntrl0]
 type=L2Cache_Controller
@@ -211,14 +211,15 @@ size=512
 start_index_bit=6
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
@@ -331,11 +332,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[1]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index d2cdb9ada..ad599d493 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,26 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/12/2012 15:33:22
+Real time: May/08/2012 15:36:34
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 1.01
-Virtual_time_in_minutes: 0.0168333
-Virtual_time_in_hours:   0.000280556
-Virtual_time_in_days:    1.16898e-05
+Virtual_time_in_seconds: 0.34
+Virtual_time_in_minutes: 0.00566667
+Virtual_time_in_hours:   9.44444e-05
+Virtual_time_in_days:    3.93519e-06
 
 Ruby_current_time: 279353
 Ruby_start_time: 0
 Ruby_cycles: 279353
 
-mbytes_resident: 0
-mbytes_total: 0
+mbytes_resident: 48.7227
+mbytes_total: 220.605
+resident_ratio: 0.220859
 
 ruby_cycles_executed: [ 279354 ]
 
@@ -118,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 13214
-page_faults: 148
+page_reclaims: 12930
+page_faults: 0
 swaps: 0
-block_inputs: 2
-block_outputs: 4
+block_inputs: 8
+block_outputs: 88
 
 Network Stats
 -------------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
index a25a5c879..5a83168a9 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 15:33:08
-gem5 started Feb 12 2012 15:33:21
-gem5 executing on Alis-MacBook-Pro.local
+gem5 compiled May  8 2012 15:08:30
+gem5 started May  8 2012 15:36:34
+gem5 executing on piton
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
index de3976298..f4fb755b0 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000279                       # Nu
 sim_ticks                                      279353                       # Number of ticks simulated
 final_tick                                     279353                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  12170                       # Simulator instruction rate (inst/s)
-host_op_rate                                    12169                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 530781                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 270088                       # Number of bytes of host memory used
-host_seconds                                     0.53                       # Real time elapsed on the host
+host_inst_rate                                  40898                       # Simulator instruction rate (inst/s)
+host_op_rate                                    40895                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1783759                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 225904                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 38b836011..f0fb5fcd1 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -54,8 +53,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.slave[1]
+icache_port=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -175,13 +174,14 @@ dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+slave=system.cpu.icache_port system.cpu.dcache_port
 
 [system.l2_cntrl0]
 type=L2Cache_Controller
@@ -207,14 +207,15 @@ size=512
 start_index_bit=6
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
@@ -327,11 +328,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[1]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 03b0eda65..122dbb303 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/23/2012 04:22:13
+Real time: May/08/2012 15:36:38
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.39
-Virtual_time_in_minutes: 0.0065
-Virtual_time_in_hours:   0.000108333
-Virtual_time_in_days:    4.51389e-06
+Virtual_time_in_seconds: 0.36
+Virtual_time_in_minutes: 0.006
+Virtual_time_in_hours:   0.0001
+Virtual_time_in_days:    4.16667e-06
 
 Ruby_current_time: 223694
 Ruby_start_time: 0
 Ruby_cycles: 223694
 
-mbytes_resident: 45.5586
-mbytes_total: 214.484
-resident_ratio: 0.21241
+mbytes_resident: 48.6758
+mbytes_total: 220.844
+resident_ratio: 0.220408
 
 ruby_cycles_executed: [ 223695 ]
 
@@ -119,10 +119,10 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11886
-page_faults: 121
+page_reclaims: 12940
+page_faults: 0
 swaps: 0
-block_inputs: 21600
+block_inputs: 8
 block_outputs: 88
 
 Network Stats
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
index aa46612d8..4a55f22f7 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:06:37
-gem5 started Feb 11 2012 13:53:23
-gem5 executing on zizzer
-command line: build/ALPHA_MOESI_CMP_directory/gem5.fast -d build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
+gem5 compiled May  8 2012 15:14:18
+gem5 started May  8 2012 15:36:38
+gem5 executing on piton
+command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 02467cae9..b6ec472df 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000224                       # Nu
 sim_ticks                                      223694                       # Number of ticks simulated
 final_tick                                     223694                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  37589                       # Simulator instruction rate (inst/s)
-host_op_rate                                    37585                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1312743                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221408                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
+host_inst_rate                                  36304                       # Simulator instruction rate (inst/s)
+host_op_rate                                    36301                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1267928                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226148                       # Number of bytes of host memory used
+host_seconds                                     0.18                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index 0617e8d38..260fc7a89 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -54,8 +53,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.slave[1]
+icache_port=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -184,13 +183,14 @@ dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+slave=system.cpu.icache_port system.cpu.dcache_port
 
 [system.l2_cntrl0]
 type=L2Cache_Controller
@@ -218,14 +218,15 @@ size=512
 start_index_bit=6
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
@@ -338,11 +339,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[1]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index 216172e7b..75506a0a9 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/23/2012 04:22:26
+Real time: May/08/2012 15:36:41
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.31
-Virtual_time_in_minutes: 0.00516667
-Virtual_time_in_hours:   8.61111e-05
-Virtual_time_in_days:    3.58796e-06
+Virtual_time_in_seconds: 0.3
+Virtual_time_in_minutes: 0.005
+Virtual_time_in_hours:   8.33333e-05
+Virtual_time_in_days:    3.47222e-06
 
 Ruby_current_time: 231701
 Ruby_start_time: 0
 Ruby_cycles: 231701
 
-mbytes_resident: 44.0234
-mbytes_total: 212.691
-resident_ratio: 0.206983
+mbytes_resident: 46.9062
+mbytes_total: 219.027
+resident_ratio: 0.214157
 
 ruby_cycles_executed: [ 231702 ]
 
@@ -127,11 +127,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11434
-page_faults: 122
+page_reclaims: 12491
+page_faults: 0
 swaps: 0
-block_inputs: 21928
-block_outputs: 104
+block_inputs: 16
+block_outputs: 88
 
 Network Stats
 -------------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
index 0b4972a17..b67f551de 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:07:02
-gem5 started Feb 11 2012 13:54:08
-gem5 executing on zizzer
-command line: build/ALPHA_MOESI_CMP_token/gem5.fast -d build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
+gem5 compiled May  8 2012 15:11:25
+gem5 started May  8 2012 15:36:41
+gem5 executing on piton
+command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index e1d06acb6..4bd1591ab 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000232                       # Nu
 sim_ticks                                      231701                       # Number of ticks simulated
 final_tick                                     231701                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  59077                       # Simulator instruction rate (inst/s)
-host_op_rate                                    59067                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                2136733                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219660                       # Number of bytes of host memory used
+host_inst_rate                                  57269                       # Simulator instruction rate (inst/s)
+host_op_rate                                    57262                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                2071522                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224288                       # Number of bytes of host memory used
 host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 15b38dd1a..c7cccc96e 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -54,8 +53,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.slave[1]
+icache_port=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -199,23 +198,25 @@ dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+slave=system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
@@ -306,11 +307,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[1]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
index 15beb0d93..24c3821ed 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/23/2012 04:21:44
+Real time: May/08/2012 15:36:31
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.3
-Virtual_time_in_minutes: 0.005
-Virtual_time_in_hours:   8.33333e-05
-Virtual_time_in_days:    3.47222e-06
+Virtual_time_in_seconds: 0.31
+Virtual_time_in_minutes: 0.00516667
+Virtual_time_in_hours:   8.61111e-05
+Virtual_time_in_days:    3.58796e-06
 
 Ruby_current_time: 208400
 Ruby_start_time: 0
 Ruby_cycles: 208400
 
-mbytes_resident: 43.3594
-mbytes_total: 212.09
-resident_ratio: 0.204439
+mbytes_resident: 46.2461
+mbytes_total: 218.586
+resident_ratio: 0.211569
 
 ruby_cycles_executed: [ 208401 ]
 
@@ -126,11 +126,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11268
-page_faults: 126
+page_reclaims: 12336
+page_faults: 10
 swaps: 0
-block_inputs: 22864
-block_outputs: 104
+block_inputs: 1632
+block_outputs: 88
 
 Network Stats
 -------------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
index 9412b907c..7aaac31e8 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:44
-gem5 started Feb 11 2012 13:52:39
-gem5 executing on zizzer
-command line: build/ALPHA_MOESI_hammer/gem5.fast -d build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
+gem5 compiled May  8 2012 15:12:50
+gem5 started May  8 2012 15:36:31
+gem5 executing on piton
+command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 87ed3fb4b..30017b1e1 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000208                       # Nu
 sim_ticks                                      208400                       # Number of ticks simulated
 final_tick                                     208400                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  64619                       # Simulator instruction rate (inst/s)
-host_op_rate                                    64607                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                2102096                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218760                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  60692                       # Simulator instruction rate (inst/s)
+host_op_rate                                    60683                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1974491                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223836                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 3d3a73e3a..3fab4efa4 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -54,8 +53,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.slave[1]
+icache_port=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -165,23 +164,25 @@ dcache=system.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.cacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+slave=system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
@@ -272,11 +273,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[1]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
index c9b06e2ad..e165866f9 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/23/2012 04:58:59
+Real time: May/08/2012 15:37:08
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.3
-Virtual_time_in_minutes: 0.005
-Virtual_time_in_hours:   8.33333e-05
-Virtual_time_in_days:    3.47222e-06
+Virtual_time_in_seconds: 0.5
+Virtual_time_in_minutes: 0.00833333
+Virtual_time_in_hours:   0.000138889
+Virtual_time_in_days:    5.78704e-06
 
 Ruby_current_time: 342698
 Ruby_start_time: 0
 Ruby_cycles: 342698
 
-mbytes_resident: 44.5703
-mbytes_total: 213.352
-resident_ratio: 0.208905
+mbytes_resident: 47.6289
+mbytes_total: 219.488
+resident_ratio: 0.217
 
 ruby_cycles_executed: [ 342699 ]
 
@@ -122,10 +122,10 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11770
-page_faults: 1
+page_reclaims: 12667
+page_faults: 0
 swaps: 0
-block_inputs: 8
+block_inputs: 0
 block_outputs: 88
 
 Network Stats
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
index 05fd4efdd..5e2ce6170 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:09:12
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:08
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index 168276764..333553551 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000343                       # Nu
 sim_ticks                                      342698                       # Number of ticks simulated
 final_tick                                     342698                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  61504                       # Simulator instruction rate (inst/s)
-host_op_rate                                    61493                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                3290073                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220236                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  30902                       # Simulator instruction rate (inst/s)
+host_op_rate                                    30898                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1653235                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224760                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
index 3b46c790f..2cc7bb879 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -120,7 +119,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
index 5e2927c57..87ec501fc 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:09:12
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:42:48
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
index 6278fa873..cd14cede6 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000033                       # Nu
 sim_ticks                                    33007000                       # Number of ticks simulated
 final_tick                                   33007000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  37663                       # Simulator instruction rate (inst/s)
-host_op_rate                                    37658                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              194071847                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 209060                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
+host_inst_rate                                 236370                       # Simulator instruction rate (inst/s)
+host_op_rate                                   236114                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1215776788                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213800                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       28544                       # Number of bytes read from this memory
@@ -118,8 +118,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          279                       # number of ReadReq MSHR misses
@@ -194,8 +194,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           95                       # number of ReadReq MSHR misses
@@ -291,8 +291,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          278                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index d74613835..e812354d2 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -419,7 +418,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -440,7 +439,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -451,7 +450,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -471,8 +470,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -482,7 +481,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -514,15 +514,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
index eb202613d..992260cf4 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 17:33:03
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:41:16
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 686010297..28a756060 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000007                       # Nu
 sim_ticks                                     7015000                       # Number of ticks simulated
 final_tick                                    7015000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  73930                       # Simulator instruction rate (inst/s)
-host_op_rate                                    73884                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              217009042                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 209140                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                  31687                       # Simulator instruction rate (inst/s)
+host_op_rate                                    31676                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               93063477                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214220                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       17600                       # Number of bytes read from this memory
@@ -364,8 +364,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst           61                       # number of ReadReq MSHR hits
@@ -446,8 +446,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           45                       # number of ReadReq MSHR hits
@@ -545,8 +545,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          189                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index d4970301b..4f5452325 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
index 8e9c64562..d7b73cec1 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:09:24
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-atomic
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:01
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index d3468c0e9..2f22610c9 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000001                       # Nu
 sim_ticks                                     1297500                       # Number of ticks simulated
 final_tick                                    1297500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  24554                       # Simulator instruction rate (inst/s)
-host_op_rate                                    24550                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               12358328                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 199092                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                 381497                       # Simulator instruction rate (inst/s)
+host_op_rate                                   379897                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              190598632                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 204064                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
index 2a33a674c..317cc6a7e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -54,8 +53,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.slave[1]
+icache_port=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -79,7 +78,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -178,13 +177,14 @@ dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+slave=system.cpu.icache_port system.cpu.dcache_port
 
 [system.l2_cntrl0]
 type=L2Cache_Controller
@@ -211,14 +211,15 @@ size=512
 start_index_bit=6
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
@@ -331,11 +332,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[1]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 9c8b2434f..bda71aafd 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/12/2012 15:33:21
+Real time: May/08/2012 15:36:34
 
 Profiler Stats
 --------------
@@ -43,17 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.71
-Virtual_time_in_minutes: 0.0118333
-Virtual_time_in_hours:   0.000197222
-Virtual_time_in_days:    8.21759e-06
+Virtual_time_in_seconds: 0.24
+Virtual_time_in_minutes: 0.004
+Virtual_time_in_hours:   6.66667e-05
+Virtual_time_in_days:    2.77778e-06
 
 Ruby_current_time: 104867
 Ruby_start_time: 0
 Ruby_cycles: 104867
 
-mbytes_resident: 0
-mbytes_total: 0
+mbytes_resident: 45.8906
+mbytes_total: 218.43
+resident_ratio: 0.210093
 
 ruby_cycles_executed: [ 104868 ]
 
@@ -118,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 12663
-page_faults: 71
+page_reclaims: 12254
+page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 88
 
 Network Stats
 -------------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
index 22e5bbd3f..59ad2cc4d 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 15:33:08
-gem5 started Feb 12 2012 15:33:21
-gem5 executing on Alis-MacBook-Pro.local
+gem5 compiled May  8 2012 15:08:30
+gem5 started May  8 2012 15:36:34
+gem5 executing on piton
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
index bb0141a2a..bd57039cb 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000105                       # Nu
 sim_ticks                                      104867                       # Number of ticks simulated
 final_tick                                     104867                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  10837                       # Simulator instruction rate (inst/s)
-host_op_rate                                    10836                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 440871                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 267756                       # Number of bytes of host memory used
-host_seconds                                     0.24                       # Real time elapsed on the host
+host_inst_rate                                  38145                       # Simulator instruction rate (inst/s)
+host_op_rate                                    38137                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1551633                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223676                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 1d5a893ff..34c479e22 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -54,8 +53,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.slave[1]
+icache_port=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -175,13 +174,14 @@ dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+slave=system.cpu.icache_port system.cpu.dcache_port
 
 [system.l2_cntrl0]
 type=L2Cache_Controller
@@ -207,14 +207,15 @@ size=512
 start_index_bit=6
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
@@ -327,11 +328,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[1]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index f2273438f..232722c59 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/23/2012 04:22:12
+Real time: May/08/2012 15:36:38
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.25
-Virtual_time_in_minutes: 0.00416667
-Virtual_time_in_hours:   6.94444e-05
-Virtual_time_in_days:    2.89352e-06
+Virtual_time_in_seconds: 0.26
+Virtual_time_in_minutes: 0.00433333
+Virtual_time_in_hours:   7.22222e-05
+Virtual_time_in_days:    3.00926e-06
 
 Ruby_current_time: 85418
 Ruby_start_time: 0
 Ruby_cycles: 85418
 
-mbytes_resident: 42.9688
-mbytes_total: 212.301
-resident_ratio: 0.202396
+mbytes_resident: 46.1016
+mbytes_total: 218.602
+resident_ratio: 0.210893
 
 ruby_cycles_executed: [ 85419 ]
 
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11325
-page_faults: 11
+page_reclaims: 12263
+page_faults: 0
 swaps: 0
-block_inputs: 1584
-block_outputs: 88
+block_inputs: 0
+block_outputs: 80
 
 Network Stats
 -------------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index 7ff042055..fe8db74fc 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:06:37
-gem5 started Feb 11 2012 13:53:34
-gem5 executing on zizzer
-command line: build/ALPHA_MOESI_CMP_directory/gem5.fast -d build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
+gem5 compiled May  8 2012 15:14:18
+gem5 started May  8 2012 15:36:38
+gem5 executing on piton
+command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index aeddd4cb4..5143cdcae 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000085                       # Nu
 sim_ticks                                       85418                       # Number of ticks simulated
 final_tick                                      85418                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  37008                       # Simulator instruction rate (inst/s)
-host_op_rate                                    36998                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1226055                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219168                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  33831                       # Simulator instruction rate (inst/s)
+host_op_rate                                    33824                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1120953                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223852                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index d5f1dd8ea..ea15696c3 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -54,8 +53,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.slave[1]
+icache_port=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -184,13 +183,14 @@ dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+slave=system.cpu.icache_port system.cpu.dcache_port
 
 [system.l2_cntrl0]
 type=L2Cache_Controller
@@ -218,14 +218,15 @@ size=512
 start_index_bit=6
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
@@ -338,11 +339,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[1]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index 2d266c770..a538bb5ac 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/23/2012 04:22:26
+Real time: May/08/2012 15:36:42
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.22
-Virtual_time_in_minutes: 0.00366667
-Virtual_time_in_hours:   6.11111e-05
-Virtual_time_in_days:    2.5463e-06
+Virtual_time_in_seconds: 0.23
+Virtual_time_in_minutes: 0.00383333
+Virtual_time_in_hours:   6.38889e-05
+Virtual_time_in_days:    2.66204e-06
 
 Ruby_current_time: 87899
 Ruby_start_time: 0
 Ruby_cycles: 87899
 
-mbytes_resident: 42.2227
-mbytes_total: 211.34
-resident_ratio: 0.199786
+mbytes_resident: 45.1094
+mbytes_total: 217.598
+resident_ratio: 0.207306
 
 ruby_cycles_executed: [ 87900 ]
 
@@ -127,11 +127,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11088
-page_faults: 5
+page_reclaims: 12024
+page_faults: 0
 swaps: 0
-block_inputs: 1064
-block_outputs: 104
+block_inputs: 0
+block_outputs: 88
 
 Network Stats
 -------------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index f1a5aa8ce..f849b0d8f 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:07:02
-gem5 started Feb 11 2012 13:54:19
-gem5 executing on zizzer
-command line: build/ALPHA_MOESI_CMP_token/gem5.fast -d build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
+gem5 compiled May  8 2012 15:11:25
+gem5 started May  8 2012 15:36:41
+gem5 executing on piton
+command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index bd362a91b..253fc28f1 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000088                       # Nu
 sim_ticks                                       87899                       # Number of ticks simulated
 final_tick                                      87899                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  58227                       # Simulator instruction rate (inst/s)
-host_op_rate                                    58203                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1984496                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218264                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                  46491                       # Simulator instruction rate (inst/s)
+host_op_rate                                    46479                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1584970                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222824                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index 82df55c27..5531e80ff 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -54,8 +53,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.slave[1]
+icache_port=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -199,23 +198,25 @@ dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+slave=system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
@@ -306,11 +307,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[1]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
index 452952d26..6835e2100 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/23/2012 04:21:49
+Real time: May/08/2012 15:36:31
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.23
-Virtual_time_in_minutes: 0.00383333
-Virtual_time_in_hours:   6.38889e-05
-Virtual_time_in_days:    2.66204e-06
+Virtual_time_in_seconds: 0.24
+Virtual_time_in_minutes: 0.004
+Virtual_time_in_hours:   6.66667e-05
+Virtual_time_in_days:    2.77778e-06
 
 Ruby_current_time: 78448
 Ruby_start_time: 0
 Ruby_cycles: 78448
 
-mbytes_resident: 41.5938
-mbytes_total: 210.898
-resident_ratio: 0.197222
+mbytes_resident: 44.707
+mbytes_total: 217.324
+resident_ratio: 0.205716
 
 ruby_cycles_executed: [ 78449 ]
 
@@ -126,10 +126,10 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10974
-page_faults: 0
+page_reclaims: 11920
+page_faults: 3
 swaps: 0
-block_inputs: 0
+block_inputs: 824
 block_outputs: 88
 
 Network Stats
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
index f44aeab20..7b52a0c21 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:44
-gem5 started Feb 11 2012 13:52:40
-gem5 executing on zizzer
-command line: build/ALPHA_MOESI_hammer/gem5.fast -d build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
+gem5 compiled May  8 2012 15:12:50
+gem5 started May  8 2012 15:36:31
+gem5 executing on piton
+command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index a79092ea7..f21155c2f 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000078                       # Nu
 sim_ticks                                       78448                       # Number of ticks simulated
 final_tick                                      78448                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  53931                       # Simulator instruction rate (inst/s)
-host_op_rate                                    53912                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1640583                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217556                       # Number of bytes of host memory used
+host_inst_rate                                  48255                       # Simulator instruction rate (inst/s)
+host_op_rate                                    48240                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1468118                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222544                       # Number of bytes of host memory used
 host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 1b51d074e..a2207b6c0 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -54,8 +53,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.slave[1]
+icache_port=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -165,23 +164,25 @@ dcache=system.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.cacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+slave=system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
@@ -272,11 +273,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[1]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
index 2c26f3344..cc4333b9c 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/23/2012 04:59:27
+Real time: May/08/2012 15:37:51
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.24
-Virtual_time_in_minutes: 0.004
-Virtual_time_in_hours:   6.66667e-05
-Virtual_time_in_days:    2.77778e-06
+Virtual_time_in_seconds: 0.4
+Virtual_time_in_minutes: 0.00666667
+Virtual_time_in_hours:   0.000111111
+Virtual_time_in_days:    4.62963e-06
 
 Ruby_current_time: 123378
 Ruby_start_time: 0
 Ruby_cycles: 123378
 
-mbytes_resident: 42.25
-mbytes_total: 211.328
-resident_ratio: 0.199926
+mbytes_resident: 45.0547
+mbytes_total: 217.531
+resident_ratio: 0.207118
 
 ruby_cycles_executed: [ 123379 ]
 
@@ -122,7 +122,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11154
+page_reclaims: 12045
 page_faults: 0
 swaps: 0
 block_inputs: 0
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
index acdbe4afb..6ae96cee0 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:09:24
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:51
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index 22da3c1b5..6c31e7bc8 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000123                       # Nu
 sim_ticks                                      123378                       # Number of ticks simulated
 final_tick                                     123378                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  35379                       # Simulator instruction rate (inst/s)
-host_op_rate                                    35370                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1692995                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218176                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  23789                       # Simulator instruction rate (inst/s)
+host_op_rate                                    23782                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1138300                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222756                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
index bcf14766c..1cfaa4239 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -120,7 +119,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
index ec60c2fa2..194a972c4 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:09:24
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:36:56
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index 4d24e98d0..2a4818376 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000017                       # Nu
 sim_ticks                                    16769000                       # Number of ticks simulated
 final_tick                                   16769000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 142484                       # Simulator instruction rate (inst/s)
-host_op_rate                                   142326                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              925222654                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 208204                       # Number of bytes of host memory used
+host_inst_rate                                 149101                       # Simulator instruction rate (inst/s)
+host_op_rate                                   148981                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              968734693                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 212944                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
@@ -118,8 +118,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          163                       # number of ReadReq MSHR misses
@@ -194,8 +194,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
@@ -285,8 +285,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          163                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index 5d5098bd1..34353ab5e 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -573,7 +572,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -596,8 +595,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index d9b6fdd69..a7713ed58 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 16:33:35
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:20:46
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 2d5ac9cf2..7aa4a6157 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000010                       # Nu
 sim_ticks                                    10303500                       # Number of ticks simulated
 final_tick                                   10303500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  46836                       # Simulator instruction rate (inst/s)
-host_op_rate                                    58425                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              104878029                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222544                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  20985                       # Simulator instruction rate (inst/s)
+host_op_rate                                    26178                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               46991642                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229632                       # Number of bytes of host memory used
+host_seconds                                     0.22                       # Real time elapsed on the host
 sim_insts                                        4600                       # Number of instructions simulated
 sim_ops                                          5739                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       25664                       # Number of bytes read from this memory
@@ -419,8 +419,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst           70                       # number of ReadReq MSHR hits
@@ -515,8 +515,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           63                       # number of ReadReq MSHR hits
@@ -625,8 +625,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            4                       # number of ReadReq MSHR hits
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index e584370ea..816c7ba86 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -514,7 +513,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -537,8 +536,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
index 9bfa3671c..fa47f77da 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 16:33:24
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:20:46
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index c4c9274ca..82d7d38dc 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000010                       # Nu
 sim_ticks                                    10303500                       # Number of ticks simulated
 final_tick                                   10303500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  48410                       # Simulator instruction rate (inst/s)
-host_op_rate                                    60388                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              108401694                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222284                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  29431                       # Simulator instruction rate (inst/s)
+host_op_rate                                    36712                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               65901409                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229344                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
 sim_insts                                        4600                       # Number of instructions simulated
 sim_ops                                          5739                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       25664                       # Number of bytes read from this memory
@@ -374,8 +374,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst           70                       # number of ReadReq MSHR hits
@@ -470,8 +470,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           63                       # number of ReadReq MSHR hits
@@ -580,8 +580,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            4                       # number of ReadReq MSHR hits
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
index 305feda00..151e2cd8c 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -154,7 +154,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -177,8 +177,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
index 38e35b911..435d1afac 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 16:33:56
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:20:46
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
index 693c12922..1b101d03e 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2875500                       # Number of ticks simulated
 final_tick                                    2875500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  95261                       # Simulator instruction rate (inst/s)
-host_op_rate                                   118814                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59514762                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212272                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                 415244                       # Simulator instruction rate (inst/s)
+host_op_rate                                   516464                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              258032084                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219364                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4600                       # Number of instructions simulated
 sim_ops                                          5739                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       22944                       # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
index a6e23776e..da6096ffc 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -100,7 +100,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -123,8 +123,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
index af4cba8f6..73791bcc0 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 16:33:45
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:20:46
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
index ed3ee4578..da264e87e 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2875500                       # Number of ticks simulated
 final_tick                                    2875500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 126142                       # Simulator instruction rate (inst/s)
-host_op_rate                                   157316                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               78793699                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212180                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                 249779                       # Simulator instruction rate (inst/s)
+host_op_rate                                   311187                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              155712783                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219320                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        4600                       # Number of instructions simulated
 sim_ops                                          5739                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       22944                       # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
index 92e235eb9..91f39c039 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -183,7 +182,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -206,8 +205,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
index 976d6a78b..f409a27fc 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 16:34:06
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:20:46
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index 2c4a7f677..55e20828c 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000026                       # Nu
 sim_ticks                                    26361000                       # Number of ticks simulated
 final_tick                                   26361000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 140316                       # Simulator instruction rate (inst/s)
-host_op_rate                                   174230                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              807994403                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221092                       # Number of bytes of host memory used
+host_inst_rate                                 148609                       # Simulator instruction rate (inst/s)
+host_op_rate                                   184448                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              855039933                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228200                       # Number of bytes of host memory used
 host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        4574                       # Number of instructions simulated
 sim_ops                                          5682                       # Number of ops (including micro ops) simulated
@@ -128,8 +128,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          241                       # number of ReadReq MSHR misses
@@ -212,8 +212,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           98                       # number of ReadReq MSHR misses
@@ -312,8 +312,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          225                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
index 600677fb9..6db06c5ff 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -41,7 +40,6 @@ choiceCtrBits=2
 choicePredictorSize=8192
 clock=500
 cpu_id=0
-dataMemPort=dcache_port
 defer_registration=false
 div16Latency=1
 div16RepeatRate=1
@@ -56,7 +54,6 @@ do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
-fetchMemPort=icache_port
 functionTrace=false
 functionTraceStart=0
 function_trace=false
@@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -115,7 +112,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=MipsTLB
@@ -123,7 +120,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -144,7 +141,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=MipsInterrupts
@@ -155,7 +152,7 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -175,8 +172,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -186,7 +183,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -218,15 +216,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
index e34fa5006..8cbac12cb 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:16:48
-gem5 started Feb 12 2012 18:16:47
-gem5 executing on zizzer
-command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing
+gem5 compiled May  8 2012 15:07:01
+gem5 started May  8 2012 15:36:45
+gem5 executing on piton
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
index e8bd2f84c..2d3519846 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000020                       # Nu
 sim_ticks                                    19775000                       # Number of ticks simulated
 final_tick                                   19775000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 108846                       # Simulator instruction rate (inst/s)
-host_op_rate                                   108810                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              369151681                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 210376                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                  83973                       # Simulator instruction rate (inst/s)
+host_op_rate                                    83956                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              284866754                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214812                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
 sim_ops                                          5827                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       29120                       # Number of bytes read from this memory
@@ -42,30 +42,6 @@ system.cpu.workload.num_syscalls                    8                       # Nu
 system.cpu.numCycles                            39551                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                          9142                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
-system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             404                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           34183                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                             5368                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         13.572350                       # Percentage of cycles cpu is active
-system.cpu.comLoads                              1164                       # Number of Load instructions committed
-system.cpu.comStores                              925                       # Number of Store instructions committed
-system.cpu.comBranches                            916                       # Number of Branches instructions committed
-system.cpu.comNops                                657                       # Number of Nop instructions committed
-system.cpu.comNonSpec                              10                       # Number of Non-Speculative instructions committed
-system.cpu.comInts                               2155                       # Number of Integer instructions committed
-system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                        5827                       # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps                          5827                       # Number of Ops committed (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total                  5827                       # Number of Instructions committed (Total)
-system.cpu.cpi                               6.787541                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         6.787541                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.147329                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.147329                       # IPC: Total IPC of All Threads
 system.cpu.branch_predictor.lookups              1152                       # Number of BP lookups
 system.cpu.branch_predictor.condPredicted          851                       # Number of conditional branches predicted
 system.cpu.branch_predictor.condIncorrect          605                       # Number of conditional branches incorrect
@@ -92,6 +68,30 @@ system.cpu.execution_unit.mispredictPct     65.065502                       # Pe
 system.cpu.execution_unit.executions             3155                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies                 3                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    1                       # Number of Divide Operations Executed
+system.cpu.contextSwitches                          1                       # Number of context switches
+system.cpu.threadCycles                          9142                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled                             404                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           34183                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                             5368                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         13.572350                       # Percentage of cycles cpu is active
+system.cpu.comLoads                              1164                       # Number of Load instructions committed
+system.cpu.comStores                              925                       # Number of Store instructions committed
+system.cpu.comBranches                            916                       # Number of Branches instructions committed
+system.cpu.comNops                                657                       # Number of Nop instructions committed
+system.cpu.comNonSpec                              10                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                               2155                       # Number of Integer instructions committed
+system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
+system.cpu.committedInsts                        5827                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                          5827                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total                  5827                       # Number of Instructions committed (Total)
+system.cpu.cpi                               6.787541                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
+system.cpu.cpi_total                         6.787541                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.147329                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
+system.cpu.ipc_total                         0.147329                       # IPC: Total IPC of All Threads
 system.cpu.stage0.idleCycles                    35911                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                      3640                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage0.utilization                9.203307                       # Percentage of cycles stage was utilized (processing insts).
@@ -150,7 +150,7 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets        29000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets        29000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
@@ -232,7 +232,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets      1153500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              23                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -337,8 +337,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          317                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
index 00305a8e7..5535b7c1b 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=MipsTLB
@@ -419,7 +418,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -440,7 +439,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=MipsInterrupts
@@ -451,7 +450,7 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -471,8 +470,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -482,7 +481,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -514,15 +514,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
index e545392ce..6efd85bce 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:16:48
-gem5 started Feb 12 2012 18:16:57
-gem5 executing on zizzer
-command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing
+gem5 compiled May  8 2012 15:07:01
+gem5 started May  8 2012 15:36:45
+gem5 executing on piton
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index f9bef2483..0f84e872e 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000013                       # Nu
 sim_ticks                                    12671500                       # Number of ticks simulated
 final_tick                                   12671500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  93816                       # Simulator instruction rate (inst/s)
-host_op_rate                                    93786                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              229841550                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211032                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  56172                       # Simulator instruction rate (inst/s)
+host_op_rate                                    56163                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              137660070                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215596                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        5169                       # Number of instructions simulated
 sim_ops                                          5169                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       30912                       # Number of bytes read from this memory
@@ -349,8 +349,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          103                       # number of ReadReq MSHR hits
@@ -431,8 +431,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           42                       # number of ReadReq MSHR hits
@@ -536,8 +536,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          341                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
index 9563d85bf..b0d54d9f2 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=MipsTLB
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
index 7716b33a4..289fd9d0d 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:07:32
-gem5 started Feb 11 2012 13:54:41
-gem5 executing on zizzer
-command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic
+gem5 compiled May  8 2012 15:07:01
+gem5 started May  8 2012 15:36:45
+gem5 executing on piton
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 9ae16c4c6..91924afa4 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2913500                       # Number of ticks simulated
 final_tick                                    2913500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1078442                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1075012                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              535874927                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 200784                       # Number of bytes of host memory used
+host_inst_rate                                 826404                       # Simulator instruction rate (inst/s)
+host_op_rate                                   824787                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              411656542                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 205596                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
 sim_ops                                          5827                       # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index da3c93787..c2b4be60f 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -54,8 +53,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.slave[1]
+icache_port=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu.dtb]
 type=MipsTLB
@@ -165,23 +164,25 @@ dcache=system.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.cacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+slave=system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
@@ -272,11 +273,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[1]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
index ac3ff100c..4fad25b5f 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:07:32
-gem5 started Feb 11 2012 13:54:52
-gem5 executing on zizzer
-command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby
+gem5 compiled May  8 2012 15:07:01
+gem5 started May  8 2012 15:36:45
+gem5 executing on piton
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index 8087912dc..b950c6483 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000293                       # Nu
 sim_ticks                                      292960                       # Number of ticks simulated
 final_tick                                     292960                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  71598                       # Simulator instruction rate (inst/s)
-host_op_rate                                    71583                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                3598224                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221836                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  60937                       # Simulator instruction rate (inst/s)
+host_op_rate                                    60929                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                3062846                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226192                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
 sim_ops                                          5827                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       27687                       # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
index 3cd70d03a..c6b1fd816 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=MipsTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=MipsInterrupts
@@ -120,7 +119,7 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
index 29b03eaff..0276ca4b7 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:07:32
-gem5 started Feb 11 2012 13:54:50
-gem5 executing on zizzer
-command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing
+gem5 compiled May  8 2012 15:07:01
+gem5 started May  8 2012 15:36:45
+gem5 executing on piton
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index 5a0520753..6c79a4c95 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000032                       # Nu
 sim_ticks                                    32088000                       # Number of ticks simulated
 final_tick                                   32088000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 603210                       # Simulator instruction rate (inst/s)
-host_op_rate                                   602100                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3309896144                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 209992                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 273601                       # Simulator instruction rate (inst/s)
+host_op_rate                                   273420                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1504754975                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214572                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
 sim_ops                                          5827                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       28096                       # Number of bytes read from this memory
@@ -104,8 +104,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          303                       # number of ReadReq MSHR misses
@@ -180,8 +180,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
@@ -277,8 +277,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          301                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
index eed88a81d..b22bc0367 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -128,7 +127,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -149,7 +148,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=PowerTLB
@@ -420,7 +419,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -441,7 +440,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=PowerInterrupts
@@ -452,7 +451,7 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -472,8 +471,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -483,7 +482,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -515,15 +515,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
index a3c2e1876..7aac87cd9 100755
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:17:52
-gem5 started Feb 12 2012 18:17:19
-gem5 executing on zizzer
-command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing
+gem5 compiled May  8 2012 15:03:54
+gem5 started May  8 2012 15:36:49
+gem5 executing on piton
+command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index e78f47ce4..129f4d9d2 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000011                       # Nu
 sim_ticks                                    11243500                       # Number of ticks simulated
 final_tick                                   11243500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 108078                       # Simulator instruction rate (inst/s)
-host_op_rate                                   108043                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              209380098                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 207884                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                  73653                       # Simulator instruction rate (inst/s)
+host_op_rate                                    73641                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              142731766                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211540                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        5800                       # Number of instructions simulated
 sim_ops                                          5800                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       28736                       # Number of bytes read from this memory
@@ -348,8 +348,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst           82                       # number of ReadReq MSHR hits
@@ -430,8 +430,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           32                       # number of ReadReq MSHR hits
@@ -535,8 +535,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          350                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
index 252e46831..0a48b581e 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -40,6 +39,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -58,8 +58,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=PowerTLB
@@ -102,15 +102,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
index 2b3bb9fb6..4ba999389 100755
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:07:55
-gem5 started Feb 11 2012 13:55:02
-gem5 executing on zizzer
-command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/simple-atomic
+gem5 compiled May  8 2012 15:03:54
+gem5 started May  8 2012 15:36:50
+gem5 executing on piton
+command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
index 5d83b2bac..87b1b3e66 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2900000                       # Number of ticks simulated
 final_tick                                    2900000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 430782                       # Simulator instruction rate (inst/s)
-host_op_rate                                   430227                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              214814147                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 197864                       # Number of bytes of host memory used
+host_inst_rate                                 413372                       # Simulator instruction rate (inst/s)
+host_op_rate                                   412979                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              206267825                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 201744                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5801                       # Number of instructions simulated
 sim_ops                                          5801                       # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
index eed996339..61b03b911 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -41,7 +40,6 @@ choiceCtrBits=2
 choicePredictorSize=8192
 clock=500
 cpu_id=0
-dataMemPort=dcache_port
 defer_registration=false
 div16Latency=1
 div16RepeatRate=1
@@ -56,7 +54,6 @@ do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
-fetchMemPort=icache_port
 functionTrace=false
 functionTraceStart=0
 function_trace=false
@@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -115,7 +112,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -123,7 +120,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -144,7 +141,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=SparcInterrupts
@@ -155,7 +152,7 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -175,8 +172,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -186,7 +183,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -218,15 +216,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
index cf9740828..19ecb4795 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:18:12
-gem5 started Feb 12 2012 18:17:30
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:36:55
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 18196500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
index 440f0bc0a..5aea2d352 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000018                       # Nu
 sim_ticks                                    18196500                       # Number of ticks simulated
 final_tick                                   18196500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  90140                       # Simulator instruction rate (inst/s)
-host_op_rate                                    90112                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              306976844                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211148                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  72963                       # Simulator instruction rate (inst/s)
+host_op_rate                                    72948                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              248531385                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221204                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
 sim_ops                                          5340                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       27072                       # Number of bytes read from this memory
@@ -24,30 +24,6 @@ system.cpu.workload.num_syscalls                   11                       # Nu
 system.cpu.numCycles                            36394                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                          9708                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
-system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             421                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           30167                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                             6227                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         17.109963                       # Percentage of cycles cpu is active
-system.cpu.comLoads                               716                       # Number of Load instructions committed
-system.cpu.comStores                              673                       # Number of Store instructions committed
-system.cpu.comBranches                           1116                       # Number of Branches instructions committed
-system.cpu.comNops                                173                       # Number of Nop instructions committed
-system.cpu.comNonSpec                             106                       # Number of Non-Speculative instructions committed
-system.cpu.comInts                               2537                       # Number of Integer instructions committed
-system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                        5340                       # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps                          5340                       # Number of Ops committed (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total                  5340                       # Number of Instructions committed (Total)
-system.cpu.cpi                               6.815356                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         6.815356                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.146727                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.146727                       # IPC: Total IPC of All Threads
 system.cpu.branch_predictor.lookups              1617                       # Number of BP lookups
 system.cpu.branch_predictor.condPredicted         1022                       # Number of conditional branches predicted
 system.cpu.branch_predictor.condIncorrect          899                       # Number of conditional branches incorrect
@@ -74,6 +50,30 @@ system.cpu.execution_unit.mispredictPct     74.910394                       # Pe
 system.cpu.execution_unit.executions             3979                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies                 0                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.contextSwitches                          1                       # Number of context switches
+system.cpu.threadCycles                          9708                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled                             421                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           30167                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                             6227                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         17.109963                       # Percentage of cycles cpu is active
+system.cpu.comLoads                               716                       # Number of Load instructions committed
+system.cpu.comStores                              673                       # Number of Store instructions committed
+system.cpu.comBranches                           1116                       # Number of Branches instructions committed
+system.cpu.comNops                                173                       # Number of Nop instructions committed
+system.cpu.comNonSpec                             106                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                               2537                       # Number of Integer instructions committed
+system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
+system.cpu.committedInsts                        5340                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                          5340                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total                  5340                       # Number of Instructions committed (Total)
+system.cpu.cpi                               6.815356                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
+system.cpu.cpi_total                         6.815356                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.146727                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
+system.cpu.ipc_total                         0.146727                       # IPC: Total IPC of All Threads
 system.cpu.stage0.idleCycles                    31821                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                      4573                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage0.utilization               12.565258                       # Percentage of cycles stage was utilized (processing insts).
@@ -132,7 +132,7 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets       106000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets 35333.333333                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
@@ -214,7 +214,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets      2259500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              45                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -322,8 +322,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          289                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
index 328fede16..3550cbb34 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
index 51b7334cc..467d94a16 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 13:55:13
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-atomic
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:36:55
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 2701000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index 12998e98f..a0bb29684 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2701000                       # Number of ticks simulated
 final_tick                                    2701000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 963329                       # Simulator instruction rate (inst/s)
-host_op_rate                                   960313                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              484321069                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 201636                       # Number of bytes of host memory used
+host_inst_rate                                 660534                       # Simulator instruction rate (inst/s)
+host_op_rate                                   659359                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              332979355                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211860                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
 sim_ops                                          5340                       # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index bca11e4c0..7c9c9a36b 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -54,8 +53,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.slave[1]
+icache_port=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -165,23 +164,25 @@ dcache=system.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.cacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+slave=system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
@@ -272,11 +273,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[1]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
index d48e9e1d8..5940396eb 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/23/2012 04:24:20
+Real time: May/08/2012 15:36:55
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.26
-Virtual_time_in_minutes: 0.00433333
-Virtual_time_in_hours:   7.22222e-05
-Virtual_time_in_days:    3.00926e-06
+Virtual_time_in_seconds: 0.28
+Virtual_time_in_minutes: 0.00466667
+Virtual_time_in_hours:   7.77778e-05
+Virtual_time_in_days:    3.24074e-06
 
 Ruby_current_time: 253364
 Ruby_start_time: 0
 Ruby_cycles: 253364
 
-mbytes_resident: 45.418
-mbytes_total: 219.465
-resident_ratio: 0.206949
+mbytes_resident: 48.3438
+mbytes_total: 226.668
+resident_ratio: 0.21328
 
 ruby_cycles_executed: [ 253365 ]
 
@@ -122,10 +122,10 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 12012
-page_faults: 1
+page_reclaims: 12864
+page_faults: 0
 swaps: 0
-block_inputs: 152
+block_inputs: 0
 block_outputs: 88
 
 Network Stats
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
index f70d252d3..dd8a0a7b3 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 13:55:24
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing-ruby
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:36:55
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 253364 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index a13bd4161..362724c03 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000253                       # Nu
 sim_ticks                                      253364                       # Number of ticks simulated
 final_tick                                     253364                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  70723                       # Simulator instruction rate (inst/s)
-host_op_rate                                    70707                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                3354080                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222404                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  60301                       # Simulator instruction rate (inst/s)
+host_op_rate                                    60291                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                2860139                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 232112                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
 sim_ops                                          5340                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       26135                       # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index a61827466..958c9bb97 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=SparcInterrupts
@@ -120,7 +119,7 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
index 5f1c3c546..702411d18 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 13:55:23
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:36:55
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 28206000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index e8bbbf4c9..d2987c02e 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    28206000                       # Number of ticks simulated
 final_tick                                   28206000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 534426                       # Simulator instruction rate (inst/s)
-host_op_rate                                   533460                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2812998715                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 210748                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 240215                       # Simulator instruction rate (inst/s)
+host_op_rate                                   240049                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1267195715                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220748                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
 sim_ops                                          5340                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       24896                       # Number of bytes read from this memory
@@ -86,8 +86,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          257                       # number of ReadReq MSHR misses
@@ -162,8 +162,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           54                       # number of ReadReq MSHR misses
@@ -262,8 +262,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          255                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 7b5ea1d59..1666732e2 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -159,7 +158,7 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[3]
+port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.fuPool]
 type=FUPool
@@ -426,7 +425,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -447,7 +446,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -455,8 +454,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[4]
-pio=system.membus.port[3]
+int_master=system.membus.slave[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -467,11 +467,11 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[2]
+port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -491,8 +491,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[4]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -502,7 +502,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -534,15 +535,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
index eda7f85a5..9c9739cf4 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:18:12
-gem5 started Feb 12 2012 18:26:23
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:49:56
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 475f993c2..cb09e3c8e 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000012                       # Nu
 sim_ticks                                    12299500                       # Number of ticks simulated
 final_tick                                   12299500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  59298                       # Simulator instruction rate (inst/s)
-host_op_rate                                   107375                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              134612595                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218308                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  24245                       # Simulator instruction rate (inst/s)
+host_op_rate                                    43905                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               55046151                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223460                       # Number of bytes of host memory used
+host_seconds                                     0.22                       # Real time elapsed on the host
 sim_insts                                        5416                       # Number of instructions simulated
 sim_ops                                          9809                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       28864                       # Number of bytes read from this memory
@@ -329,8 +329,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst           88                       # number of ReadReq MSHR hits
@@ -411,8 +411,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           44                       # number of ReadReq MSHR hits
@@ -514,8 +514,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          302                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
index 8e464f4fc..c00e48a14 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -69,7 +69,7 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.membus.port[5]
+port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -77,8 +77,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[7]
-pio=system.membus.port[6]
+int_master=system.membus.slave[5]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -89,7 +90,7 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.membus.port[4]
+port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -121,15 +122,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
index 51c6cbf48..972a98347 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:53
-gem5 started Feb 11 2012 14:04:16
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-atomic
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:49:56
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
index d15c91451..0f9f946d6 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000006                       # Nu
 sim_ticks                                     5651000                       # Number of ticks simulated
 final_tick                                    5651000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 364793                       # Simulator instruction rate (inst/s)
-host_op_rate                                   659825                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              379660541                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 207748                       # Number of bytes of host memory used
+host_inst_rate                                 330960                       # Simulator instruction rate (inst/s)
+host_op_rate                                   598371                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              344132346                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213012                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5417                       # Number of instructions simulated
 sim_ops                                          9810                       # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index 95be41a11..e879347ff 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -54,8 +53,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.slave[1]
+icache_port=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -66,7 +65,7 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.l1_cntrl0.sequencer.port[3]
+port=system.l1_cntrl0.sequencer.slave[3]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -74,8 +73,9 @@ int_latency=1
 pio_addr=2305843009213693952
 pio_latency=1
 system=system
-int_port=system.l1_cntrl0.sequencer.port[5]
-pio=system.l1_cntrl0.sequencer.port[4]
+int_master=system.l1_cntrl0.sequencer.slave[4]
+int_slave=system.l1_cntrl0.sequencer.master[1]
+pio=system.l1_cntrl0.sequencer.master[0]
 
 [system.cpu.itb]
 type=X86TLB
@@ -86,7 +86,7 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.l1_cntrl0.sequencer.port[2]
+port=system.l1_cntrl0.sequencer.slave[2]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -185,23 +185,26 @@ dcache=system.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.cacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
@@ -292,11 +295,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[1]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
index 33342e3e3..442d60f8b 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/23/2012 04:24:44
+Real time: May/08/2012 15:50:07
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.27
-Virtual_time_in_minutes: 0.0045
-Virtual_time_in_hours:   7.5e-05
-Virtual_time_in_days:    3.125e-06
+Virtual_time_in_seconds: 0.37
+Virtual_time_in_minutes: 0.00616667
+Virtual_time_in_hours:   0.000102778
+Virtual_time_in_days:    4.28241e-06
 
 Ruby_current_time: 276484
 Ruby_start_time: 0
 Ruby_cycles: 276484
 
-mbytes_resident: 46.1367
-mbytes_total: 218.203
-resident_ratio: 0.211439
+mbytes_resident: 52
+mbytes_total: 227.848
+resident_ratio: 0.228223
 
 ruby_cycles_executed: [ 276485 ]
 
@@ -125,10 +125,10 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 12102
-page_faults: 2
+page_reclaims: 13872
+page_faults: 0
 swaps: 0
-block_inputs: 144
+block_inputs: 0
 block_outputs: 88
 
 Network Stats
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
index f8a22f9ca..15a51cba3 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:53
-gem5 started Feb 11 2012 14:04:37
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing-ruby
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:50:07
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 31a5db86e..3c66f2b85 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000276                       # Nu
 sim_ticks                                      276484                       # Number of ticks simulated
 final_tick                                     276484                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  47191                       # Simulator instruction rate (inst/s)
-host_op_rate                                    85448                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                2407911                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228676                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                  46315                       # Simulator instruction rate (inst/s)
+host_op_rate                                    83864                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                2363372                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 233320                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
 sim_insts                                        5417                       # Number of instructions simulated
 sim_ops                                          9810                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       62348                       # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index 7bd202ff4..b01f0f148 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -91,11 +90,11 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[3]
+port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -116,7 +115,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -124,8 +123,9 @@ int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
 system=system
-int_port=system.membus.port[4]
-pio=system.membus.port[3]
+int_master=system.membus.slave[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.itb]
 type=X86TLB
@@ -136,11 +136,11 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 system=system
-port=system.cpu.toL2Bus.port[2]
+port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -160,8 +160,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[4]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -171,7 +171,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -203,15 +204,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
index 89203c6bc..f6aa045a2 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:53
-gem5 started Feb 11 2012 14:04:26
-gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing
+gem5 compiled May  8 2012 15:05:30
+gem5 started May  8 2012 15:50:07
+gem5 executing on piton
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index c2e4355d3..bb825e929 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000029                       # Nu
 sim_ticks                                    28768000                       # Number of ticks simulated
 final_tick                                   28768000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 265683                       # Simulator instruction rate (inst/s)
-host_op_rate                                   480724                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1408532008                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216996                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 193646                       # Simulator instruction rate (inst/s)
+host_op_rate                                   350298                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1026195488                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221892                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        5417                       # Number of instructions simulated
 sim_ops                                          9810                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       23104                       # Number of bytes read from this memory
@@ -86,8 +86,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          228                       # number of ReadReq MSHR misses
@@ -162,8 +162,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
@@ -259,8 +259,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          227                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index 14cc5821d..60ac42ca2 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -419,7 +418,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -440,7 +439,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
@@ -451,7 +450,7 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -471,8 +470,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -482,7 +481,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -533,15 +533,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index 2e652c55a..c897f1e4e 100755
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:15:14
-gem5 started Feb 12 2012 17:33:14
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:40:54
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index f99bdda93..244839beb 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000014                       # Nu
 sim_ticks                                    13973500                       # Number of ticks simulated
 final_tick                                   13973500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  94205                       # Simulator instruction rate (inst/s)
-host_op_rate                                    94192                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              103032063                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 210576                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
+host_inst_rate                                  43715                       # Simulator instruction rate (inst/s)
+host_op_rate                                    43711                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               47815570                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215652                       # Number of bytes of host memory used
+host_seconds                                     0.29                       # Real time elapsed on the host
 sim_insts                                       12773                       # Number of instructions simulated
 sim_ops                                         12773                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       62784                       # Number of bytes read from this memory
@@ -509,8 +509,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          262                       # number of ReadReq MSHR hits
@@ -593,8 +593,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          104                       # number of ReadReq MSHR hits
@@ -701,7 +701,7 @@ system.cpu.l2cache.blocked_cycles::no_targets            0
 system.cpu.l2cache.blocked::no_mshrs                4                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs         5250                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          628                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
index a2e6b7523..8b9b39b0d 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -41,7 +40,6 @@ choiceCtrBits=2
 choicePredictorSize=8192
 clock=500
 cpu_id=0
-dataMemPort=dcache_port
 defer_registration=false
 div16Latency=1
 div16RepeatRate=1
@@ -56,7 +54,6 @@ do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
-fetchMemPort=icache_port
 functionTrace=false
 functionTraceStart=0
 function_trace=false
@@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -115,7 +112,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -123,7 +120,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -144,7 +141,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=SparcInterrupts
@@ -155,7 +152,7 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -175,8 +172,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -186,7 +183,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -218,15 +216,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
index 0e8b3f2e0..b2566a0a7 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:18:12
-gem5 started Feb 12 2012 18:17:51
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:36:55
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
index a378be567..5325eaa70 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000025                       # Nu
 sim_ticks                                    25007500                       # Number of ticks simulated
 final_tick                                   25007500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 100667                       # Simulator instruction rate (inst/s)
-host_op_rate                                   100655                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              165855291                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211052                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
+host_inst_rate                                  55900                       # Simulator instruction rate (inst/s)
+host_op_rate                                    55897                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               92110077                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220976                       # Number of bytes of host memory used
+host_seconds                                     0.27                       # Real time elapsed on the host
 sim_insts                                       15175                       # Number of instructions simulated
 sim_ops                                         15175                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       27904                       # Number of bytes read from this memory
@@ -24,30 +24,6 @@ system.cpu.workload.num_syscalls                   18                       # Nu
 system.cpu.numCycles                            50016                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                         21887                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
-system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             453                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           32683                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                            17333                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         34.654910                       # Percentage of cycles cpu is active
-system.cpu.comLoads                              2226                       # Number of Load instructions committed
-system.cpu.comStores                             1448                       # Number of Store instructions committed
-system.cpu.comBranches                           3359                       # Number of Branches instructions committed
-system.cpu.comNops                                726                       # Number of Nop instructions committed
-system.cpu.comNonSpec                             222                       # Number of Non-Speculative instructions committed
-system.cpu.comInts                               7177                       # Number of Integer instructions committed
-system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                       15175                       # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps                         15175                       # Number of Ops committed (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total                 15175                       # Number of Instructions committed (Total)
-system.cpu.cpi                               3.295947                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         3.295947                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.303403                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.303403                       # IPC: Total IPC of All Threads
 system.cpu.branch_predictor.lookups              5015                       # Number of BP lookups
 system.cpu.branch_predictor.condPredicted         3353                       # Number of conditional branches predicted
 system.cpu.branch_predictor.condIncorrect         2379                       # Number of conditional branches incorrect
@@ -74,6 +50,30 @@ system.cpu.execution_unit.mispredictPct     68.949092                       # Pe
 system.cpu.execution_unit.executions            11084                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies                 0                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.contextSwitches                          1                       # Number of context switches
+system.cpu.threadCycles                         21887                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled                             453                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           32683                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                            17333                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         34.654910                       # Percentage of cycles cpu is active
+system.cpu.comLoads                              2226                       # Number of Load instructions committed
+system.cpu.comStores                             1448                       # Number of Store instructions committed
+system.cpu.comBranches                           3359                       # Number of Branches instructions committed
+system.cpu.comNops                                726                       # Number of Nop instructions committed
+system.cpu.comNonSpec                             222                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                               7177                       # Number of Integer instructions committed
+system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
+system.cpu.committedInsts                       15175                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                         15175                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total                 15175                       # Number of Instructions committed (Total)
+system.cpu.cpi                               3.295947                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
+system.cpu.cpi_total                         3.295947                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.303403                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
+system.cpu.ipc_total                         0.303403                       # IPC: Total IPC of All Threads
 system.cpu.stage0.idleCycles                    36923                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                     13093                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage0.utilization               26.177623                       # Percentage of cycles stage was utilized (processing insts).
@@ -132,7 +132,7 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets        65500                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets        32750                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
@@ -218,7 +218,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets      2208000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              44                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets 50181.818182                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          299                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
index a7b62ffbf..64273b3fe 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -419,7 +418,7 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -440,7 +439,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=SparcInterrupts
@@ -451,7 +450,7 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -471,8 +470,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -482,7 +481,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -514,15 +514,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
index 37bab0cbc..076570d2f 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:18:12
-gem5 started Feb 12 2012 18:17:52
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:36:55
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index dae08ebeb..693d12ddb 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000020                       # Nu
 sim_ticks                                    19744500                       # Number of ticks simulated
 final_tick                                   19744500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 108489                       # Simulator instruction rate (inst/s)
-host_op_rate                                   108474                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              148211557                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211612                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
+host_inst_rate                                  52427                       # Simulator instruction rate (inst/s)
+host_op_rate                                    52424                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               71633039                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221536                       # Number of bytes of host memory used
+host_seconds                                     0.28                       # Real time elapsed on the host
 sim_insts                                       14449                       # Number of instructions simulated
 sim_ops                                         14449                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       30976                       # Number of bytes read from this memory
@@ -327,8 +327,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          146                       # number of ReadReq MSHR hits
@@ -413,8 +413,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           55                       # number of ReadReq MSHR hits
@@ -518,8 +518,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          338                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index b6cf50e7b..63fce3718 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
index 15efcd3a3..c5ff1dac8 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 13:55:45
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-atomic
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:36:55
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index de9d99a5d..b4eb79291 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000008                       # Nu
 sim_ticks                                     7618500                       # Number of ticks simulated
 final_tick                                    7618500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 298140                       # Simulator instruction rate (inst/s)
-host_op_rate                                   298037                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              149578582                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 201436                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                 147764                       # Simulator instruction rate (inst/s)
+host_op_rate                                   147721                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               74142280                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211580                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                       15175                       # Number of instructions simulated
 sim_ops                                         15175                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       72223                       # Number of bytes read from this memory
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
index a5f3d5088..ad6d2cdd3 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=SparcInterrupts
@@ -120,7 +119,7 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
index 6f63071eb..9346f2ccc 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 13:55:45
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:42:54
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index f7405d428..dfba79da8 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000042                       # Nu
 sim_ticks                                    41800000                       # Number of ticks simulated
 final_tick                                   41800000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 399467                       # Simulator instruction rate (inst/s)
-host_op_rate                                   399277                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1099343547                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 210560                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                 130693                       # Simulator instruction rate (inst/s)
+host_op_rate                                   130661                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              359830859                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220580                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
 sim_insts                                       15175                       # Number of instructions simulated
 sim_ops                                         15175                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       26624                       # Number of bytes read from this memory
@@ -86,8 +86,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          280                       # number of ReadReq MSHR misses
@@ -166,8 +166,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
@@ -263,8 +263,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          278                       # number of ReadReq MSHR misses
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
index 850fc5669..2ed8852ac 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
@@ -1,6 +1,9 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
-
-gzip: stdout: Broken pipe
+Traceback (most recent call last):
+  File "<string>", line 1, in <module>
+  File "/n/piton/z/nate/work/m5/work/src/python/m5/main.py", line 357, in main
+    exec filecode in scope
+  File "tests/run.py", line 78, in <module>
+    execfile(joinpath(tests_root, category, mode, name, 'test.py'))
+  File "tests/quick/se/20.eio-short/test.py", line 29, in <module>
+    root.system.cpu.workload = EioProcess(file = binpath('anagram',
+NameError: name 'EioProcess' is not defined
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
index 94e5c0a9b..a0bfbf546 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
@@ -1,12 +1,7 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 29 2012 00:47:21
-gem5 started Feb 29 2012 00:51:57
-gem5 executing on zizzer
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:08
+gem5 executing on piton
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-main dictionary has 1245 entries
-49508 bytes wasted
->Exiting @ tick 250015500 because a thread reached the max instruction count
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
index 5065b3dff..e69de29bb 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
@@ -1,80 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000250                       # Number of seconds simulated
-sim_ticks                                   250015500                       # Number of ticks simulated
-final_tick                                  250015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3174528                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3174125                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1586983445                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 203780                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
-sim_insts                                      500001                       # Number of instructions simulated
-sim_ops                                        500001                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                     2872676                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                2000076                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                   417562                       # Number of bytes written to this memory
-system.physmem.num_reads                       624454                       # Number of read requests responded to by this memory
-system.physmem.num_writes                       56340                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                    11489991621                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                7999808012                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                    1670144451                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                   13160136072                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                       124435                       # DTB read hits
-system.cpu.dtb.read_misses                          8                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                   124443                       # DTB read accesses
-system.cpu.dtb.write_hits                       56340                       # DTB write hits
-system.cpu.dtb.write_misses                        10                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                   56350                       # DTB write accesses
-system.cpu.dtb.data_hits                       180775                       # DTB hits
-system.cpu.dtb.data_misses                         18                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                   180793                       # DTB accesses
-system.cpu.itb.fetch_hits                      500019                       # ITB hits
-system.cpu.itb.fetch_misses                        13                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                  500032                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                           500032                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                      500001                       # Number of instructions committed
-system.cpu.committedOps                        500001                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                474689                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     32                       # Number of float alu accesses
-system.cpu.num_func_calls                       14357                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                       474689                       # number of integer instructions
-system.cpu.num_fp_insts                            32                       # number of float instructions
-system.cpu.num_int_register_reads              654286                       # number of times the integer registers were read
-system.cpu.num_int_register_writes             371542                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   32                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_mem_refs                        180793                       # number of memory refs
-system.cpu.num_load_insts                      124443                       # Number of load instructions
-system.cpu.num_store_insts                      56350                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     500032                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
index 850fc5669..2ed8852ac 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
@@ -1,6 +1,9 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
-
-gzip: stdout: Broken pipe
+Traceback (most recent call last):
+  File "<string>", line 1, in <module>
+  File "/n/piton/z/nate/work/m5/work/src/python/m5/main.py", line 357, in main
+    exec filecode in scope
+  File "tests/run.py", line 78, in <module>
+    execfile(joinpath(tests_root, category, mode, name, 'test.py'))
+  File "tests/quick/se/20.eio-short/test.py", line 29, in <module>
+    root.system.cpu.workload = EioProcess(file = binpath('anagram',
+NameError: name 'EioProcess' is not defined
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
index 51a8ca57b..cd02db6e7 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
@@ -1,12 +1,7 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 29 2012 00:47:21
-gem5 started Feb 29 2012 00:51:57
-gem5 executing on zizzer
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:07
+gem5 executing on piton
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-main dictionary has 1245 entries
-49508 bytes wasted
->Exiting @ tick 727929000 because a thread reached the max instruction count
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
index a62b8b2ca..e69de29bb 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
@@ -1,330 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000728                       # Number of seconds simulated
-sim_ticks                                   727929000                       # Number of ticks simulated
-final_tick                                  727929000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1742138                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1742023                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2535976572                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212652                       # Number of bytes of host memory used
-host_seconds                                     0.29                       # Real time elapsed on the host
-sim_insts                                      500001                       # Number of instructions simulated
-sim_ops                                        500001                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       54848                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          857                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       75348008                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                  35432027                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      75348008                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                       124435                       # DTB read hits
-system.cpu.dtb.read_misses                          8                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                   124443                       # DTB read accesses
-system.cpu.dtb.write_hits                       56340                       # DTB write hits
-system.cpu.dtb.write_misses                        10                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                   56350                       # DTB write accesses
-system.cpu.dtb.data_hits                       180775                       # DTB hits
-system.cpu.dtb.data_misses                         18                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                   180793                       # DTB accesses
-system.cpu.itb.fetch_hits                      500020                       # ITB hits
-system.cpu.itb.fetch_misses                        13                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                  500033                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                          1455858                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                      500001                       # Number of instructions committed
-system.cpu.committedOps                        500001                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                474689                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     32                       # Number of float alu accesses
-system.cpu.num_func_calls                       14357                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                       474689                       # number of integer instructions
-system.cpu.num_fp_insts                            32                       # number of float instructions
-system.cpu.num_int_register_reads              654286                       # number of times the integer registers were read
-system.cpu.num_int_register_writes             371542                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   32                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_mem_refs                        180793                       # number of memory refs
-system.cpu.num_load_insts                      124443                       # Number of load instructions
-system.cpu.num_store_insts                      56350                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                    1455858                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                264.952126                       # Cycle average of tags in use
-system.cpu.icache.total_refs                   499617                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    403                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                1239.744417                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     264.952126                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.129371                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.129371                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst       499617                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total          499617                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst        499617                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total           499617                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst       499617                       # number of overall hits
-system.cpu.icache.overall_hits::total          499617                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          403                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           403                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          403                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            403                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          403                       # number of overall misses
-system.cpu.icache.overall_misses::total           403                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     22568000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     22568000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     22568000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     22568000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     22568000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     22568000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst       500020                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total       500020                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst       500020                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total       500020                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst       500020                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total       500020                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000806                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000806                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000806                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          403                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          403                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          403                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          403                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          403                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          403                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     21359000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     21359000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     21359000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     21359000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     21359000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     21359000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000806                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000806                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000806                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                287.175167                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                   180321                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                    454                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 397.182819                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     287.175167                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.070111                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.070111                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data       124120                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total          124120                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data        56201                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total          56201                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data        180321                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total           180321                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data       180321                       # number of overall hits
-system.cpu.dcache.overall_hits::total          180321                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          315                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           315                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          139                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          454                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            454                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          454                       # number of overall misses
-system.cpu.dcache.overall_misses::total           454                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     17640000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     17640000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      7784000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      7784000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     25424000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     25424000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     25424000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     25424000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data       180775                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data       180775                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002531                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002511                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002511                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          315                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          315                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data          139                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          454                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          454                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          454                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          454                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     16695000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     16695000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      7367000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      7367000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     24062000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     24062000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     24062000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     24062000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002531                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002511                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002511                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               481.419470                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                   718                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                         0                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    264.958770                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    216.460700                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.008086                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.006606                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.014692                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_misses::cpu.inst          403                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          315                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          718                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data          139                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          139                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          403                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          454                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           857                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          403                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          454                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          857                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     20956000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     16380000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     37336000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      7228000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      7228000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     20956000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     23608000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     44564000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     20956000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     23608000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     44564000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          403                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          315                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          718                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data          139                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total          139                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          403                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          454                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          857                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          403                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          454                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          857                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          403                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          315                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          718                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          139                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          139                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          403                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          454                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          857                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          403                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          454                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          857                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16120000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     12600000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     28720000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5560000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5560000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16120000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     18160000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     34280000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16120000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     18160000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     34280000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
index 8b296506e..eba0181d6 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
@@ -1,10 +1,9 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
+Traceback (most recent call last):
+  File "<string>", line 1, in <module>
+  File "/n/piton/z/nate/work/m5/work/src/python/m5/main.py", line 357, in main
+    exec filecode in scope
+  File "tests/run.py", line 78, in <module>
+    execfile(joinpath(tests_root, category, mode, name, 'test.py'))
+  File "tests/quick/se/30.eio-mp/test.py", line 29, in <module>
+    process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz'))
+NameError: name 'EioProcess' is not defined
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
index 9e07934a0..f8532632c 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
@@ -1,18 +1,7 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 29 2012 00:47:21
-gem5 started Feb 29 2012 00:51:57
-gem5 executing on zizzer
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:40:55
+gem5 executing on piton
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
->>>>Exiting @ tick 250015500 because a thread reached the max instruction count
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index 8880fe952..e69de29bb 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -1,749 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000250                       # Number of seconds simulated
-sim_ticks                                   250015500                       # Number of ticks simulated
-final_tick                                  250015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3384594                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3384489                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              423074550                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1140672                       # Number of bytes of host memory used
-host_seconds                                     0.59                       # Real time elapsed on the host
-sim_insts                                     2000004                       # Number of instructions simulated
-sim_ops                                       2000004                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                      219392                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 103168                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                         3428                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      877513594                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 412646416                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     877513594                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu0.dtb.fetch_hits                          0                       # ITB hits
-system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.fetch_acv                           0                       # ITB acv
-system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                      124435                       # DTB read hits
-system.cpu0.dtb.read_misses                         8                       # DTB read misses
-system.cpu0.dtb.read_acv                            0                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu0.dtb.write_hits                      56340                       # DTB write hits
-system.cpu0.dtb.write_misses                       10                       # DTB write misses
-system.cpu0.dtb.write_acv                           0                       # DTB write access violations
-system.cpu0.dtb.write_accesses                  56350                       # DTB write accesses
-system.cpu0.dtb.data_hits                      180775                       # DTB hits
-system.cpu0.dtb.data_misses                        18                       # DTB misses
-system.cpu0.dtb.data_acv                            0                       # DTB access violations
-system.cpu0.dtb.data_accesses                  180793                       # DTB accesses
-system.cpu0.itb.fetch_hits                     500019                       # ITB hits
-system.cpu0.itb.fetch_misses                       13                       # ITB misses
-system.cpu0.itb.fetch_acv                           0                       # ITB acv
-system.cpu0.itb.fetch_accesses                 500032                       # ITB accesses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.read_acv                            0                       # DTB read access violations
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.write_acv                           0                       # DTB write access violations
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.data_hits                           0                       # DTB hits
-system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.data_acv                            0                       # DTB access violations
-system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.workload.num_syscalls                  18                       # Number of system calls
-system.cpu0.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     500001                       # Number of instructions committed
-system.cpu0.committedOps                       500001                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu0.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      474689                       # number of integer instructions
-system.cpu0.num_fp_insts                           32                       # number of float instructions
-system.cpu0.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                       180793                       # number of memory refs
-system.cpu0.num_load_insts                     124443                       # Number of load instructions
-system.cpu0.num_store_insts                     56350                       # Number of store instructions
-system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu0.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu0.icache.replacements                   152                       # number of replacements
-system.cpu0.icache.tagsinuse               218.086151                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                  499556                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs               1078.954644                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   218.086151                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.425950                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst       499556                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       499556                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          499556                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       499556                       # number of overall hits
-system.cpu0.icache.overall_hits::total         499556                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          463                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          463                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          463                       # number of overall misses
-system.cpu0.icache.overall_misses::total          463                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       500019                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       500019                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.000926                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.000926                       # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements                    61                       # number of replacements
-system.cpu0.dcache.tagsinuse               276.872320                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                  180312                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                389.442765                       # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   276.872320                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.540766                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.540766                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data       124111                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        56201                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       180312                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       180312                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         180312                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          324                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          139                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu0.dcache.demand_misses::cpu0.data          463                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data          463                       # number of overall misses
-system.cpu0.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       180775                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       180775                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.002561                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.002561                       # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu0.dcache.writebacks::total               29                       # number of writebacks
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dtb.fetch_hits                          0                       # ITB hits
-system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.fetch_acv                           0                       # ITB acv
-system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                      124435                       # DTB read hits
-system.cpu1.dtb.read_misses                         8                       # DTB read misses
-system.cpu1.dtb.read_acv                            0                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu1.dtb.write_hits                      56340                       # DTB write hits
-system.cpu1.dtb.write_misses                       10                       # DTB write misses
-system.cpu1.dtb.write_acv                           0                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  56350                       # DTB write accesses
-system.cpu1.dtb.data_hits                      180775                       # DTB hits
-system.cpu1.dtb.data_misses                        18                       # DTB misses
-system.cpu1.dtb.data_acv                            0                       # DTB access violations
-system.cpu1.dtb.data_accesses                  180793                       # DTB accesses
-system.cpu1.itb.fetch_hits                     500019                       # ITB hits
-system.cpu1.itb.fetch_misses                       13                       # ITB misses
-system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                 500032                       # ITB accesses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.read_acv                            0                       # DTB read access violations
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.write_acv                           0                       # DTB write access violations
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.data_hits                           0                       # DTB hits
-system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.data_acv                            0                       # DTB access violations
-system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.workload.num_syscalls                  18                       # Number of system calls
-system.cpu1.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                     500001                       # Number of instructions committed
-system.cpu1.committedOps                       500001                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu1.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                      474689                       # number of integer instructions
-system.cpu1.num_fp_insts                           32                       # number of float instructions
-system.cpu1.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                       180793                       # number of memory refs
-system.cpu1.num_load_insts                     124443                       # Number of load instructions
-system.cpu1.num_store_insts                     56350                       # Number of store instructions
-system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu1.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu1.icache.replacements                   152                       # number of replacements
-system.cpu1.icache.tagsinuse               218.086151                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                  499556                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs               1078.954644                       # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst   218.086151                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.425950                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst       499556                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       499556                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          499556                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       499556                       # number of overall hits
-system.cpu1.icache.overall_hits::total         499556                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          463                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          463                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          463                       # number of overall misses
-system.cpu1.icache.overall_misses::total          463                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       500019                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       500019                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.000926                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.000926                       # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                    61                       # number of replacements
-system.cpu1.dcache.tagsinuse               276.872320                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                  180312                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                389.442765                       # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data   276.872320                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.540766                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.540766                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data       124111                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        56201                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
-system.cpu1.dcache.demand_hits::cpu1.data       180312                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data       180312                       # number of overall hits
-system.cpu1.dcache.overall_hits::total         180312                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          324                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          139                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          463                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          463                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data       180775                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data       180775                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.002561                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.002561                       # miss rate for overall accesses
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu1.dcache.writebacks::total               29                       # number of writebacks
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dtb.fetch_hits                          0                       # ITB hits
-system.cpu2.dtb.fetch_misses                        0                       # ITB misses
-system.cpu2.dtb.fetch_acv                           0                       # ITB acv
-system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                      124435                       # DTB read hits
-system.cpu2.dtb.read_misses                         8                       # DTB read misses
-system.cpu2.dtb.read_acv                            0                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu2.dtb.write_hits                      56340                       # DTB write hits
-system.cpu2.dtb.write_misses                       10                       # DTB write misses
-system.cpu2.dtb.write_acv                           0                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  56350                       # DTB write accesses
-system.cpu2.dtb.data_hits                      180775                       # DTB hits
-system.cpu2.dtb.data_misses                        18                       # DTB misses
-system.cpu2.dtb.data_acv                            0                       # DTB access violations
-system.cpu2.dtb.data_accesses                  180793                       # DTB accesses
-system.cpu2.itb.fetch_hits                     500019                       # ITB hits
-system.cpu2.itb.fetch_misses                       13                       # ITB misses
-system.cpu2.itb.fetch_acv                           0                       # ITB acv
-system.cpu2.itb.fetch_accesses                 500032                       # ITB accesses
-system.cpu2.itb.read_hits                           0                       # DTB read hits
-system.cpu2.itb.read_misses                         0                       # DTB read misses
-system.cpu2.itb.read_acv                            0                       # DTB read access violations
-system.cpu2.itb.read_accesses                       0                       # DTB read accesses
-system.cpu2.itb.write_hits                          0                       # DTB write hits
-system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.write_acv                           0                       # DTB write access violations
-system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.data_hits                           0                       # DTB hits
-system.cpu2.itb.data_misses                         0                       # DTB misses
-system.cpu2.itb.data_acv                            0                       # DTB access violations
-system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.workload.num_syscalls                  18                       # Number of system calls
-system.cpu2.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                     500001                       # Number of instructions committed
-system.cpu2.committedOps                       500001                       # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu2.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu2.num_int_insts                      474689                       # number of integer instructions
-system.cpu2.num_fp_insts                           32                       # number of float instructions
-system.cpu2.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu2.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu2.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu2.num_mem_refs                       180793                       # number of memory refs
-system.cpu2.num_load_insts                     124443                       # Number of load instructions
-system.cpu2.num_store_insts                     56350                       # Number of store instructions
-system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu2.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu2.icache.replacements                   152                       # number of replacements
-system.cpu2.icache.tagsinuse               218.086151                       # Cycle average of tags in use
-system.cpu2.icache.total_refs                  499556                       # Total number of references to valid blocks.
-system.cpu2.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu2.icache.avg_refs               1078.954644                       # Average number of references to valid blocks.
-system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::cpu2.inst   218.086151                       # Average occupied blocks per requestor
-system.cpu2.icache.occ_percent::cpu2.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu2.icache.occ_percent::total        0.425950                       # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst       499556                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst       499556                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total          499556                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst       499556                       # number of overall hits
-system.cpu2.icache.overall_hits::total         499556                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          463                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          463                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          463                       # number of overall misses
-system.cpu2.icache.overall_misses::total          463                       # number of overall misses
-system.cpu2.icache.ReadReq_accesses::cpu2.inst       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst       500019                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst       500019                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.000926                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.000926                       # miss rate for overall accesses
-system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dcache.replacements                    61                       # number of replacements
-system.cpu2.dcache.tagsinuse               276.872320                       # Cycle average of tags in use
-system.cpu2.dcache.total_refs                  180312                       # Total number of references to valid blocks.
-system.cpu2.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu2.dcache.avg_refs                389.442765                       # Average number of references to valid blocks.
-system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.occ_blocks::cpu2.data   276.872320                       # Average occupied blocks per requestor
-system.cpu2.dcache.occ_percent::cpu2.data     0.540766                       # Average percentage of cache occupancy
-system.cpu2.dcache.occ_percent::total        0.540766                       # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits::cpu2.data       124111                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        56201                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
-system.cpu2.dcache.demand_hits::cpu2.data       180312                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data       180312                       # number of overall hits
-system.cpu2.dcache.overall_hits::total         180312                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          324                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          463                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          463                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu2.dcache.ReadReq_accesses::cpu2.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data       180775                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data       180775                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.002561                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.002561                       # miss rate for overall accesses
-system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu2.dcache.writebacks::total               29                       # number of writebacks
-system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dtb.fetch_hits                          0                       # ITB hits
-system.cpu3.dtb.fetch_misses                        0                       # ITB misses
-system.cpu3.dtb.fetch_acv                           0                       # ITB acv
-system.cpu3.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu3.dtb.read_hits                      124435                       # DTB read hits
-system.cpu3.dtb.read_misses                         8                       # DTB read misses
-system.cpu3.dtb.read_acv                            0                       # DTB read access violations
-system.cpu3.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu3.dtb.write_hits                      56340                       # DTB write hits
-system.cpu3.dtb.write_misses                       10                       # DTB write misses
-system.cpu3.dtb.write_acv                           0                       # DTB write access violations
-system.cpu3.dtb.write_accesses                  56350                       # DTB write accesses
-system.cpu3.dtb.data_hits                      180775                       # DTB hits
-system.cpu3.dtb.data_misses                        18                       # DTB misses
-system.cpu3.dtb.data_acv                            0                       # DTB access violations
-system.cpu3.dtb.data_accesses                  180793                       # DTB accesses
-system.cpu3.itb.fetch_hits                     500019                       # ITB hits
-system.cpu3.itb.fetch_misses                       13                       # ITB misses
-system.cpu3.itb.fetch_acv                           0                       # ITB acv
-system.cpu3.itb.fetch_accesses                 500032                       # ITB accesses
-system.cpu3.itb.read_hits                           0                       # DTB read hits
-system.cpu3.itb.read_misses                         0                       # DTB read misses
-system.cpu3.itb.read_acv                            0                       # DTB read access violations
-system.cpu3.itb.read_accesses                       0                       # DTB read accesses
-system.cpu3.itb.write_hits                          0                       # DTB write hits
-system.cpu3.itb.write_misses                        0                       # DTB write misses
-system.cpu3.itb.write_acv                           0                       # DTB write access violations
-system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.data_hits                           0                       # DTB hits
-system.cpu3.itb.data_misses                         0                       # DTB misses
-system.cpu3.itb.data_acv                            0                       # DTB access violations
-system.cpu3.itb.data_accesses                       0                       # DTB accesses
-system.cpu3.workload.num_syscalls                  18                       # Number of system calls
-system.cpu3.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.committedInsts                     500001                       # Number of instructions committed
-system.cpu3.committedOps                       500001                       # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu3.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu3.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu3.num_int_insts                      474689                       # number of integer instructions
-system.cpu3.num_fp_insts                           32                       # number of float instructions
-system.cpu3.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu3.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu3.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu3.num_mem_refs                       180793                       # number of memory refs
-system.cpu3.num_load_insts                     124443                       # Number of load instructions
-system.cpu3.num_store_insts                     56350                       # Number of store instructions
-system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu3.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu3.icache.replacements                   152                       # number of replacements
-system.cpu3.icache.tagsinuse               218.086151                       # Cycle average of tags in use
-system.cpu3.icache.total_refs                  499556                       # Total number of references to valid blocks.
-system.cpu3.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu3.icache.avg_refs               1078.954644                       # Average number of references to valid blocks.
-system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::cpu3.inst   218.086151                       # Average occupied blocks per requestor
-system.cpu3.icache.occ_percent::cpu3.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu3.icache.occ_percent::total        0.425950                       # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits::cpu3.inst       499556                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst       499556                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total          499556                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst       499556                       # number of overall hits
-system.cpu3.icache.overall_hits::total         499556                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          463                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          463                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          463                       # number of overall misses
-system.cpu3.icache.overall_misses::total          463                       # number of overall misses
-system.cpu3.icache.ReadReq_accesses::cpu3.inst       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst       500019                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst       500019                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.000926                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.000926                       # miss rate for overall accesses
-system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dcache.replacements                    61                       # number of replacements
-system.cpu3.dcache.tagsinuse               276.872320                       # Cycle average of tags in use
-system.cpu3.dcache.total_refs                  180312                       # Total number of references to valid blocks.
-system.cpu3.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu3.dcache.avg_refs                389.442765                       # Average number of references to valid blocks.
-system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.occ_blocks::cpu3.data   276.872320                       # Average occupied blocks per requestor
-system.cpu3.dcache.occ_percent::cpu3.data     0.540766                       # Average percentage of cache occupancy
-system.cpu3.dcache.occ_percent::total        0.540766                       # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits::cpu3.data       124111                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        56201                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
-system.cpu3.dcache.demand_hits::cpu3.data       180312                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data       180312                       # number of overall hits
-system.cpu3.dcache.overall_hits::total         180312                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          324                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          139                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          463                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          463                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu3.dcache.ReadReq_accesses::cpu3.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data       180775                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data       180775                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.002561                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.002561                       # miss rate for overall accesses
-system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu3.dcache.writebacks::total               29                       # number of writebacks
-system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.l2c.replacements                             0                       # number of replacements
-system.l2c.tagsinuse                      1962.780232                       # Cycle average of tags in use
-system.l2c.total_refs                             332                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                          2932                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          0.113233                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks           17.466765                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst           267.152061                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data           219.176305                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst           267.152061                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data           219.176305                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.inst           267.152061                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data           219.176305                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.inst           267.152061                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.data           219.176305                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.000267                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.004076                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.003344                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.004076                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data            0.003344                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.inst            0.004076                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.data            0.003344                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu3.inst            0.004076                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu3.data            0.003344                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.029950                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                    276                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks             116                       # number of Writeback hits
-system.l2c.Writeback_hits::total                  116                       # number of Writeback hits
-system.l2c.demand_hits::cpu0.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                     276                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu0.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu1.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
-system.l2c.overall_hits::total                    276                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 2872                       # number of ReadReq misses
-system.l2c.ReadExReq_misses::cpu0.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                556                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                  3428                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu1.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu2.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu3.data              454                       # number of overall misses
-system.l2c.overall_misses::total                 3428                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               3148                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks          116                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total              116                       # number of Writeback accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total              556                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                3704                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               3704                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.980562                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.980562                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
index 8b296506e..eba0181d6 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
@@ -1,10 +1,9 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
+Traceback (most recent call last):
+  File "<string>", line 1, in <module>
+  File "/n/piton/z/nate/work/m5/work/src/python/m5/main.py", line 357, in main
+    exec filecode in scope
+  File "tests/run.py", line 78, in <module>
+    execfile(joinpath(tests_root, category, mode, name, 'test.py'))
+  File "tests/quick/se/30.eio-mp/test.py", line 29, in <module>
+    process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz'))
+NameError: name 'EioProcess' is not defined
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index ae6fe41da..f3027b2ea 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -1,18 +1,7 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 29 2012 00:47:21
-gem5 started Feb 29 2012 00:51:57
-gem5 executing on zizzer
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:36:56
+gem5 executing on piton
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
->>>>Exiting @ tick 728920000 because a thread reached the max instruction count
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index 08b853160..e69de29bb 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,1181 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000729                       # Number of seconds simulated
-sim_ticks                                   728920000                       # Number of ticks simulated
-final_tick                                  728920000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1560894                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1560871                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              568880584                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223172                       # Number of bytes of host memory used
-host_seconds                                     1.28                       # Real time elapsed on the host
-sim_insts                                     1999954                       # Number of instructions simulated
-sim_ops                                       1999954                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                      219392                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 103168                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                         3428                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      300982275                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 141535422                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     300982275                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu0.dtb.fetch_hits                          0                       # ITB hits
-system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.fetch_acv                           0                       # ITB acv
-system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                      124435                       # DTB read hits
-system.cpu0.dtb.read_misses                         8                       # DTB read misses
-system.cpu0.dtb.read_acv                            0                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu0.dtb.write_hits                      56340                       # DTB write hits
-system.cpu0.dtb.write_misses                       10                       # DTB write misses
-system.cpu0.dtb.write_acv                           0                       # DTB write access violations
-system.cpu0.dtb.write_accesses                  56350                       # DTB write accesses
-system.cpu0.dtb.data_hits                      180775                       # DTB hits
-system.cpu0.dtb.data_misses                        18                       # DTB misses
-system.cpu0.dtb.data_acv                            0                       # DTB access violations
-system.cpu0.dtb.data_accesses                  180793                       # DTB accesses
-system.cpu0.itb.fetch_hits                     500020                       # ITB hits
-system.cpu0.itb.fetch_misses                       13                       # ITB misses
-system.cpu0.itb.fetch_acv                           0                       # ITB acv
-system.cpu0.itb.fetch_accesses                 500033                       # ITB accesses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.read_acv                            0                       # DTB read access violations
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.write_acv                           0                       # DTB write access violations
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.data_hits                           0                       # DTB hits
-system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.data_acv                            0                       # DTB access violations
-system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.workload.num_syscalls                  18                       # Number of system calls
-system.cpu0.numCycles                         1457840                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     500001                       # Number of instructions committed
-system.cpu0.committedOps                       500001                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu0.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      474689                       # number of integer instructions
-system.cpu0.num_fp_insts                           32                       # number of float instructions
-system.cpu0.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                       180793                       # number of memory refs
-system.cpu0.num_load_insts                     124443                       # Number of load instructions
-system.cpu0.num_store_insts                     56350                       # Number of store instructions
-system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu0.num_busy_cycles                   1457840                       # Number of busy cycles
-system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu0.icache.replacements                   152                       # number of replacements
-system.cpu0.icache.tagsinuse               216.390931                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                  499557                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs               1078.956803                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   216.390931                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.422639                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.422639                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst       499557                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         499557                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       499557                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          499557                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       499557                       # number of overall hits
-system.cpu0.icache.overall_hits::total         499557                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          463                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          463                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          463                       # number of overall misses
-system.cpu0.icache.overall_misses::total          463                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     23474000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     23474000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     23474000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     23474000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     23474000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     23474000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       500020                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       500020                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       500020                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       500020                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       500020                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       500020                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.000926                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.000926                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 50699.784017                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 50699.784017                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 50699.784017                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          463                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst          463                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst          463                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     22085000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     22085000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     22085000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     22085000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     22085000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     22085000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47699.784017                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47699.784017                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47699.784017                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements                    61                       # number of replacements
-system.cpu0.dcache.tagsinuse               273.518805                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                  180312                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                389.442765                       # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   273.518805                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.534216                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.534216                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data       124111                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        56201                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       180312                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       180312                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         180312                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          324                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          139                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu0.dcache.demand_misses::cpu0.data          463                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data          463                       # number of overall misses
-system.cpu0.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     17785000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total     17785000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      7793000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total      7793000                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     25578000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     25578000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     25578000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     25578000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       180775                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       180775                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.002561                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.002561                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 54891.975309                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 56064.748201                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 55244.060475                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 55244.060475                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu0.dcache.writebacks::total               29                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          324                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          139                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data          463                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data          463                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data     16813000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total     16813000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7376000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7376000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     24189000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     24189000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     24189000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     24189000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002561                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002561                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 51891.975309                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53064.748201                       # average WriteReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52244.060475                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52244.060475                       # average overall mshr miss latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dtb.fetch_hits                          0                       # ITB hits
-system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.fetch_acv                           0                       # ITB acv
-system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                      124435                       # DTB read hits
-system.cpu1.dtb.read_misses                         8                       # DTB read misses
-system.cpu1.dtb.read_acv                            0                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu1.dtb.write_hits                      56339                       # DTB write hits
-system.cpu1.dtb.write_misses                       10                       # DTB write misses
-system.cpu1.dtb.write_acv                           0                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  56349                       # DTB write accesses
-system.cpu1.dtb.data_hits                      180774                       # DTB hits
-system.cpu1.dtb.data_misses                        18                       # DTB misses
-system.cpu1.dtb.data_acv                            0                       # DTB access violations
-system.cpu1.dtb.data_accesses                  180792                       # DTB accesses
-system.cpu1.itb.fetch_hits                     500012                       # ITB hits
-system.cpu1.itb.fetch_misses                       13                       # ITB misses
-system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                 500025                       # ITB accesses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.read_acv                            0                       # DTB read access violations
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.write_acv                           0                       # DTB write access violations
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.data_hits                           0                       # DTB hits
-system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.data_acv                            0                       # DTB access violations
-system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.workload.num_syscalls                  18                       # Number of system calls
-system.cpu1.numCycles                         1457840                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                     499993                       # Number of instructions committed
-system.cpu1.committedOps                       499993                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses               474681                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu1.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                      474681                       # number of integer instructions
-system.cpu1.num_fp_insts                           32                       # number of float instructions
-system.cpu1.num_int_register_reads             654273                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes            371536                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                       180792                       # number of memory refs
-system.cpu1.num_load_insts                     124443                       # Number of load instructions
-system.cpu1.num_store_insts                     56349                       # Number of store instructions
-system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu1.num_busy_cycles                   1457840                       # Number of busy cycles
-system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu1.icache.replacements                   152                       # number of replacements
-system.cpu1.icache.tagsinuse               216.386658                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                  499549                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs               1078.939525                       # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst   216.386658                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.422630                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.422630                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst       499549                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         499549                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       499549                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          499549                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       499549                       # number of overall hits
-system.cpu1.icache.overall_hits::total         499549                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          463                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          463                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          463                       # number of overall misses
-system.cpu1.icache.overall_misses::total          463                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     23473000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total     23473000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst     23473000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total     23473000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst     23473000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total     23473000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       500012                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       500012                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       500012                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       500012                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       500012                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       500012                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.000926                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.000926                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 50697.624190                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 50697.624190                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 50697.624190                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          463                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst          463                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst          463                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     22084000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total     22084000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     22084000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total     22084000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     22084000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total     22084000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 47697.624190                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 47697.624190                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47697.624190                       # average overall mshr miss latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                    61                       # number of replacements
-system.cpu1.dcache.tagsinuse               273.512548                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                  180311                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                389.440605                       # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data   273.512548                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.534204                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.534204                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data       124111                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        56200                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         56200                       # number of WriteReq hits
-system.cpu1.dcache.demand_hits::cpu1.data       180311                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total          180311                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data       180311                       # number of overall hits
-system.cpu1.dcache.overall_hits::total         180311                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          324                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          139                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          463                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          463                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data     17785000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total     17785000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      7803000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      7803000                       # number of WriteReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data     25588000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total     25588000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data     25588000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total     25588000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data       180774                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total       180774                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data       180774                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total       180774                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.002561                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.002561                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 54891.975309                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 56136.690647                       # average WriteReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 55265.658747                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 55265.658747                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu1.dcache.writebacks::total               29                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          324                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          139                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          463                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          463                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data     16813000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total     16813000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      7386000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      7386000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data     24199000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total     24199000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data     24199000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total     24199000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002561                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002561                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 51891.975309                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53136.690647                       # average WriteReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52265.658747                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52265.658747                       # average overall mshr miss latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dtb.fetch_hits                          0                       # ITB hits
-system.cpu2.dtb.fetch_misses                        0                       # ITB misses
-system.cpu2.dtb.fetch_acv                           0                       # ITB acv
-system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                      124433                       # DTB read hits
-system.cpu2.dtb.read_misses                         8                       # DTB read misses
-system.cpu2.dtb.read_acv                            0                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  124441                       # DTB read accesses
-system.cpu2.dtb.write_hits                      56339                       # DTB write hits
-system.cpu2.dtb.write_misses                       10                       # DTB write misses
-system.cpu2.dtb.write_acv                           0                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  56349                       # DTB write accesses
-system.cpu2.dtb.data_hits                      180772                       # DTB hits
-system.cpu2.dtb.data_misses                        18                       # DTB misses
-system.cpu2.dtb.data_acv                            0                       # DTB access violations
-system.cpu2.dtb.data_accesses                  180790                       # DTB accesses
-system.cpu2.itb.fetch_hits                     500001                       # ITB hits
-system.cpu2.itb.fetch_misses                       13                       # ITB misses
-system.cpu2.itb.fetch_acv                           0                       # ITB acv
-system.cpu2.itb.fetch_accesses                 500014                       # ITB accesses
-system.cpu2.itb.read_hits                           0                       # DTB read hits
-system.cpu2.itb.read_misses                         0                       # DTB read misses
-system.cpu2.itb.read_acv                            0                       # DTB read access violations
-system.cpu2.itb.read_accesses                       0                       # DTB read accesses
-system.cpu2.itb.write_hits                          0                       # DTB write hits
-system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.write_acv                           0                       # DTB write access violations
-system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.data_hits                           0                       # DTB hits
-system.cpu2.itb.data_misses                         0                       # DTB misses
-system.cpu2.itb.data_acv                            0                       # DTB access violations
-system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.workload.num_syscalls                  18                       # Number of system calls
-system.cpu2.numCycles                         1457840                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                     499982                       # Number of instructions committed
-system.cpu2.committedOps                       499982                       # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses               474671                       # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu2.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
-system.cpu2.num_int_insts                      474671                       # number of integer instructions
-system.cpu2.num_fp_insts                           32                       # number of float instructions
-system.cpu2.num_int_register_reads             654261                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            371526                       # number of times the integer registers were written
-system.cpu2.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu2.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu2.num_mem_refs                       180789                       # number of memory refs
-system.cpu2.num_load_insts                     124440                       # Number of load instructions
-system.cpu2.num_store_insts                     56349                       # Number of store instructions
-system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu2.num_busy_cycles                   1457840                       # Number of busy cycles
-system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu2.icache.replacements                   152                       # number of replacements
-system.cpu2.icache.tagsinuse               216.383557                       # Cycle average of tags in use
-system.cpu2.icache.total_refs                  499538                       # Total number of references to valid blocks.
-system.cpu2.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu2.icache.avg_refs               1078.915767                       # Average number of references to valid blocks.
-system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::cpu2.inst   216.383557                       # Average occupied blocks per requestor
-system.cpu2.icache.occ_percent::cpu2.inst     0.422624                       # Average percentage of cache occupancy
-system.cpu2.icache.occ_percent::total        0.422624                       # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst       499538                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total         499538                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst       499538                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total          499538                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst       499538                       # number of overall hits
-system.cpu2.icache.overall_hits::total         499538                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          463                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          463                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          463                       # number of overall misses
-system.cpu2.icache.overall_misses::total          463                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     23483000                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total     23483000                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst     23483000                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total     23483000                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst     23483000                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total     23483000                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst       500001                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total       500001                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst       500001                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total       500001                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst       500001                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total       500001                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.000926                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.000926                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 50719.222462                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 50719.222462                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 50719.222462                       # average overall miss latency
-system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          463                       # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst          463                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst          463                       # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     22094000                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total     22094000                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     22094000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total     22094000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     22094000                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total     22094000                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 47719.222462                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 47719.222462                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47719.222462                       # average overall mshr miss latency
-system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dcache.replacements                    61                       # number of replacements
-system.cpu2.dcache.tagsinuse               273.508588                       # Cycle average of tags in use
-system.cpu2.dcache.total_refs                  180309                       # Total number of references to valid blocks.
-system.cpu2.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu2.dcache.avg_refs                389.436285                       # Average number of references to valid blocks.
-system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.occ_blocks::cpu2.data   273.508588                       # Average occupied blocks per requestor
-system.cpu2.dcache.occ_percent::cpu2.data     0.534196                       # Average percentage of cache occupancy
-system.cpu2.dcache.occ_percent::total        0.534196                       # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits::cpu2.data       124109                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total         124109                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        56200                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         56200                       # number of WriteReq hits
-system.cpu2.dcache.demand_hits::cpu2.data       180309                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total          180309                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data       180309                       # number of overall hits
-system.cpu2.dcache.overall_hits::total         180309                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          324                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          463                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          463                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data     17794000                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total     17794000                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      7797000                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      7797000                       # number of WriteReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data     25591000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total     25591000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data     25591000                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total     25591000                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data       124433                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total       124433                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data       180772                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total       180772                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data       180772                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total       180772                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.002561                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.002561                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 54919.753086                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 56093.525180                       # average WriteReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 55272.138229                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 55272.138229                       # average overall miss latency
-system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu2.dcache.writebacks::total               29                       # number of writebacks
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          324                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          139                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          463                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          463                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data     16822000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total     16822000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      7380000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      7380000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data     24202000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total     24202000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data     24202000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total     24202000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.002561                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.002561                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 51919.753086                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53093.525180                       # average WriteReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52272.138229                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52272.138229                       # average overall mshr miss latency
-system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dtb.fetch_hits                          0                       # ITB hits
-system.cpu3.dtb.fetch_misses                        0                       # ITB misses
-system.cpu3.dtb.fetch_acv                           0                       # ITB acv
-system.cpu3.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu3.dtb.read_hits                      124431                       # DTB read hits
-system.cpu3.dtb.read_misses                         8                       # DTB read misses
-system.cpu3.dtb.read_acv                            0                       # DTB read access violations
-system.cpu3.dtb.read_accesses                  124439                       # DTB read accesses
-system.cpu3.dtb.write_hits                      56339                       # DTB write hits
-system.cpu3.dtb.write_misses                       10                       # DTB write misses
-system.cpu3.dtb.write_acv                           0                       # DTB write access violations
-system.cpu3.dtb.write_accesses                  56349                       # DTB write accesses
-system.cpu3.dtb.data_hits                      180770                       # DTB hits
-system.cpu3.dtb.data_misses                        18                       # DTB misses
-system.cpu3.dtb.data_acv                            0                       # DTB access violations
-system.cpu3.dtb.data_accesses                  180788                       # DTB accesses
-system.cpu3.itb.fetch_hits                     499997                       # ITB hits
-system.cpu3.itb.fetch_misses                       13                       # ITB misses
-system.cpu3.itb.fetch_acv                           0                       # ITB acv
-system.cpu3.itb.fetch_accesses                 500010                       # ITB accesses
-system.cpu3.itb.read_hits                           0                       # DTB read hits
-system.cpu3.itb.read_misses                         0                       # DTB read misses
-system.cpu3.itb.read_acv                            0                       # DTB read access violations
-system.cpu3.itb.read_accesses                       0                       # DTB read accesses
-system.cpu3.itb.write_hits                          0                       # DTB write hits
-system.cpu3.itb.write_misses                        0                       # DTB write misses
-system.cpu3.itb.write_acv                           0                       # DTB write access violations
-system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.data_hits                           0                       # DTB hits
-system.cpu3.itb.data_misses                         0                       # DTB misses
-system.cpu3.itb.data_acv                            0                       # DTB access violations
-system.cpu3.itb.data_accesses                       0                       # DTB accesses
-system.cpu3.workload.num_syscalls                  18                       # Number of system calls
-system.cpu3.numCycles                         1457840                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.committedInsts                     499978                       # Number of instructions committed
-system.cpu3.committedOps                       499978                       # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses               474667                       # Number of integer alu accesses
-system.cpu3.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu3.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts        38178                       # number of instructions that are conditional controls
-system.cpu3.num_int_insts                      474667                       # number of integer instructions
-system.cpu3.num_fp_insts                           32                       # number of float instructions
-system.cpu3.num_int_register_reads             654256                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            371523                       # number of times the integer registers were written
-system.cpu3.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu3.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu3.num_mem_refs                       180787                       # number of memory refs
-system.cpu3.num_load_insts                     124438                       # Number of load instructions
-system.cpu3.num_store_insts                     56349                       # Number of store instructions
-system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu3.num_busy_cycles                   1457840                       # Number of busy cycles
-system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu3.icache.replacements                   152                       # number of replacements
-system.cpu3.icache.tagsinuse               216.381810                       # Cycle average of tags in use
-system.cpu3.icache.total_refs                  499534                       # Total number of references to valid blocks.
-system.cpu3.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu3.icache.avg_refs               1078.907127                       # Average number of references to valid blocks.
-system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::cpu3.inst   216.381810                       # Average occupied blocks per requestor
-system.cpu3.icache.occ_percent::cpu3.inst     0.422621                       # Average percentage of cache occupancy
-system.cpu3.icache.occ_percent::total        0.422621                       # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits::cpu3.inst       499534                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total         499534                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst       499534                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total          499534                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst       499534                       # number of overall hits
-system.cpu3.icache.overall_hits::total         499534                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          463                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          463                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          463                       # number of overall misses
-system.cpu3.icache.overall_misses::total          463                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst     23492000                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total     23492000                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst     23492000                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total     23492000                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst     23492000                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total     23492000                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst       499997                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total       499997                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst       499997                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total       499997                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst       499997                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total       499997                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.000926                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.000926                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 50738.660907                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 50738.660907                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 50738.660907                       # average overall miss latency
-system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          463                       # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst          463                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst          463                       # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst     22103000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total     22103000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst     22103000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total     22103000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst     22103000                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total     22103000                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 47738.660907                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 47738.660907                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 47738.660907                       # average overall mshr miss latency
-system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dcache.replacements                    61                       # number of replacements
-system.cpu3.dcache.tagsinuse               273.505617                       # Cycle average of tags in use
-system.cpu3.dcache.total_refs                  180307                       # Total number of references to valid blocks.
-system.cpu3.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu3.dcache.avg_refs                389.431965                       # Average number of references to valid blocks.
-system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.occ_blocks::cpu3.data   273.505617                       # Average occupied blocks per requestor
-system.cpu3.dcache.occ_percent::cpu3.data     0.534191                       # Average percentage of cache occupancy
-system.cpu3.dcache.occ_percent::total        0.534191                       # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits::cpu3.data       124107                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total         124107                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        56200                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         56200                       # number of WriteReq hits
-system.cpu3.dcache.demand_hits::cpu3.data       180307                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total          180307                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data       180307                       # number of overall hits
-system.cpu3.dcache.overall_hits::total         180307                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          324                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          139                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          463                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          463                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data     17791000                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total     17791000                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      7797000                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      7797000                       # number of WriteReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data     25588000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total     25588000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data     25588000                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total     25588000                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data       124431                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total       124431                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data       180770                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total       180770                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data       180770                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total       180770                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.002561                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.002561                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 54910.493827                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 56093.525180                       # average WriteReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 55265.658747                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 55265.658747                       # average overall miss latency
-system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu3.dcache.writebacks::total               29                       # number of writebacks
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          324                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          139                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          463                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          463                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data     16819000                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total     16819000                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      7380000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      7380000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data     24199000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total     24199000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data     24199000                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total     24199000                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.002561                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.002561                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 51910.493827                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 53093.525180                       # average WriteReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 52265.658747                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52265.658747                       # average overall mshr miss latency
-system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.l2c.replacements                             0                       # number of replacements
-system.l2c.tagsinuse                      1943.298536                       # Cycle average of tags in use
-system.l2c.total_refs                             332                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                          2932                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          0.113233                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks           17.228456                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst           265.029263                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data           216.501106                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst           265.023656                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data           216.496016                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.inst           265.019384                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data           216.492927                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.inst           265.017115                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.data           216.490615                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.000263                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.004044                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.003304                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.004044                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data            0.003303                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.inst            0.004044                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.data            0.003303                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu3.inst            0.004044                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu3.data            0.003303                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.029652                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                    276                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks             116                       # number of Writeback hits
-system.l2c.Writeback_hits::total                  116                       # number of Writeback hits
-system.l2c.demand_hits::cpu0.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                     276                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu0.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu1.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
-system.l2c.overall_hits::total                    276                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 2872                       # number of ReadReq misses
-system.l2c.ReadExReq_misses::cpu0.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                556                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                  3428                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu1.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu2.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu3.data              454                       # number of overall misses
-system.l2c.overall_misses::total                 3428                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst     20968000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data     16386000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst     20958000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data     16380000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst     20961000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data     16382000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.inst     20959000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.data     16381000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      149375000                       # number of ReadReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data      7228000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data      7228000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data      7230000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data      7229000                       # number of ReadExReq miss cycles
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-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40008.810573                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40007.444169                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40004.405286                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40029.776675                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.215859                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40004.962779                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40012.406948                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40008.810573                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40007.444169                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40004.405286                       # average overall mshr miss latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index bb8df191a..5684cea4e 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[2]
+system_port=system.membus.slave[1]
 
 [system.cpu0]
 type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
 
 [system.cpu0.dtb]
 type=SparcTLB
@@ -419,7 +418,7 @@ opLat=3
 
 [system.cpu0.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -440,7 +439,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
 
 [system.cpu0.interrupts]
 type=SparcInterrupts
@@ -570,7 +569,7 @@ icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -591,7 +590,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[4]
+mem_side=system.toL2Bus.slave[3]
 
 [system.cpu1.dtb]
 type=SparcTLB
@@ -862,7 +861,7 @@ opLat=3
 
 [system.cpu1.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -883,7 +882,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[3]
+mem_side=system.toL2Bus.slave[2]
 
 [system.cpu1.interrupts]
 type=SparcInterrupts
@@ -994,7 +993,7 @@ icache_port=system.cpu2.icache.cpu_side
 
 [system.cpu2.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -1015,7 +1014,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
-mem_side=system.toL2Bus.port[6]
+mem_side=system.toL2Bus.slave[5]
 
 [system.cpu2.dtb]
 type=SparcTLB
@@ -1286,7 +1285,7 @@ opLat=3
 
 [system.cpu2.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -1307,7 +1306,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
-mem_side=system.toL2Bus.port[5]
+mem_side=system.toL2Bus.slave[4]
 
 [system.cpu2.interrupts]
 type=SparcInterrupts
@@ -1418,7 +1417,7 @@ icache_port=system.cpu3.icache.cpu_side
 
 [system.cpu3.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -1439,7 +1438,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
-mem_side=system.toL2Bus.port[8]
+mem_side=system.toL2Bus.slave[7]
 
 [system.cpu3.dtb]
 type=SparcTLB
@@ -1710,7 +1709,7 @@ opLat=3
 
 [system.cpu3.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -1731,7 +1730,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
-mem_side=system.toL2Bus.port[7]
+mem_side=system.toL2Bus.slave[6]
 
 [system.cpu3.interrupts]
 type=SparcInterrupts
@@ -1745,7 +1744,7 @@ type=ExeTracer
 
 [system.l2c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
 forward_snoops=true
@@ -1765,8 +1764,8 @@ tgts_per_mshr=16
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[0]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[0]
 
 [system.membus]
 type=Bus
@@ -1776,17 +1775,20 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.mem_side system.physmem.port[0] system.system_port
+master=system.physmem.port[0]
+slave=system.l2c.mem_side system.system_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
 [system.toL2Bus]
 type=Bus
@@ -1796,5 +1798,6 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 84d6c3ee2..9445b3529 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 17:18:12
-gem5 started Feb 12 2012 18:18:13
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:42:58
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index f6ac2f26c..243852286 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000111                       # Nu
 sim_ticks                                   111402500                       # Number of ticks simulated
 final_tick                                  111402500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 189621                       # Simulator instruction rate (inst/s)
-host_op_rate                                   189621                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               19396106                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226052                       # Number of bytes of host memory used
-host_seconds                                     5.74                       # Real time elapsed on the host
+host_inst_rate                                  79928                       # Simulator instruction rate (inst/s)
+host_op_rate                                    79928                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                8175729                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236248                       # Number of bytes of host memory used
+host_seconds                                    13.63                       # Real time elapsed on the host
 sim_insts                                     1089093                       # Number of instructions simulated
 sim_ops                                       1089093                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       43072                       # Number of bytes read from this memory
@@ -329,7 +329,7 @@ system.cpu0.icache.blocked_cycles::no_targets            0
 system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs        15500                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          165                       # number of ReadReq MSHR hits
@@ -421,7 +421,7 @@ system.cpu0.dcache.blocked_cycles::no_targets            0
 system.cpu0.dcache.blocked::no_mshrs               19                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks            6                       # number of writebacks
@@ -774,8 +774,8 @@ system.cpu1.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           70                       # number of ReadReq MSHR hits
@@ -866,8 +866,8 @@ system.cpu1.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks            1                       # number of writebacks
@@ -1221,7 +1221,7 @@ system.cpu2.icache.blocked_cycles::no_targets            0
 system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu2.icache.avg_blocked_cycles::no_mshrs        33000                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           72                       # number of ReadReq MSHR hits
@@ -1312,8 +1312,8 @@ system.cpu2.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.dcache.writebacks::writebacks            1                       # number of writebacks
@@ -1666,8 +1666,8 @@ system.cpu3.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           71                       # number of ReadReq MSHR hits
@@ -1758,8 +1758,8 @@ system.cpu3.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.dcache.writebacks::writebacks            1                       # number of writebacks
@@ -2038,8 +2038,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.ReadReq_mshr_hits::cpu1.inst             1                       # number of ReadReq MSHR hits
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index 90b4c4184..a47e5e15d 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[2]
+system_port=system.membus.slave[1]
 
 [system.cpu0]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu0.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu0.interrupts
@@ -62,7 +62,7 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -83,7 +83,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
 
 [system.cpu0.dtb]
 type=SparcTLB
@@ -91,7 +91,7 @@ size=64
 
 [system.cpu0.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -112,7 +112,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
 
 [system.cpu0.interrupts]
 type=SparcInterrupts
@@ -154,6 +154,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu1.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu1.interrupts
@@ -177,7 +178,7 @@ icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -198,7 +199,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[4]
+mem_side=system.toL2Bus.slave[3]
 
 [system.cpu1.dtb]
 type=SparcTLB
@@ -206,7 +207,7 @@ size=64
 
 [system.cpu1.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -227,7 +228,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[3]
+mem_side=system.toL2Bus.slave[2]
 
 [system.cpu1.interrupts]
 type=SparcInterrupts
@@ -250,6 +251,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu2.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu2.interrupts
@@ -273,7 +275,7 @@ icache_port=system.cpu2.icache.cpu_side
 
 [system.cpu2.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -294,7 +296,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
-mem_side=system.toL2Bus.port[6]
+mem_side=system.toL2Bus.slave[5]
 
 [system.cpu2.dtb]
 type=SparcTLB
@@ -302,7 +304,7 @@ size=64
 
 [system.cpu2.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -323,7 +325,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
-mem_side=system.toL2Bus.port[5]
+mem_side=system.toL2Bus.slave[4]
 
 [system.cpu2.interrupts]
 type=SparcInterrupts
@@ -346,6 +348,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu3.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu3.interrupts
@@ -369,7 +372,7 @@ icache_port=system.cpu3.icache.cpu_side
 
 [system.cpu3.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -390,7 +393,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
-mem_side=system.toL2Bus.port[8]
+mem_side=system.toL2Bus.slave[7]
 
 [system.cpu3.dtb]
 type=SparcTLB
@@ -398,7 +401,7 @@ size=64
 
 [system.cpu3.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -419,7 +422,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
-mem_side=system.toL2Bus.port[7]
+mem_side=system.toL2Bus.slave[6]
 
 [system.cpu3.interrupts]
 type=SparcInterrupts
@@ -433,7 +436,7 @@ type=ExeTracer
 
 [system.l2c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
 forward_snoops=true
@@ -453,8 +456,8 @@ tgts_per_mshr=16
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[0]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[0]
 
 [system.membus]
 type=Bus
@@ -464,17 +467,20 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.mem_side system.physmem.port[0] system.system_port
+master=system.physmem.port[0]
+slave=system.l2c.mem_side system.system_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:1073741823
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
 [system.toL2Bus]
 type=Bus
@@ -484,5 +490,6 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
index 4d44fa6f6..ab456df4c 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 13:55:56
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:43:05
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 71dd904a3..e871b4c6b 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000088                       # Nu
 sim_ticks                                    87713500                       # Number of ticks simulated
 final_tick                                   87713500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1664146                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1664073                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              215483439                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1139232                       # Number of bytes of host memory used
-host_seconds                                     0.41                       # Real time elapsed on the host
+host_inst_rate                                 523852                       # Simulator instruction rate (inst/s)
+host_op_rate                                   523839                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               67834135                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1149444                       # Number of bytes of host memory used
+host_seconds                                     1.29                       # Real time elapsed on the host
 sim_insts                                      677340                       # Number of instructions simulated
 sim_ops                                        677340                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       35776                       # Number of bytes read from this memory
@@ -77,8 +77,8 @@ system.cpu0.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
@@ -130,8 +130,8 @@ system.cpu0.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks            6                       # number of writebacks
@@ -193,8 +193,8 @@ system.cpu1.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
@@ -246,8 +246,8 @@ system.cpu1.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks            1                       # number of writebacks
@@ -309,8 +309,8 @@ system.cpu2.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
@@ -362,8 +362,8 @@ system.cpu2.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.dcache.writebacks::writebacks            1                       # number of writebacks
@@ -425,8 +425,8 @@ system.cpu3.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
@@ -478,8 +478,8 @@ system.cpu3.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.dcache.writebacks::writebacks            1                       # number of writebacks
@@ -653,8 +653,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index c00589f53..7658e05d6 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[1]
+system_port=system.membus.slave[1]
 
 [system.cpu0]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
 
 [system.cpu0.dtb]
 type=SparcTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu0.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
 
 [system.cpu0.interrupts]
 type=SparcInterrupts
@@ -171,7 +170,7 @@ icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -192,7 +191,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[4]
+mem_side=system.toL2Bus.slave[3]
 
 [system.cpu1.dtb]
 type=SparcTLB
@@ -200,7 +199,7 @@ size=64
 
 [system.cpu1.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -221,7 +220,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[3]
+mem_side=system.toL2Bus.slave[2]
 
 [system.cpu1.interrupts]
 type=SparcInterrupts
@@ -264,7 +263,7 @@ icache_port=system.cpu2.icache.cpu_side
 
 [system.cpu2.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -285,7 +284,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
-mem_side=system.toL2Bus.port[6]
+mem_side=system.toL2Bus.slave[5]
 
 [system.cpu2.dtb]
 type=SparcTLB
@@ -293,7 +292,7 @@ size=64
 
 [system.cpu2.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -314,7 +313,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
-mem_side=system.toL2Bus.port[5]
+mem_side=system.toL2Bus.slave[4]
 
 [system.cpu2.interrupts]
 type=SparcInterrupts
@@ -357,7 +356,7 @@ icache_port=system.cpu3.icache.cpu_side
 
 [system.cpu3.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -378,7 +377,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
-mem_side=system.toL2Bus.port[8]
+mem_side=system.toL2Bus.slave[7]
 
 [system.cpu3.dtb]
 type=SparcTLB
@@ -386,7 +385,7 @@ size=64
 
 [system.cpu3.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -407,7 +406,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
-mem_side=system.toL2Bus.port[7]
+mem_side=system.toL2Bus.slave[6]
 
 [system.cpu3.interrupts]
 type=SparcInterrupts
@@ -421,7 +420,7 @@ type=ExeTracer
 
 [system.l2c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
 forward_snoops=true
@@ -441,8 +440,8 @@ tgts_per_mshr=16
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[0]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[0]
 
 [system.membus]
 type=Bus
@@ -452,17 +451,20 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.mem_side system.system_port system.physmem.port[0]
+master=system.physmem.port[0]
+slave=system.l2c.mem_side system.system_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[2]
+port=system.membus.master[0]
 
 [system.toL2Bus]
 type=Bus
@@ -472,5 +474,6 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
index bd048d482..bd4b2c9b4 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 13:56:07
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:43:05
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index fcff65a90..70ef2d753 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000262                       # Nu
 sim_ticks                                   262298000                       # Number of ticks simulated
 final_tick                                  262298000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1330969                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1330920                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              527074583                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221728                       # Number of bytes of host memory used
-host_seconds                                     0.50                       # Real time elapsed on the host
+host_inst_rate                                 323904                       # Simulator instruction rate (inst/s)
+host_op_rate                                   323899                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              128274037                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231956                       # Number of bytes of host memory used
+host_seconds                                     2.05                       # Real time elapsed on the host
 sim_insts                                      662307                       # Number of instructions simulated
 sim_ops                                        662307                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       36608                       # Number of bytes read from this memory
@@ -86,8 +86,8 @@ system.cpu0.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          467                       # number of ReadReq MSHR misses
@@ -172,8 +172,8 @@ system.cpu0.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks            6                       # number of writebacks
@@ -274,8 +274,8 @@ system.cpu1.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          366                       # number of ReadReq MSHR misses
@@ -360,8 +360,8 @@ system.cpu1.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks            1                       # number of writebacks
@@ -462,8 +462,8 @@ system.cpu2.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          366                       # number of ReadReq MSHR misses
@@ -548,8 +548,8 @@ system.cpu2.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.dcache.writebacks::writebacks            1                       # number of writebacks
@@ -650,8 +650,8 @@ system.cpu3.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          367                       # number of ReadReq MSHR misses
@@ -736,8 +736,8 @@ system.cpu3.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.dcache.writebacks::writebacks            1                       # number of writebacks
@@ -1008,8 +1008,8 @@ system.l2c.blocked_cycles::no_mshrs                 0                       # nu
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
index dacf2f87f..35cfc3441 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
@@ -14,9 +14,8 @@ init_param=0
 kernel=
 load_addr_mask=1099511627775
 mem_mode=timing
-memories=system.physmem system.funcmem
+memories=system.funcmem system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu0]
 type=MemTest
@@ -44,7 +43,7 @@ suppress_func_warnings=true
 sys=system
 trace_addr=0
 functional=system.funcmem.port[0]
-test=system.l1_cntrl0.sequencer.port[0]
+test=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu1]
 type=MemTest
@@ -62,7 +61,7 @@ suppress_func_warnings=true
 sys=system
 trace_addr=0
 functional=system.funcmem.port[1]
-test=system.l1_cntrl1.sequencer.port[0]
+test=system.l1_cntrl1.sequencer.slave[0]
 
 [system.cpu2]
 type=MemTest
@@ -80,7 +79,7 @@ suppress_func_warnings=true
 sys=system
 trace_addr=0
 functional=system.funcmem.port[2]
-test=system.l1_cntrl2.sequencer.port[0]
+test=system.l1_cntrl2.sequencer.slave[0]
 
 [system.cpu3]
 type=MemTest
@@ -98,7 +97,7 @@ suppress_func_warnings=true
 sys=system
 trace_addr=0
 functional=system.funcmem.port[3]
-test=system.l1_cntrl3.sequencer.port[0]
+test=system.l1_cntrl3.sequencer.slave[0]
 
 [system.cpu4]
 type=MemTest
@@ -116,7 +115,7 @@ suppress_func_warnings=true
 sys=system
 trace_addr=0
 functional=system.funcmem.port[4]
-test=system.l1_cntrl4.sequencer.port[0]
+test=system.l1_cntrl4.sequencer.slave[0]
 
 [system.cpu5]
 type=MemTest
@@ -134,7 +133,7 @@ suppress_func_warnings=true
 sys=system
 trace_addr=0
 functional=system.funcmem.port[5]
-test=system.l1_cntrl5.sequencer.port[0]
+test=system.l1_cntrl5.sequencer.slave[0]
 
 [system.cpu6]
 type=MemTest
@@ -152,7 +151,7 @@ suppress_func_warnings=true
 sys=system
 trace_addr=0
 functional=system.funcmem.port[6]
-test=system.l1_cntrl6.sequencer.port[0]
+test=system.l1_cntrl6.sequencer.slave[0]
 
 [system.cpu7]
 type=MemTest
@@ -170,7 +169,7 @@ suppress_func_warnings=true
 sys=system
 trace_addr=0
 functional=system.funcmem.port[7]
-test=system.l1_cntrl7.sequencer.port[0]
+test=system.l1_cntrl7.sequencer.slave[0]
 
 [system.dir_cntrl0]
 type=Directory_Controller
@@ -191,7 +190,7 @@ version=0
 type=RubyDirectoryMemory
 map_levels=4
 numa_high_bit=6
-size=134217728
+size=268435456
 use_map=false
 version=0
 
@@ -217,8 +216,10 @@ tFaw=0
 version=0
 
 [system.funcmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=false
 latency=30
 latency_var=0
 null=false
@@ -270,13 +271,14 @@ dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu0.test
+slave=system.cpu0.test
 
 [system.l1_cntrl1]
 type=L1Cache_Controller
@@ -322,13 +324,14 @@ dcache=system.l1_cntrl1.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl1.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=1
-physMemPort=system.physmem.port[1]
-port=system.cpu1.test
+slave=system.cpu1.test
 
 [system.l1_cntrl2]
 type=L1Cache_Controller
@@ -374,13 +377,14 @@ dcache=system.l1_cntrl2.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl2.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=2
-physMemPort=system.physmem.port[2]
-port=system.cpu2.test
+slave=system.cpu2.test
 
 [system.l1_cntrl3]
 type=L1Cache_Controller
@@ -426,13 +430,14 @@ dcache=system.l1_cntrl3.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl3.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=3
-physMemPort=system.physmem.port[3]
-port=system.cpu3.test
+slave=system.cpu3.test
 
 [system.l1_cntrl4]
 type=L1Cache_Controller
@@ -478,13 +483,14 @@ dcache=system.l1_cntrl4.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl4.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=4
-physMemPort=system.physmem.port[4]
-port=system.cpu4.test
+slave=system.cpu4.test
 
 [system.l1_cntrl5]
 type=L1Cache_Controller
@@ -530,13 +536,14 @@ dcache=system.l1_cntrl5.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl5.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=5
-physMemPort=system.physmem.port[5]
-port=system.cpu5.test
+slave=system.cpu5.test
 
 [system.l1_cntrl6]
 type=L1Cache_Controller
@@ -582,13 +589,14 @@ dcache=system.l1_cntrl6.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl6.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=6
-physMemPort=system.physmem.port[6]
-port=system.cpu6.test
+slave=system.cpu6.test
 
 [system.l1_cntrl7]
 type=L1Cache_Controller
@@ -634,13 +642,14 @@ dcache=system.l1_cntrl7.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl7.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=7
-physMemPort=system.physmem.port[7]
-port=system.cpu7.test
+slave=system.cpu7.test
 
 [system.l2_cntrl0]
 type=L2Cache_Controller
@@ -667,21 +676,22 @@ size=512
 start_index_bit=6
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
 children=network profiler
 block_size_bytes=64
 clock=1
-mem_size=134217728
+mem_size=268435456
 no_mem_vec=false
 random_seed=1234
 randomization=false
@@ -941,11 +951,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[8]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
index e8a51599b..b44d5a4c2 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
@@ -7,8 +7,8 @@ RubySystem config:
   cycle_period: 1
   block_size_bytes: 64
   block_size_bits: 6
-  memory_size_bytes: 134217728
-  memory_size_bits: 27
+  memory_size_bytes: 268435456
+  memory_size_bits: 28
 
 Network Configuration
 ---------------------
@@ -34,26 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/12/2012 15:36:31
+Real time: May/08/2012 15:38:27
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 190
-Elapsed_time_in_minutes: 3.16667
-Elapsed_time_in_hours: 0.0527778
-Elapsed_time_in_days: 0.00219907
+Elapsed_time_in_seconds: 113
+Elapsed_time_in_minutes: 1.88333
+Elapsed_time_in_hours: 0.0313889
+Elapsed_time_in_days: 0.00130787
 
-Virtual_time_in_seconds: 189.25
-Virtual_time_in_minutes: 3.15417
-Virtual_time_in_hours:   0.0525694
-Virtual_time_in_days:    0.00219039
+Virtual_time_in_seconds: 112.14
+Virtual_time_in_minutes: 1.869
+Virtual_time_in_hours:   0.03115
+Virtual_time_in_days:    0.00129792
 
 Ruby_current_time: 22495354
 Ruby_start_time: 0
 Ruby_cycles: 22495354
 
-mbytes_resident: 0
-mbytes_total: 0
+mbytes_resident: 60.2695
+mbytes_total: 361.398
+resident_ratio: 0.166768
 
 ruby_cycles_executed: [ 22495355 22495355 22495355 22495355 22495355 22495355 22495355 22495355 ]
 
@@ -115,13 +116,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 3280807 average: 0.508064 |
 Resource Usage
 --------------
 page_size: 4096
-user_time: 188
+user_time: 112
 system_time: 0
-page_reclaims: 12571
+page_reclaims: 15932
 page_faults: 0
 swaps: 0
-block_inputs: 1
-block_outputs: 44
+block_inputs: 0
+block_outputs: 232
 
 Network Stats
 -------------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
index f74c8ffd6..26548e28d 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 15:33:08
-gem5 started Feb 12 2012 15:33:21
-gem5 executing on Alis-MacBook-Pro.local
+gem5 compiled May  8 2012 15:08:30
+gem5 started May  8 2012 15:36:34
+gem5 executing on piton
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
index 1bc6a2ebb..1ae2ff15c 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
@@ -4,21 +4,21 @@ sim_seconds                                  0.022495                       # Nu
 sim_ticks                                    22495354                       # Number of ticks simulated
 final_tick                                   22495354                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 118487                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 398520                       # Number of bytes of host memory used
-host_seconds                                   189.86                       # Real time elapsed on the host
-system.physmem.bytes_read                           0                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+host_tick_rate                                 200233                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 370076                       # Number of bytes of host memory used
+host_seconds                                   112.35                       # Real time elapsed on the host
 system.funcmem.bytes_read                           0                       # Number of bytes read from this memory
 system.funcmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
 system.funcmem.bytes_written                        0                       # Number of bytes written to this memory
 system.funcmem.num_reads                            0                       # Number of read requests responded to by this memory
 system.funcmem.num_writes                           0                       # Number of write requests responded to by this memory
 system.funcmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
 system.cpu0.num_reads                           99326                       # number of read accesses completed
 system.cpu0.num_writes                          53132                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
index e0267adf3..af42ad0ff 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,15 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
-memories=system.physmem system.funcmem
+memories=system.funcmem system.physmem
 num_work_ids=16
-physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -19,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu0]
 type=MemTest
@@ -34,9 +40,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[0]
-test=system.l1_cntrl0.sequencer.port[0]
+test=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu1]
 type=MemTest
@@ -51,9 +58,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[1]
-test=system.l1_cntrl1.sequencer.port[0]
+test=system.l1_cntrl1.sequencer.slave[0]
 
 [system.cpu2]
 type=MemTest
@@ -68,9 +76,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[2]
-test=system.l1_cntrl2.sequencer.port[0]
+test=system.l1_cntrl2.sequencer.slave[0]
 
 [system.cpu3]
 type=MemTest
@@ -85,9 +94,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[3]
-test=system.l1_cntrl3.sequencer.port[0]
+test=system.l1_cntrl3.sequencer.slave[0]
 
 [system.cpu4]
 type=MemTest
@@ -102,9 +112,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[4]
-test=system.l1_cntrl4.sequencer.port[0]
+test=system.l1_cntrl4.sequencer.slave[0]
 
 [system.cpu5]
 type=MemTest
@@ -119,9 +130,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[5]
-test=system.l1_cntrl5.sequencer.port[0]
+test=system.l1_cntrl5.sequencer.slave[0]
 
 [system.cpu6]
 type=MemTest
@@ -136,9 +148,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[6]
-test=system.l1_cntrl6.sequencer.port[0]
+test=system.l1_cntrl6.sequencer.slave[0]
 
 [system.cpu7]
 type=MemTest
@@ -153,9 +166,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[7]
-test=system.l1_cntrl7.sequencer.port[0]
+test=system.l1_cntrl7.sequencer.slave[0]
 
 [system.dir_cntrl0]
 type=Directory_Controller
@@ -175,7 +189,7 @@ version=0
 type=RubyDirectoryMemory
 map_levels=4
 numa_high_bit=6
-size=134217728
+size=268435456
 use_map=false
 version=0
 
@@ -201,8 +215,10 @@ tFaw=0
 version=0
 
 [system.funcmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=false
 latency=30
 latency_var=0
 null=false
@@ -222,6 +238,7 @@ number_of_TBEs=256
 recycle_latency=10
 request_latency=2
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
@@ -251,13 +268,14 @@ dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu0.test
+slave=system.cpu0.test
 
 [system.l1_cntrl1]
 type=L1Cache_Controller
@@ -271,6 +289,7 @@ number_of_TBEs=256
 recycle_latency=10
 request_latency=2
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl1.sequencer
 transitions_per_cycle=32
 version=1
@@ -300,13 +319,14 @@ dcache=system.l1_cntrl1.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl1.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=1
-physMemPort=system.physmem.port[1]
-port=system.cpu1.test
+slave=system.cpu1.test
 
 [system.l1_cntrl2]
 type=L1Cache_Controller
@@ -320,6 +340,7 @@ number_of_TBEs=256
 recycle_latency=10
 request_latency=2
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl2.sequencer
 transitions_per_cycle=32
 version=2
@@ -349,13 +370,14 @@ dcache=system.l1_cntrl2.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl2.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=2
-physMemPort=system.physmem.port[2]
-port=system.cpu2.test
+slave=system.cpu2.test
 
 [system.l1_cntrl3]
 type=L1Cache_Controller
@@ -369,6 +391,7 @@ number_of_TBEs=256
 recycle_latency=10
 request_latency=2
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl3.sequencer
 transitions_per_cycle=32
 version=3
@@ -398,13 +421,14 @@ dcache=system.l1_cntrl3.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl3.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=3
-physMemPort=system.physmem.port[3]
-port=system.cpu3.test
+slave=system.cpu3.test
 
 [system.l1_cntrl4]
 type=L1Cache_Controller
@@ -418,6 +442,7 @@ number_of_TBEs=256
 recycle_latency=10
 request_latency=2
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl4.sequencer
 transitions_per_cycle=32
 version=4
@@ -447,13 +472,14 @@ dcache=system.l1_cntrl4.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl4.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=4
-physMemPort=system.physmem.port[4]
-port=system.cpu4.test
+slave=system.cpu4.test
 
 [system.l1_cntrl5]
 type=L1Cache_Controller
@@ -467,6 +493,7 @@ number_of_TBEs=256
 recycle_latency=10
 request_latency=2
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl5.sequencer
 transitions_per_cycle=32
 version=5
@@ -496,13 +523,14 @@ dcache=system.l1_cntrl5.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl5.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=5
-physMemPort=system.physmem.port[5]
-port=system.cpu5.test
+slave=system.cpu5.test
 
 [system.l1_cntrl6]
 type=L1Cache_Controller
@@ -516,6 +544,7 @@ number_of_TBEs=256
 recycle_latency=10
 request_latency=2
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl6.sequencer
 transitions_per_cycle=32
 version=6
@@ -545,13 +574,14 @@ dcache=system.l1_cntrl6.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl6.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=6
-physMemPort=system.physmem.port[6]
-port=system.cpu6.test
+slave=system.cpu6.test
 
 [system.l1_cntrl7]
 type=L1Cache_Controller
@@ -565,6 +595,7 @@ number_of_TBEs=256
 recycle_latency=10
 request_latency=2
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl7.sequencer
 transitions_per_cycle=32
 version=7
@@ -594,13 +625,14 @@ dcache=system.l1_cntrl7.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl7.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=7
-physMemPort=system.physmem.port[7]
-port=system.cpu7.test
+slave=system.cpu7.test
 
 [system.l2_cntrl0]
 type=L2Cache_Controller
@@ -626,21 +658,22 @@ size=512
 start_index_bit=6
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
 children=network profiler
 block_size_bytes=64
 clock=1
-mem_size=134217728
+mem_size=268435456
 no_mem_vec=false
 random_seed=1234
 randomization=false
@@ -900,11 +933,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[8]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
index 78fcf4ec9..cb3fdaf16 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
@@ -7,8 +7,8 @@ RubySystem config:
   cycle_period: 1
   block_size_bytes: 64
   block_size_bits: 6
-  memory_size_bytes: 134217728
-  memory_size_bits: 27
+  memory_size_bytes: 268435456
+  memory_size_bits: 28
 
 Network Configuration
 ---------------------
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/23/2012 04:26:05
+Real time: May/08/2012 15:42:43
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 233
-Elapsed_time_in_minutes: 3.88333
-Elapsed_time_in_hours: 0.0647222
-Elapsed_time_in_days: 0.00269676
+Elapsed_time_in_seconds: 365
+Elapsed_time_in_minutes: 6.08333
+Elapsed_time_in_hours: 0.101389
+Elapsed_time_in_days: 0.00422454
 
-Virtual_time_in_seconds: 232.61
-Virtual_time_in_minutes: 3.87683
-Virtual_time_in_hours:   0.0646139
-Virtual_time_in_days:    0.00269225
+Virtual_time_in_seconds: 361.58
+Virtual_time_in_minutes: 6.02633
+Virtual_time_in_hours:   0.100439
+Virtual_time_in_days:    0.00418495
 
 Ruby_current_time: 19400856
 Ruby_start_time: 0
 Ruby_cycles: 19400856
 
-mbytes_resident: 42.1172
-mbytes_total: 339.848
-resident_ratio: 0.12393
+mbytes_resident: 60.2344
+mbytes_total: 361.566
+resident_ratio: 0.166593
 
 ruby_cycles_executed: [ 19400857 19400857 19400857 19400857 19400857 19400857 19400857 19400857 ]
 
@@ -116,13 +116,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
 Resource Usage
 --------------
 page_size: 4096
-user_time: 232
+user_time: 361
 system_time: 0
-page_reclaims: 11111
+page_reclaims: 15956
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 192
+block_outputs: 448
 
 Network Stats
 -------------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
index b246a2d4a..403e6654c 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:47:36
-gem5 started Jan 23 2012 04:22:12
-gem5 executing on zizzer
-command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
+gem5 compiled May  8 2012 15:14:18
+gem5 started May  8 2012 15:36:38
+gem5 executing on piton
+command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 19400856 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
index ec3afa4a7..9aec04ac2 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
@@ -4,21 +4,21 @@ sim_seconds                                  0.019401                       # Nu
 sim_ticks                                    19400856                       # Number of ticks simulated
 final_tick                                   19400856                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  83409                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 348008                       # Number of bytes of host memory used
-host_seconds                                   232.60                       # Real time elapsed on the host
-system.physmem.bytes_read                           0                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+host_tick_rate                                  53186                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 370248                       # Number of bytes of host memory used
+host_seconds                                   364.77                       # Real time elapsed on the host
 system.funcmem.bytes_read                           0                       # Number of bytes read from this memory
 system.funcmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
 system.funcmem.bytes_written                        0                       # Number of bytes written to this memory
 system.funcmem.num_reads                            0                       # Number of read requests responded to by this memory
 system.funcmem.num_writes                           0                       # Number of write requests responded to by this memory
 system.funcmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
 system.cpu0.num_reads                           98844                       # number of read accesses completed
 system.cpu0.num_writes                          53478                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
index 84c75eb68..4af9d9478 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,15 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem system.funcmem
 num_work_ids=16
-physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -19,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu0]
 type=MemTest
@@ -34,9 +40,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[0]
-test=system.l1_cntrl0.sequencer.port[0]
+test=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu1]
 type=MemTest
@@ -51,9 +58,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[1]
-test=system.l1_cntrl1.sequencer.port[0]
+test=system.l1_cntrl1.sequencer.slave[0]
 
 [system.cpu2]
 type=MemTest
@@ -68,9 +76,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[2]
-test=system.l1_cntrl2.sequencer.port[0]
+test=system.l1_cntrl2.sequencer.slave[0]
 
 [system.cpu3]
 type=MemTest
@@ -85,9 +94,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[3]
-test=system.l1_cntrl3.sequencer.port[0]
+test=system.l1_cntrl3.sequencer.slave[0]
 
 [system.cpu4]
 type=MemTest
@@ -102,9 +112,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[4]
-test=system.l1_cntrl4.sequencer.port[0]
+test=system.l1_cntrl4.sequencer.slave[0]
 
 [system.cpu5]
 type=MemTest
@@ -119,9 +130,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[5]
-test=system.l1_cntrl5.sequencer.port[0]
+test=system.l1_cntrl5.sequencer.slave[0]
 
 [system.cpu6]
 type=MemTest
@@ -136,9 +148,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[6]
-test=system.l1_cntrl6.sequencer.port[0]
+test=system.l1_cntrl6.sequencer.slave[0]
 
 [system.cpu7]
 type=MemTest
@@ -153,9 +166,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[7]
-test=system.l1_cntrl7.sequencer.port[0]
+test=system.l1_cntrl7.sequencer.slave[0]
 
 [system.dir_cntrl0]
 type=Directory_Controller
@@ -178,7 +192,7 @@ version=0
 type=RubyDirectoryMemory
 map_levels=4
 numa_high_bit=6
-size=134217728
+size=268435456
 use_map=false
 version=0
 
@@ -204,8 +218,10 @@ tFaw=0
 version=0
 
 [system.funcmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=false
 latency=30
 latency_var=0
 null=false
@@ -231,6 +247,7 @@ number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
@@ -260,13 +277,14 @@ dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu0.test
+slave=system.cpu0.test
 
 [system.l1_cntrl1]
 type=L1Cache_Controller
@@ -286,6 +304,7 @@ number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl1.sequencer
 transitions_per_cycle=32
 version=1
@@ -315,13 +334,14 @@ dcache=system.l1_cntrl1.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl1.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=1
-physMemPort=system.physmem.port[1]
-port=system.cpu1.test
+slave=system.cpu1.test
 
 [system.l1_cntrl2]
 type=L1Cache_Controller
@@ -341,6 +361,7 @@ number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl2.sequencer
 transitions_per_cycle=32
 version=2
@@ -370,13 +391,14 @@ dcache=system.l1_cntrl2.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl2.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=2
-physMemPort=system.physmem.port[2]
-port=system.cpu2.test
+slave=system.cpu2.test
 
 [system.l1_cntrl3]
 type=L1Cache_Controller
@@ -396,6 +418,7 @@ number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl3.sequencer
 transitions_per_cycle=32
 version=3
@@ -425,13 +448,14 @@ dcache=system.l1_cntrl3.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl3.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=3
-physMemPort=system.physmem.port[3]
-port=system.cpu3.test
+slave=system.cpu3.test
 
 [system.l1_cntrl4]
 type=L1Cache_Controller
@@ -451,6 +475,7 @@ number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl4.sequencer
 transitions_per_cycle=32
 version=4
@@ -480,13 +505,14 @@ dcache=system.l1_cntrl4.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl4.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=4
-physMemPort=system.physmem.port[4]
-port=system.cpu4.test
+slave=system.cpu4.test
 
 [system.l1_cntrl5]
 type=L1Cache_Controller
@@ -506,6 +532,7 @@ number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl5.sequencer
 transitions_per_cycle=32
 version=5
@@ -535,13 +562,14 @@ dcache=system.l1_cntrl5.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl5.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=5
-physMemPort=system.physmem.port[5]
-port=system.cpu5.test
+slave=system.cpu5.test
 
 [system.l1_cntrl6]
 type=L1Cache_Controller
@@ -561,6 +589,7 @@ number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl6.sequencer
 transitions_per_cycle=32
 version=6
@@ -590,13 +619,14 @@ dcache=system.l1_cntrl6.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl6.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=6
-physMemPort=system.physmem.port[6]
-port=system.cpu6.test
+slave=system.cpu6.test
 
 [system.l1_cntrl7]
 type=L1Cache_Controller
@@ -616,6 +646,7 @@ number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl7.sequencer
 transitions_per_cycle=32
 version=7
@@ -645,13 +676,14 @@ dcache=system.l1_cntrl7.L1DcacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl7.L1IcacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=7
-physMemPort=system.physmem.port[7]
-port=system.cpu7.test
+slave=system.cpu7.test
 
 [system.l2_cntrl0]
 type=L2Cache_Controller
@@ -679,21 +711,22 @@ size=512
 start_index_bit=6
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
 children=network profiler
 block_size_bytes=64
 clock=1
-mem_size=134217728
+mem_size=268435456
 no_mem_vec=false
 random_seed=1234
 randomization=false
@@ -953,11 +986,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[8]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
index 5b7a6fff2..ab5cb8e9e 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
@@ -7,8 +7,8 @@ RubySystem config:
   cycle_period: 1
   block_size_bytes: 64
   block_size_bits: 6
-  memory_size_bytes: 134217728
-  memory_size_bits: 27
+  memory_size_bytes: 268435456
+  memory_size_bits: 28
 
 Network Configuration
 ---------------------
@@ -34,29 +34,29 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/23/2012 04:24:27
+Real time: May/08/2012 15:39:26
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 120
-Elapsed_time_in_minutes: 2
-Elapsed_time_in_hours: 0.0333333
-Elapsed_time_in_days: 0.00138889
+Elapsed_time_in_seconds: 164
+Elapsed_time_in_minutes: 2.73333
+Elapsed_time_in_hours: 0.0455556
+Elapsed_time_in_days: 0.00189815
 
-Virtual_time_in_seconds: 119.35
-Virtual_time_in_minutes: 1.98917
-Virtual_time_in_hours:   0.0331528
-Virtual_time_in_days:    0.00138137
+Virtual_time_in_seconds: 163.7
+Virtual_time_in_minutes: 2.72833
+Virtual_time_in_hours:   0.0454722
+Virtual_time_in_days:    0.00189468
 
-Ruby_current_time: 19658320
+Ruby_current_time: 19665440
 Ruby_start_time: 0
-Ruby_cycles: 19658320
+Ruby_cycles: 19665440
 
-mbytes_resident: 41.6445
-mbytes_total: 339.402
-resident_ratio: 0.1227
+mbytes_resident: 60.0117
+mbytes_total: 361.082
+resident_ratio: 0.1662
 
-ruby_cycles_executed: [ 19658321 19658321 19658321 19658321 19658321 19658321 19658321 19658321 ]
+ruby_cycles_executed: [ 19665441 19665441 19665441 19665441 19665441 19665441 19665441 19665441 ]
 
 Busy Controller Counts:
 L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
@@ -67,35 +67,35 @@ Directory-0:0
 
 Busy Bank Count:0
 
-sequencer_requests_outstanding: [binsize: 1 max: 16 count: 615732 average: 15.9984 | standard deviation: 0.126922 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 615612 ]
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 615791 average: 15.9984 | standard deviation: 0.126916 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 615671 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 128 max: 18520 count: 615604 average: 4086.79 | standard deviation: 2944.53 | 596 6466 13264 14393 14238 17364 19534 19886 17213 15228 16326 15266 13085 12364 11235 10730 9475 9043 9065 7719 7748 7559 7862 7157 6552 7013 7074 6670 6771 6341 6912 6682 6584 6902 6301 6596 6654 7004 6743 6175 6952 7090 6725 6856 6582 7347 7091 7151 7379 6597 7114 7104 7285 7020 6346 6929 7026 6665 6372 5841 6151 5725 5614 5684 4803 4921 4577 4608 4096 3343 3553 3445 3118 2793 2470 2458 2157 1968 1839 1509 1491 1372 1275 1092 889 849 861 678 630 504 509 471 398 313 303 221 231 191 167 128 129 109 96 89 84 52 62 53 45 29 26 20 18 23 14 13 16 6 7 4 4 2 4 5 2 9 0 1 1 1 1 3 0 0 1 2 1 1 1 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 128 max: 18520 count: 399925 average: 4085.78 | standard deviation: 2943.7 | 411 4241 8744 9371 9204 11299 12636 12913 11096 9899 10485 9918 8546 8048 7413 6933 6133 5806 5894 5034 5021 4872 5059 4679 4204 4555 4577 4358 4446 4076 4496 4395 4244 4508 4111 4303 4337 4576 4392 4020 4619 4630 4439 4337 4254 4804 4601 4590 4875 4227 4658 4573 4693 4557 4183 4441 4623 4325 4101 3776 4035 3686 3683 3683 3151 3218 2947 2959 2688 2200 2281 2233 2025 1848 1629 1589 1388 1243 1160 970 972 871 848 711 556 548 549 449 405 310 346 306 262 198 204 135 149 121 104 87 86 72 63 58 50 38 42 37 28 20 18 15 13 15 9 6 10 2 6 3 2 1 3 5 1 5 0 1 0 1 1 1 0 0 1 2 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 128 max: 17820 count: 215679 average: 4088.66 | standard deviation: 2946.1 | 185 2225 4520 5022 5034 6065 6898 6973 6117 5329 5841 5348 4539 4316 3822 3797 3342 3237 3171 2685 2727 2687 2803 2478 2348 2458 2497 2312 2325 2265 2416 2287 2340 2394 2190 2293 2317 2428 2351 2155 2333 2460 2286 2519 2328 2543 2490 2561 2504 2370 2456 2531 2592 2463 2163 2488 2403 2340 2271 2065 2116 2039 1931 2001 1652 1703 1630 1649 1408 1143 1272 1212 1093 945 841 869 769 725 679 539 519 501 427 381 333 301 312 229 225 194 163 165 136 115 99 86 82 70 63 41 43 37 33 31 34 14 20 16 17 9 8 5 5 8 5 7 6 4 1 1 2 1 1 0 1 4 0 0 1 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache: [binsize: 1 max: 2 count: 131 average:     2 | standard deviation: 0 | 0 0 131 ]
-miss_latency_L2Cache: [binsize: 128 max: 14875 count: 3746 average: 4024.34 | standard deviation: 3007.93 | 204 55 53 50 42 111 96 107 106 79 69 84 62 70 71 76 59 59 55 55 58 40 43 38 30 44 37 43 40 53 30 50 48 39 29 37 48 40 46 46 43 40 28 35 34 39 49 48 51 43 34 37 48 27 33 46 34 50 49 30 39 41 26 40 24 29 21 28 21 31 25 22 18 19 12 31 12 10 13 4 10 8 7 2 5 14 4 4 0 5 1 3 2 0 0 4 1 2 0 1 2 0 1 0 1 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Directory: [binsize: 128 max: 18520 count: 608513 average: 4090.49 | standard deviation: 2943.6 | 1 6328 13141 14257 14115 17140 19369 19675 17048 15093 16201 15110 12979 12234 11111 10605 9373 8948 8977 7617 7656 7477 7782 7092 6496 6928 6991 6601 6695 6251 6849 6600 6501 6828 6238 6511 6574 6914 6666 6091 6877 7011 6655 6787 6509 7277 7011 7063 7302 6516 7046 7036 7198 6971 6282 6863 6968 6580 6295 5779 6080 5663 5553 5625 4758 4866 4542 4559 4058 3292 3511 3409 3088 2765 2450 2423 2138 1954 1818 1495 1479 1357 1264 1084 879 829 853 671 630 497 506 467 396 312 301 217 229 189 166 127 126 108 95 89 83 52 59 53 44 28 26 20 18 23 14 13 15 5 7 4 4 2 4 5 2 9 0 1 1 1 1 3 0 0 1 2 1 1 1 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache_wCC: [binsize: 128 max: 15052 count: 3214 average: 3625.44 | standard deviation: 2955.6 | 260 83 70 86 81 113 69 104 59 56 56 72 44 60 53 49 43 36 33 47 34 42 37 27 26 41 46 26 36 37 33 32 35 35 34 48 32 50 31 38 32 39 42 34 39 31 31 40 26 38 34 31 39 22 31 20 24 35 28 32 32 21 35 19 21 26 14 21 17 20 17 14 12 9 8 4 7 4 8 10 2 7 4 6 5 6 4 3 0 2 2 1 0 1 2 0 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 128 max: 17950 count: 615663 average: 4087.9 | standard deviation: 2956.06 | 623 6672 13560 14818 14265 17966 19787 19525 17351 15783 16469 15505 13071 12320 10871 10722 9526 9130 8887 7565 7667 7466 7531 7035 6354 6785 6935 6505 6586 6197 6688 6288 6356 6714 5904 6537 6481 6912 6526 6034 6775 7081 6913 6760 6410 7338 6903 6984 7337 6740 7182 7215 7632 7074 6418 7159 7114 6737 6491 6024 6332 6004 5733 5688 4797 5051 4642 4682 4143 3530 3610 3411 3200 2859 2550 2444 2181 1984 1892 1560 1505 1322 1318 1079 894 847 816 664 565 542 483 377 337 330 279 261 213 201 124 131 124 110 84 81 66 54 56 46 35 30 30 26 23 19 17 15 11 7 6 5 9 9 2 2 3 2 1 1 0 1 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 128 max: 17950 count: 399929 average: 4087.58 | standard deviation: 2957.17 | 427 4346 8825 9550 9296 11679 12873 12593 11401 10212 10707 10147 8404 8073 7003 6964 6161 5868 5801 4897 4955 4924 4917 4586 4142 4464 4604 4193 4274 3952 4333 4116 4068 4378 3852 4207 4233 4508 4295 3961 4411 4535 4480 4361 4179 4757 4439 4506 4744 4400 4603 4692 4979 4557 4111 4623 4589 4415 4237 3907 4062 3885 3692 3767 3150 3284 2995 3038 2750 2299 2388 2194 2087 1839 1653 1583 1436 1307 1186 1037 994 869 861 691 593 539 560 428 376 343 295 247 213 228 183 160 141 135 75 92 76 69 49 47 48 30 35 26 24 18 20 18 12 17 9 11 7 7 6 4 5 8 2 2 3 2 0 1 0 1 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 128 max: 16140 count: 215734 average: 4088.48 | standard deviation: 2954.01 | 196 2326 4735 5268 4969 6287 6914 6932 5950 5571 5762 5358 4667 4247 3868 3758 3365 3262 3086 2668 2712 2542 2614 2449 2212 2321 2331 2312 2312 2245 2355 2172 2288 2336 2052 2330 2248 2404 2231 2073 2364 2546 2433 2399 2231 2581 2464 2478 2593 2340 2579 2523 2653 2517 2307 2536 2525 2322 2254 2117 2270 2119 2041 1921 1647 1767 1647 1644 1393 1231 1222 1217 1113 1020 897 861 745 677 706 523 511 453 457 388 301 308 256 236 189 199 188 130 124 102 96 101 72 66 49 39 48 41 35 34 18 24 21 20 11 12 10 8 11 2 8 4 4 0 0 1 4 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache: [binsize: 1 max: 2 count: 160 average:     2 | standard deviation: 0 | 0 0 160 ]
+miss_latency_L2Cache: [binsize: 128 max: 14287 count: 3749 average: 4006.09 | standard deviation: 3008.68 | 182 57 48 68 52 141 103 85 85 85 92 86 77 80 65 61 63 55 45 46 49 46 48 53 39 33 48 40 33 48 39 30 30 32 48 36 24 35 33 37 37 41 53 39 34 41 53 47 50 35 39 43 54 42 41 57 36 33 48 63 36 33 33 35 25 31 22 26 25 15 24 19 16 16 14 15 9 11 11 8 6 12 4 7 6 5 5 3 4 5 1 1 3 4 2 1 1 1 2 0 0 2 0 0 3 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Directory: [binsize: 128 max: 17950 count: 608537 average: 4091.83 | standard deviation: 2954.99 | 0 6545 13426 14647 14125 17700 19605 19380 17190 15625 16326 15351 12950 12192 10777 10598 9431 9049 8802 7478 7578 7387 7449 6948 6294 6721 6849 6431 6520 6110 6613 6225 6297 6648 5830 6473 6424 6847 6457 5970 6698 7009 6819 6700 6339 7258 6804 6902 7258 6665 7098 7139 7542 7010 6328 7074 7054 6671 6409 5933 6261 5945 5672 5631 4740 4993 4601 4639 4096 3494 3574 3375 3173 2833 2526 2418 2163 1954 1877 1545 1492 1309 1308 1069 886 842 809 658 559 536 482 374 334 325 277 260 210 199 121 131 124 107 84 81 63 54 56 45 35 29 29 25 23 19 17 15 11 7 6 5 9 9 2 2 3 2 1 1 0 1 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache_wCC: [binsize: 128 max: 13052 count: 3217 average: 3643.18 | standard deviation: 2994.23 | 281 70 86 103 88 125 79 60 76 73 51 68 44 48 29 63 32 26 40 41 40 33 34 34 21 31 38 34 33 39 36 33 29 34 26 28 33 30 36 27 40 31 41 21 37 39 46 35 29 40 45 33 36 22 49 28 24 33 34 28 35 26 28 22 32 27 19 17 22 21 12 17 11 10 10 11 9 19 4 7 7 1 6 3 2 0 2 3 2 1 0 2 0 1 0 0 2 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-imcomplete_wCC_Times: 3214
+imcomplete_wCC_Times: 3217
 miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 7 average:     0 | standard deviation: 0 | 7 ]
 miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 7 average:     0 | standard deviation: 0 | 7 ]
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 7 average:     0 | standard deviation: 0 | 7 ]
 miss_latency_dir_first_response_to_completion: [binsize: 4 max: 559 count: 7 average:   349 | standard deviation: 173.877 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-imcomplete_dir_Times: 608506
-miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 86 average:     2 | standard deviation: 0 | 0 0 86 ]
-miss_latency_LD_L2Cache: [binsize: 128 max: 14875 count: 2363 average: 3952.27 | standard deviation: 3021.97 | 138 36 38 38 21 71 69 68 68 51 47 56 34 47 47 50 35 39 35 34 38 21 26 23 18 22 23 28 23 30 17 34 30 26 12 16 26 34 31 31 28 25 23 30 23 23 29 25 31 27 17 21 34 13 22 28 18 31 27 21 21 20 18 26 15 20 11 15 13 22 18 12 14 13 6 13 7 7 8 4 7 7 7 1 3 8 2 2 0 2 1 2 2 0 0 1 1 1 0 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD_Directory: [binsize: 128 max: 18520 count: 395348 average: 4090.03 | standard deviation: 2942.49 | 0 4146 8658 9278 9133 11157 12522 12773 10991 9808 10400 9813 8481 7963 7331 6853 6072 5743 5837 4969 4966 4821 5007 4640 4165 4510 4530 4311 4405 4020 4459 4342 4193 4458 4075 4256 4288 4508 4339 3960 4567 4580 4387 4287 4204 4758 4553 4542 4825 4173 4616 4533 4635 4531 4144 4401 4590 4272 4051 3734 3993 3654 3641 3648 3123 3177 2928 2929 2667 2166 2255 2210 2001 1827 1620 1572 1377 1232 1146 961 963 859 838 707 549 536 544 445 405 306 343 303 260 197 202 134 147 120 103 86 84 72 62 58 49 38 40 37 27 19 18 15 13 15 9 6 9 2 6 3 2 1 3 5 1 5 0 1 0 1 1 1 0 0 1 2 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 13969 count: 2128 average: 3610.63 | standard deviation: 2983.96 | 187 59 48 55 50 71 45 72 37 40 38 49 31 38 35 30 26 24 22 31 17 30 26 16 21 23 24 19 18 26 20 19 21 24 24 31 23 34 22 29 24 25 29 20 27 23 19 23 19 27 25 19 24 13 17 12 15 22 23 21 21 12 24 9 13 21 8 15 8 12 8 11 10 8 3 4 4 4 6 5 2 5 3 3 4 4 3 2 0 2 2 1 0 1 2 0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 45 average:     2 | standard deviation: 0 | 0 0 45 ]
-miss_latency_ST_L2Cache: [binsize: 128 max: 13576 count: 1383 average: 4147.49 | standard deviation: 2980.85 | 66 19 15 12 21 40 27 39 38 28 22 28 28 23 24 26 24 20 20 21 20 19 17 15 12 22 14 15 17 23 13 16 18 13 17 21 22 6 15 15 15 15 5 5 11 16 20 23 20 16 17 16 14 14 11 18 16 19 22 9 18 21 8 14 9 9 10 13 8 9 7 10 4 6 6 18 5 3 5 0 3 1 0 1 2 6 2 2 0 3 0 1 0 0 0 3 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_Directory: [binsize: 128 max: 17820 count: 213165 average: 4091.35 | standard deviation: 2945.66 | 1 2182 4483 4979 4982 5983 6847 6902 6057 5285 5801 5297 4498 4271 3780 3752 3301 3205 3140 2648 2690 2656 2775 2452 2331 2418 2461 2290 2290 2231 2390 2258 2308 2370 2163 2255 2286 2406 2327 2131 2310 2431 2268 2500 2305 2519 2458 2521 2477 2343 2430 2503 2563 2440 2138 2462 2378 2308 2244 2045 2087 2009 1912 1977 1635 1689 1614 1630 1391 1126 1256 1199 1087 938 830 851 761 722 672 534 516 498 426 377 330 293 309 226 225 191 163 164 136 115 99 83 82 69 63 41 42 36 33 31 34 14 19 16 17 9 8 5 5 8 5 7 6 3 1 1 2 1 1 0 1 4 0 0 1 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 15052 count: 1086 average: 3654.46 | standard deviation: 2900.39 | 73 24 22 31 31 42 24 32 22 16 18 23 13 22 18 19 17 12 11 16 17 12 11 11 5 18 22 7 18 11 13 13 14 11 10 17 9 16 9 9 8 14 13 14 12 8 12 17 7 11 9 12 15 9 14 8 9 13 5 11 11 9 11 10 8 5 6 6 9 8 9 3 2 1 5 0 3 0 2 5 0 2 1 3 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+imcomplete_dir_Times: 608530
+miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 104 average:     2 | standard deviation: 0 | 0 0 104 ]
+miss_latency_LD_L2Cache: [binsize: 128 max: 14136 count: 2421 average: 3972.56 | standard deviation: 2987.64 | 126 34 28 45 27 90 74 53 57 58 58 58 52 47 37 42 41 39 30 31 32 26 30 28 29 21 35 24 21 35 31 17 20 20 34 21 14 26 23 21 24 32 30 26 21 27 35 29 25 24 24 29 35 24 25 40 26 16 31 42 25 17 24 26 17 23 12 16 13 8 15 14 10 10 7 10 6 8 7 6 5 7 2 1 4 4 3 2 1 4 0 0 2 3 1 0 0 1 1 0 0 1 0 0 2 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_Directory: [binsize: 128 max: 17950 count: 395321 average: 4091.73 | standard deviation: 2956.13 | 0 4268 8739 9438 9215 11511 12748 12502 11295 10108 10609 10045 8324 7999 6946 6889 6101 5816 5746 4843 4896 4877 4863 4536 4101 4421 4544 4145 4236 3888 4283 4080 4032 4335 3797 4165 4196 4464 4244 3919 4359 4483 4421 4323 4131 4704 4374 4456 4701 4351 4553 4645 4920 4520 4057 4569 4546 4379 4184 3847 4019 3852 3648 3726 3116 3245 2966 3012 2721 2278 2364 2167 2067 1823 1637 1567 1424 1288 1179 1025 984 861 855 688 587 535 555 424 373 338 295 245 211 225 182 160 139 134 73 92 76 68 49 47 46 30 35 25 24 17 19 18 12 17 9 11 7 7 6 4 5 8 2 2 3 2 0 1 0 1 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache_wCC: [binsize: 64 max: 12658 count: 2083 average: 3638.66 | standard deviation: 3014.99 | 138 59 33 11 24 34 33 34 35 19 40 38 20 31 19 19 26 23 22 24 20 20 19 25 12 16 19 8 13 7 21 12 14 5 8 5 12 13 13 10 12 15 9 12 12 12 13 9 5 7 10 12 9 16 9 15 9 8 18 11 10 9 8 11 9 7 15 8 10 11 15 6 13 10 9 9 13 15 10 11 14 14 6 14 11 18 4 8 12 15 15 11 23 7 10 11 7 11 12 13 14 12 9 9 10 14 6 7 15 14 9 5 9 8 6 14 11 11 10 8 10 8 8 8 10 10 4 11 7 10 9 7 6 11 4 6 8 8 10 3 5 4 3 10 4 6 3 3 4 5 4 2 2 4 5 6 0 0 2 4 3 2 0 1 3 1 0 2 0 2 0 0 0 2 0 2 0 2 1 0 0 0 0 2 0 0 0 0 0 0 0 0 1 1 0 0 0 1 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 56 average:     2 | standard deviation: 0 | 0 0 56 ]
+miss_latency_ST_L2Cache: [binsize: 128 max: 14287 count: 1328 average: 4067.22 | standard deviation: 3046.85 | 56 23 20 23 25 51 29 32 28 27 34 28 25 33 28 19 22 16 15 15 17 20 18 25 10 12 13 16 12 13 8 13 10 12 14 15 10 9 10 16 13 9 23 13 13 14 18 18 25 11 15 14 19 18 16 17 10 17 17 21 11 16 9 9 8 8 10 10 12 7 9 5 6 6 7 5 3 3 4 2 1 5 2 6 2 1 2 1 3 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_Directory: [binsize: 128 max: 16140 count: 213216 average: 4092.01 | standard deviation: 2952.9 | 0 2277 4687 5209 4910 6189 6857 6878 5895 5517 5717 5306 4626 4193 3831 3709 3330 3233 3056 2635 2682 2510 2586 2412 2193 2300 2305 2286 2284 2222 2330 2145 2265 2313 2033 2308 2228 2383 2213 2051 2339 2526 2398 2377 2208 2554 2430 2446 2557 2314 2545 2494 2622 2490 2271 2505 2508 2292 2225 2086 2242 2093 2024 1905 1624 1748 1635 1627 1375 1216 1210 1208 1106 1010 889 851 739 666 698 520 508 448 453 381 299 307 254 234 186 198 187 129 123 100 95 100 71 65 48 39 48 39 35 34 17 24 21 20 11 12 10 7 11 2 8 4 4 0 0 1 4 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 13052 count: 1134 average: 3651.49 | standard deviation: 2957.03 | 84 26 28 36 34 47 28 22 27 27 11 24 16 21 9 30 13 13 15 18 13 12 10 12 9 9 13 10 16 10 17 14 13 11 5 7 10 12 8 6 12 11 12 9 10 13 16 14 11 15 19 15 12 9 20 14 7 13 12 10 17 10 8 7 15 11 2 7 6 8 3 4 1 4 1 5 3 8 4 1 2 0 2 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -125,307 +125,301 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
 Resource Usage
 --------------
 page_size: 4096
-user_time: 119
+user_time: 163
 system_time: 0
-page_reclaims: 10999
+page_reclaims: 15846
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 208
+block_outputs: 288
 
 Network Stats
 -------------
 
-total_msg_count_Request_Control: 3688391 29507128
-total_msg_count_Response_Data: 1832355 131929560
-total_msg_count_ResponseL2hit_Data: 4578 329616
-total_msg_count_ResponseLocal_Data: 6687 481464
-total_msg_count_Response_Control: 5517 44136
-total_msg_count_Writeback_Data: 2490666 179327952
-total_msg_count_Writeback_Control: 1184091 9472728
-total_msg_count_Broadcast_Control: 9232425 73859400
-total_msg_count_Persistent_Control: 8208600 65668800
-total_msgs: 26653310 total_bytes: 490620784
+total_msg_count_Request_Control: 3688605 29508840
+total_msg_count_Response_Data: 1832376 131931072
+total_msg_count_ResponseL2hit_Data: 4557 328104
+total_msg_count_ResponseLocal_Data: 6807 490104
+total_msg_count_Response_Control: 5775 46200
+total_msg_count_Writeback_Data: 2490786 179336592
+total_msg_count_Writeback_Control: 1183890 9471120
+total_msg_count_Broadcast_Control: 9232905 73863240
+total_msg_count_Persistent_Control: 8183920 65471360
+total_msgs: 26629621 total_bytes: 490446632
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 3.2394
-  links_utilized_percent_switch_0_link_0: 4.18174 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 2.29707 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_0_link_0_Response_Data: 76720 5523840 [ 0 0 0 0 76720 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 204 14688 [ 0 0 0 0 204 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_ResponseLocal_Data: 259 18648 [ 0 0 0 0 259 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Data: 82 5904 [ 0 0 0 0 82 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Broadcast_Control: 538306 4306448 [ 0 538306 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Request_Control: 77189 617512 [ 0 77189 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Data: 124 8928 [ 0 0 0 0 124 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_ResponseLocal_Data: 286 20592 [ 0 0 0 0 286 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Control: 226 1808 [ 0 0 0 0 226 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Data: 77037 5546664 [ 0 0 0 0 77037 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Broadcast_Control: 77189 617512 [ 0 77189 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Persistent_Control: 51505 412040 [ 0 0 0 51505 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_0: 3.24081
+  links_utilized_percent_switch_0_link_0: 4.18124 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 2.30038 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_0_link_0_Response_Data: 76922 5538384 [ 0 0 0 0 76922 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 186 13392 [ 0 0 0 0 186 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_ResponseLocal_Data: 277 19944 [ 0 0 0 0 277 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Data: 80 5760 [ 0 0 0 0 80 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Broadcast_Control: 538135 4305080 [ 0 538135 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Request_Control: 77392 619136 [ 0 77392 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 120 8640 [ 0 0 0 0 120 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_ResponseLocal_Data: 281 20232 [ 0 0 0 0 281 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Control: 254 2032 [ 0 0 0 0 254 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Data: 77209 5559048 [ 0 0 0 0 77209 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Broadcast_Control: 77392 619136 [ 0 77392 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Persistent_Control: 51231 409848 [ 0 0 0 51231 0 0 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 3.23446
-  links_utilized_percent_switch_1_link_0: 4.17797 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 2.29095 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_1_link_0_Response_Data: 76500 5508000 [ 0 0 0 0 76500 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 196 14112 [ 0 0 0 0 196 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_ResponseLocal_Data: 276 19872 [ 0 0 0 0 276 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Writeback_Data: 109 7848 [ 0 0 0 0 109 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Broadcast_Control: 538478 4307824 [ 0 538478 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Request_Control: 77017 616136 [ 0 77017 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 132 9504 [ 0 0 0 0 132 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_ResponseLocal_Data: 292 21024 [ 0 0 0 0 292 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Control: 247 1976 [ 0 0 0 0 247 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Data: 76832 5531904 [ 0 0 0 0 76832 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Broadcast_Control: 77017 616136 [ 0 77017 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Persistent_Control: 51141 409128 [ 0 0 0 51141 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_1: 3.23201
+  links_utilized_percent_switch_1_link_0: 4.17377 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 2.29025 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_1_link_0_Response_Data: 76476 5506272 [ 0 0 0 0 76476 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 187 13464 [ 0 0 0 0 187 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_ResponseLocal_Data: 309 22248 [ 0 0 0 0 309 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Writeback_Data: 126 9072 [ 0 0 0 0 126 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Broadcast_Control: 538503 4308024 [ 0 538503 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Request_Control: 77024 616192 [ 0 77024 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 122 8784 [ 0 0 0 0 122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_ResponseLocal_Data: 305 21960 [ 0 0 0 0 305 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Control: 253 2024 [ 0 0 0 0 253 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Data: 76843 5532696 [ 0 0 0 0 76843 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Broadcast_Control: 77024 616192 [ 0 77024 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Persistent_Control: 51043 408344 [ 0 0 0 51043 0 0 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 3.2337
-  links_utilized_percent_switch_2_link_0: 4.17711 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 2.29029 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_2_link_0_Response_Data: 76476 5506272 [ 0 0 0 0 76476 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_ResponseL2hit_Data: 191 13752 [ 0 0 0 0 191 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_ResponseLocal_Data: 247 17784 [ 0 0 0 0 247 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Data: 126 9072 [ 0 0 0 0 126 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Broadcast_Control: 538509 4308072 [ 0 538509 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Request_Control: 76986 615888 [ 0 76986 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Data: 118 8496 [ 0 0 0 0 118 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_ResponseLocal_Data: 273 19656 [ 0 0 0 0 273 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Control: 240 1920 [ 0 0 0 0 240 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Writeback_Data: 76800 5529600 [ 0 0 0 0 76800 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Broadcast_Control: 76986 615888 [ 0 76986 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Persistent_Control: 51535 412280 [ 0 0 0 51535 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_2: 3.22381
+  links_utilized_percent_switch_2_link_0: 4.16688 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 2.28074 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_2_link_0_Response_Data: 76167 5484024 [ 0 0 0 0 76167 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_ResponseL2hit_Data: 178 12816 [ 0 0 0 0 178 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_ResponseLocal_Data: 282 20304 [ 0 0 0 0 282 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Data: 133 9576 [ 0 0 0 0 133 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Broadcast_Control: 538834 4310672 [ 0 538834 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Request_Control: 76693 613544 [ 0 76693 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Data: 129 9288 [ 0 0 0 0 129 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_ResponseLocal_Data: 299 21528 [ 0 0 0 0 299 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Control: 255 2040 [ 0 0 0 0 255 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Data: 76504 5508288 [ 0 0 0 0 76504 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Broadcast_Control: 76693 613544 [ 0 76693 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Persistent_Control: 51008 408064 [ 0 0 0 51008 0 0 0 0 0 0 ] base_latency: 1
 
 switch_3_inlinks: 2
 switch_3_outlinks: 2
-links_utilized_percent_switch_3: 3.24065
-  links_utilized_percent_switch_3_link_0: 4.18288 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_3_link_1: 2.29842 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_3_link_0_Response_Data: 76703 5522616 [ 0 0 0 0 76703 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 171 12312 [ 0 0 0 0 171 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_ResponseLocal_Data: 265 19080 [ 0 0 0 0 265 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Writeback_Data: 183 13176 [ 0 0 0 0 183 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Broadcast_Control: 538236 4305888 [ 0 538236 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Request_Control: 77259 618072 [ 0 77259 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Response_Data: 116 8352 [ 0 0 0 0 116 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_ResponseLocal_Data: 296 21312 [ 0 0 0 0 296 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Response_Control: 228 1824 [ 0 0 0 0 228 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Writeback_Data: 77093 5550696 [ 0 0 0 0 77093 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Broadcast_Control: 77259 618072 [ 0 77259 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Persistent_Control: 51372 410976 [ 0 0 0 51372 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_3: 3.2261
+  links_utilized_percent_switch_3_link_0: 4.16925 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 2.28295 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_3_link_0_Response_Data: 76263 5490936 [ 0 0 0 0 76263 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 190 13680 [ 0 0 0 0 190 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_ResponseLocal_Data: 283 20376 [ 0 0 0 0 283 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Writeback_Data: 142 10224 [ 0 0 0 0 142 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Broadcast_Control: 538706 4309648 [ 0 538706 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Request_Control: 76821 614568 [ 0 76821 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Data: 118 8496 [ 0 0 0 0 118 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_ResponseLocal_Data: 279 20088 [ 0 0 0 0 279 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Control: 244 1952 [ 0 0 0 0 244 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Writeback_Data: 76634 5517648 [ 0 0 0 0 76634 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Broadcast_Control: 76821 614568 [ 0 76821 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Persistent_Control: 50741 405928 [ 0 0 0 50741 0 0 0 0 0 0 ] base_latency: 1
 
 switch_4_inlinks: 2
 switch_4_outlinks: 2
-links_utilized_percent_switch_4: 3.22384
-  links_utilized_percent_switch_4_link_0: 4.1693 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_4_link_1: 2.27838 bw: 16000 base_latency: 1
+links_utilized_percent_switch_4: 3.22416
+  links_utilized_percent_switch_4_link_0: 4.16711 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_4_link_1: 2.28121 bw: 16000 base_latency: 1
 
-  outgoing_messages_switch_4_link_0_Response_Data: 75931 5467032 [ 0 0 0 0 75931 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_ResponseL2hit_Data: 211 15192 [ 0 0 0 0 211 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_ResponseLocal_Data: 287 20664 [ 0 0 0 0 287 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Data: 76124 5480928 [ 0 0 0 0 76124 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_ResponseL2hit_Data: 189 13608 [ 0 0 0 0 189 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_ResponseLocal_Data: 255 18360 [ 0 0 0 0 255 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_4_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Writeback_Data: 225 16200 [ 0 0 0 0 225 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Broadcast_Control: 538910 4311280 [ 0 538910 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Request_Control: 76585 612680 [ 0 76585 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Response_Data: 129 9288 [ 0 0 0 0 129 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_ResponseLocal_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Response_Control: 211 1688 [ 0 0 0 0 211 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Writeback_Data: 76442 5503824 [ 0 0 0 0 76442 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Broadcast_Control: 76585 612680 [ 0 76585 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Persistent_Control: 51095 408760 [ 0 0 0 51095 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Writeback_Data: 203 14616 [ 0 0 0 0 203 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Broadcast_Control: 538827 4310616 [ 0 538827 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Request_Control: 76700 613600 [ 0 76700 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Data: 121 8712 [ 0 0 0 0 121 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_ResponseLocal_Data: 298 21456 [ 0 0 0 0 298 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Control: 241 1928 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Writeback_Data: 76528 5510016 [ 0 0 0 0 76528 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Broadcast_Control: 76700 613600 [ 0 76700 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Persistent_Control: 51053 408424 [ 0 0 0 51053 0 0 0 0 0 0 ] base_latency: 1
 
 switch_5_inlinks: 2
 switch_5_outlinks: 2
-links_utilized_percent_switch_5: 3.22911
-  links_utilized_percent_switch_5_link_0: 4.17325 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_5_link_1: 2.28497 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_5_link_0_Response_Data: 76128 5481216 [ 0 0 0 0 76128 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_ResponseL2hit_Data: 184 13248 [ 0 0 0 0 184 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_ResponseLocal_Data: 305 21960 [ 0 0 0 0 305 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Writeback_Data: 231 16632 [ 0 0 0 0 231 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Broadcast_Control: 538720 4309760 [ 0 538720 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Request_Control: 76775 614200 [ 0 76775 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Response_Data: 138 9936 [ 0 0 0 0 138 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_ResponseLocal_Data: 274 19728 [ 0 0 0 0 274 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Response_Control: 228 1824 [ 0 0 0 0 228 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Writeback_Data: 76617 5516424 [ 0 0 0 0 76617 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Broadcast_Control: 76775 614200 [ 0 76775 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Persistent_Control: 51335 410680 [ 0 0 0 51335 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_5: 3.22862
+  links_utilized_percent_switch_5_link_0: 4.17097 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_1: 2.28627 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_5_link_0_Response_Data: 76217 5487624 [ 0 0 0 0 76217 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_ResponseL2hit_Data: 198 14256 [ 0 0 0 0 198 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_ResponseLocal_Data: 311 22392 [ 0 0 0 0 311 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Writeback_Data: 235 16920 [ 0 0 0 0 235 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Broadcast_Control: 538633 4309064 [ 0 538633 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Request_Control: 76894 615152 [ 0 76894 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Data: 119 8568 [ 0 0 0 0 119 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_ResponseLocal_Data: 270 19440 [ 0 0 0 0 270 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Control: 227 1816 [ 0 0 0 0 227 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Writeback_Data: 76732 5524704 [ 0 0 0 0 76732 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Broadcast_Control: 76894 615152 [ 0 76894 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Persistent_Control: 51107 408856 [ 0 0 0 51107 0 0 0 0 0 0 ] base_latency: 1
 
 switch_6_inlinks: 2
 switch_6_outlinks: 2
-links_utilized_percent_switch_6: 3.22368
-  links_utilized_percent_switch_6_link_0: 4.16935 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_6_link_1: 2.278 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_6_link_0_Response_Data: 75904 5465088 [ 0 0 0 0 75904 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_ResponseL2hit_Data: 201 14472 [ 0 0 0 0 201 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_ResponseLocal_Data: 289 20808 [ 0 0 0 0 289 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Writeback_Data: 263 18936 [ 0 0 0 0 263 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Broadcast_Control: 538905 4311240 [ 0 538905 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Request_Control: 76590 612720 [ 0 76590 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Response_Data: 120 8640 [ 0 0 0 0 120 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_ResponseLocal_Data: 269 19368 [ 0 0 0 0 269 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Response_Control: 239 1912 [ 0 0 0 0 239 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Writeback_Data: 76419 5502168 [ 0 0 0 0 76419 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Broadcast_Control: 76590 612720 [ 0 76590 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Persistent_Control: 50944 407552 [ 0 0 0 50944 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_6: 3.23111
+  links_utilized_percent_switch_6_link_0: 4.17316 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_6_link_1: 2.28907 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_6_link_0_Response_Data: 76312 5494464 [ 0 0 0 0 76312 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_ResponseL2hit_Data: 198 14256 [ 0 0 0 0 198 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_ResponseLocal_Data: 256 18432 [ 0 0 0 0 256 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Writeback_Data: 301 21672 [ 0 0 0 0 301 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Broadcast_Control: 538539 4308312 [ 0 538539 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Request_Control: 76988 615904 [ 0 76988 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Data: 107 7704 [ 0 0 0 0 107 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_ResponseLocal_Data: 265 19080 [ 0 0 0 0 265 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Control: 218 1744 [ 0 0 0 0 218 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Writeback_Data: 76849 5533128 [ 0 0 0 0 76849 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Broadcast_Control: 76988 615904 [ 0 76988 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Persistent_Control: 51127 409016 [ 0 0 0 51127 0 0 0 0 0 0 ] base_latency: 1
 
 switch_7_inlinks: 2
 switch_7_outlinks: 2
-links_utilized_percent_switch_7: 3.23753
-  links_utilized_percent_switch_7_link_0: 4.18018 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_7_link_1: 2.29487 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_7_link_0_Response_Data: 76423 5502456 [ 0 0 0 0 76423 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_ResponseL2hit_Data: 168 12096 [ 0 0 0 0 168 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_ResponseLocal_Data: 301 21672 [ 0 0 0 0 301 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Writeback_Data: 294 21168 [ 0 0 0 0 294 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Broadcast_Control: 538401 4307208 [ 0 538401 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Request_Control: 77094 616752 [ 0 77094 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Response_Data: 108 7776 [ 0 0 0 0 108 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_ResponseLocal_Data: 298 21456 [ 0 0 0 0 298 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Response_Control: 217 1736 [ 0 0 0 0 217 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Writeback_Data: 76967 5541624 [ 0 0 0 0 76967 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Broadcast_Control: 77094 616752 [ 0 77094 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Persistent_Control: 51503 412024 [ 0 0 0 51503 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_7: 3.23256
+  links_utilized_percent_switch_7_link_0: 4.17354 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_7_link_1: 2.29158 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_7_link_0_Response_Data: 76311 5494392 [ 0 0 0 0 76311 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_ResponseL2hit_Data: 193 13896 [ 0 0 0 0 193 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_ResponseLocal_Data: 296 21312 [ 0 0 0 0 296 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Writeback_Data: 287 20664 [ 0 0 0 0 287 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Broadcast_Control: 538512 4308096 [ 0 538512 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Request_Control: 77015 616120 [ 0 77015 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Data: 111 7992 [ 0 0 0 0 111 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_ResponseLocal_Data: 272 19584 [ 0 0 0 0 272 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Control: 231 1848 [ 0 0 0 0 231 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Writeback_Data: 76856 5533632 [ 0 0 0 0 76856 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Broadcast_Control: 77015 616120 [ 0 77015 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Persistent_Control: 51886 415088 [ 0 0 0 51886 0 0 0 0 0 0 ] base_latency: 1
 
 switch_8_inlinks: 2
 switch_8_outlinks: 2
-links_utilized_percent_switch_8: 12.1177
-  links_utilized_percent_switch_8_link_0: 16.6607 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_8_link_1: 7.57472 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_8_link_0_Request_Control: 615495 4923960 [ 0 615495 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Response_Control: 1833 14664 [ 0 0 0 0 1833 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Writeback_Data: 613630 44181360 [ 0 0 0 0 613630 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Request_Control: 613969 4911752 [ 0 0 613969 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Response_Data: 1306 94032 [ 0 0 0 0 1306 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_ResponseL2hit_Data: 1526 109872 [ 0 0 0 0 1526 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_8: 12.1124
+  links_utilized_percent_switch_8_link_0: 16.6506 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_8_link_1: 7.57426 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_8_link_0_Request_Control: 615527 4924216 [ 0 615527 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Response_Control: 1919 15352 [ 0 0 0 0 1919 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Writeback_Data: 613576 44177472 [ 0 0 0 0 613576 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Request_Control: 614008 4912064 [ 0 0 614008 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Response_Data: 1331 95832 [ 0 0 0 0 1331 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_ResponseL2hit_Data: 1519 109368 [ 0 0 0 0 1519 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_8_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Writeback_Data: 215997 15551784 [ 0 0 0 0 215997 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Writeback_Control: 394694 3157552 [ 0 0 0 0 394694 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Writeback_Data: 216082 15557904 [ 0 0 0 0 216082 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Writeback_Control: 394626 3157008 [ 0 0 0 0 394626 0 0 0 0 0 ] base_latency: 1
 
 switch_9_inlinks: 2
 switch_9_outlinks: 2
-links_utilized_percent_switch_9: 11.2311
-  links_utilized_percent_switch_9_link_0: 8.53279 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_1: 13.9295 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_9_link_0_Request_Control: 613968 4911744 [ 0 0 613968 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Writeback_Data: 215079 15485688 [ 0 0 0 0 215079 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Writeback_Control: 394695 3157560 [ 0 0 0 0 394695 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Response_Data: 608494 43811568 [ 0 0 0 0 608494 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Writeback_Data: 18 1296 [ 0 0 0 0 18 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_9: 11.2269
+  links_utilized_percent_switch_9_link_0: 8.52878 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_1: 13.9251 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_9_link_0_Request_Control: 614008 4912064 [ 0 0 614008 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Writeback_Data: 215179 15492888 [ 0 0 0 0 215179 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Writeback_Control: 394628 3157024 [ 0 0 0 0 394628 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Data: 608514 43813008 [ 0 0 0 0 608514 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Writeback_Data: 25 1800 [ 0 0 0 0 25 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_9_link_1_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
 
 switch_10_inlinks: 10
 switch_10_outlinks: 10
-links_utilized_percent_switch_10: 5.75614
-  links_utilized_percent_switch_10_link_0: 4.05074 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_10_link_1: 4.0479 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_10_link_2: 4.04603 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_10_link_3: 4.05221 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_10_link_4: 4.03934 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_10_link_5: 4.04268 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_10_link_6: 4.03978 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_10_link_7: 4.04919 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_10_link_8: 16.6607 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_10_link_9: 8.53279 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_10_link_0_Response_Data: 76720 5523840 [ 0 0 0 0 76720 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_ResponseL2hit_Data: 204 14688 [ 0 0 0 0 204 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_ResponseLocal_Data: 259 18648 [ 0 0 0 0 259 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_Writeback_Data: 82 5904 [ 0 0 0 0 82 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_Broadcast_Control: 538306 4306448 [ 0 538306 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_Persistent_Control: 358925 2871400 [ 0 0 0 358925 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Response_Data: 76500 5508000 [ 0 0 0 0 76500 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_ResponseL2hit_Data: 196 14112 [ 0 0 0 0 196 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_ResponseLocal_Data: 276 19872 [ 0 0 0 0 276 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Writeback_Data: 109 7848 [ 0 0 0 0 109 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Broadcast_Control: 538478 4307824 [ 0 538478 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Persistent_Control: 359289 2874312 [ 0 0 0 359289 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_Response_Data: 76476 5506272 [ 0 0 0 0 76476 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_ResponseL2hit_Data: 191 13752 [ 0 0 0 0 191 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_ResponseLocal_Data: 247 17784 [ 0 0 0 0 247 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_Writeback_Data: 126 9072 [ 0 0 0 0 126 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_Broadcast_Control: 538509 4308072 [ 0 538509 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_Persistent_Control: 358895 2871160 [ 0 0 0 358895 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Response_Data: 76703 5522616 [ 0 0 0 0 76703 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_ResponseL2hit_Data: 171 12312 [ 0 0 0 0 171 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_ResponseLocal_Data: 265 19080 [ 0 0 0 0 265 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Writeback_Data: 183 13176 [ 0 0 0 0 183 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Broadcast_Control: 538236 4305888 [ 0 538236 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Persistent_Control: 359058 2872464 [ 0 0 0 359058 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_Response_Data: 75931 5467032 [ 0 0 0 0 75931 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_ResponseL2hit_Data: 211 15192 [ 0 0 0 0 211 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_ResponseLocal_Data: 287 20664 [ 0 0 0 0 287 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_10: 5.75149
+  links_utilized_percent_switch_10_link_0: 4.05098 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_1: 4.04399 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_2: 4.03719 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_3: 4.04024 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_4: 4.03732 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_5: 4.04103 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_6: 4.04317 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_7: 4.04162 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_8: 16.6506 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_9: 8.52878 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_10_link_0_Response_Data: 76922 5538384 [ 0 0 0 0 76922 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_ResponseL2hit_Data: 186 13392 [ 0 0 0 0 186 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_ResponseLocal_Data: 277 19944 [ 0 0 0 0 277 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Writeback_Data: 80 5760 [ 0 0 0 0 80 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Broadcast_Control: 538135 4305080 [ 0 538135 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Persistent_Control: 357965 2863720 [ 0 0 0 357965 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Response_Data: 76476 5506272 [ 0 0 0 0 76476 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_ResponseL2hit_Data: 187 13464 [ 0 0 0 0 187 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_ResponseLocal_Data: 309 22248 [ 0 0 0 0 309 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Writeback_Data: 126 9072 [ 0 0 0 0 126 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Broadcast_Control: 538503 4308024 [ 0 538503 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Persistent_Control: 358153 2865224 [ 0 0 0 358153 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Response_Data: 76167 5484024 [ 0 0 0 0 76167 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_ResponseL2hit_Data: 178 12816 [ 0 0 0 0 178 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_ResponseLocal_Data: 282 20304 [ 0 0 0 0 282 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Writeback_Data: 133 9576 [ 0 0 0 0 133 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Broadcast_Control: 538834 4310672 [ 0 538834 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Persistent_Control: 358188 2865504 [ 0 0 0 358188 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Response_Data: 76263 5490936 [ 0 0 0 0 76263 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_ResponseL2hit_Data: 190 13680 [ 0 0 0 0 190 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_ResponseLocal_Data: 283 20376 [ 0 0 0 0 283 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Writeback_Data: 142 10224 [ 0 0 0 0 142 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Broadcast_Control: 538706 4309648 [ 0 538706 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Persistent_Control: 358455 2867640 [ 0 0 0 358455 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Response_Data: 76124 5480928 [ 0 0 0 0 76124 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_ResponseL2hit_Data: 189 13608 [ 0 0 0 0 189 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_ResponseLocal_Data: 255 18360 [ 0 0 0 0 255 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_10_link_4_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_Writeback_Data: 225 16200 [ 0 0 0 0 225 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_Broadcast_Control: 538910 4311280 [ 0 538910 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_Persistent_Control: 359335 2874680 [ 0 0 0 359335 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_Response_Data: 76128 5481216 [ 0 0 0 0 76128 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_ResponseL2hit_Data: 184 13248 [ 0 0 0 0 184 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_ResponseLocal_Data: 305 21960 [ 0 0 0 0 305 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_Writeback_Data: 231 16632 [ 0 0 0 0 231 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_Broadcast_Control: 538720 4309760 [ 0 538720 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_Persistent_Control: 359095 2872760 [ 0 0 0 359095 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Response_Data: 75904 5465088 [ 0 0 0 0 75904 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_ResponseL2hit_Data: 201 14472 [ 0 0 0 0 201 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_ResponseLocal_Data: 289 20808 [ 0 0 0 0 289 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Writeback_Data: 263 18936 [ 0 0 0 0 263 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Broadcast_Control: 538905 4311240 [ 0 538905 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Persistent_Control: 359486 2875888 [ 0 0 0 359486 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Response_Data: 76423 5502456 [ 0 0 0 0 76423 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_ResponseL2hit_Data: 168 12096 [ 0 0 0 0 168 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_ResponseLocal_Data: 301 21672 [ 0 0 0 0 301 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Writeback_Data: 294 21168 [ 0 0 0 0 294 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Broadcast_Control: 538401 4307208 [ 0 538401 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Persistent_Control: 358927 2871416 [ 0 0 0 358927 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_8_Request_Control: 615495 4923960 [ 0 615495 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_8_Response_Control: 1833 14664 [ 0 0 0 0 1833 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_8_Writeback_Data: 613630 44181360 [ 0 0 0 0 613630 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_8_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_9_Request_Control: 613969 4911752 [ 0 0 613969 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_9_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_9_Writeback_Data: 215079 15485688 [ 0 0 0 0 215079 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_9_Writeback_Control: 394695 3157560 [ 0 0 0 0 394695 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_9_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Writeback_Data: 203 14616 [ 0 0 0 0 203 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Broadcast_Control: 538827 4310616 [ 0 538827 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Persistent_Control: 358143 2865144 [ 0 0 0 358143 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Response_Data: 76217 5487624 [ 0 0 0 0 76217 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_ResponseL2hit_Data: 198 14256 [ 0 0 0 0 198 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_ResponseLocal_Data: 311 22392 [ 0 0 0 0 311 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Writeback_Data: 235 16920 [ 0 0 0 0 235 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Broadcast_Control: 538633 4309064 [ 0 538633 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Persistent_Control: 358089 2864712 [ 0 0 0 358089 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Response_Data: 76312 5494464 [ 0 0 0 0 76312 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_ResponseL2hit_Data: 198 14256 [ 0 0 0 0 198 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_ResponseLocal_Data: 256 18432 [ 0 0 0 0 256 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Writeback_Data: 301 21672 [ 0 0 0 0 301 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Broadcast_Control: 538539 4308312 [ 0 538539 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Persistent_Control: 358069 2864552 [ 0 0 0 358069 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Response_Data: 76311 5494392 [ 0 0 0 0 76311 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_ResponseL2hit_Data: 193 13896 [ 0 0 0 0 193 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_ResponseLocal_Data: 296 21312 [ 0 0 0 0 296 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Writeback_Data: 287 20664 [ 0 0 0 0 287 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Broadcast_Control: 538512 4308096 [ 0 538512 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Persistent_Control: 357310 2858480 [ 0 0 0 357310 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Request_Control: 615527 4924216 [ 0 615527 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Response_Control: 1919 15352 [ 0 0 0 0 1919 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Writeback_Data: 613576 44177472 [ 0 0 0 0 613576 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Request_Control: 614008 4912064 [ 0 0 614008 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Writeback_Data: 215179 15492888 [ 0 0 0 0 215179 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Writeback_Control: 394628 3157024 [ 0 0 0 0 394628 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1
 
 Cache Stats: system.l1_cntrl0.L1IcacheMemory
   system.l1_cntrl0.L1IcacheMemory_total_misses: 0
@@ -436,80 +430,80 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 77189
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 77189
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 77392
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 77392
   system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   65.1557%
-  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   34.8443%
+  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   64.7535%
+  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   35.2465%
 
-  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   77189    100%
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   77392    100%
 
  --- L1Cache ---
  - Event Counts -
-Load [49690 49997 49629 50054 50303 50190 50006 50073 ] 399942
+Load [50067 49857 50011 50121 50120 50072 49850 49845 ] 399943
 Ifetch [0 0 0 0 0 0 0 0 ] 0
-Store [26905 26796 26976 27053 26903 26845 27007 27200 ] 215685
+Store [26650 27053 27004 26916 27282 26976 26863 27000 ] 215744
 Atomic [0 0 0 0 0 0 0 0 ] 0
-L1_Replacement [1281089 1281955 1281461 1287176 1288071 1285927 1285387 1289906 ] 10280972
-Data_Shared [262 248 238 231 241 229 241 222 ] 1912
-Data_Owner [57 66 67 68 67 47 58 64 ] 494
-Data_All_Tokens [76335 76534 76352 76887 76957 76805 76741 77036 ] 613647
-Ack [1 0 1 1 0 1 0 1 ] 5
-Ack_All_Tokens [0 0 0 1 0 0 0 1 ] 2
+L1_Replacement [1283063 1285718 1284830 1287683 1292303 1287314 1281727 1284342 ] 10286980
+Data_Shared [248 259 233 244 221 248 232 234 ] 1919
+Data_Owner [38 49 40 55 56 61 50 38 ] 387
+Data_All_Tokens [76485 76653 76794 76788 77188 76789 76478 76606 ] 613781
+Ack [3 1 2 0 1 0 0 0 ] 7
+Ack_All_Tokens [0 0 1 0 0 0 0 0 ] 1
 Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-Transient_Local_GETX [188736 188850 188667 188589 188743 188802 188643 188443 ] 1509473
+Transient_Local_GETX [189041 188639 188690 188780 188410 188723 188833 188700 ] 1509816
 Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-Transient_Local_GETS [350173 349869 350237 349812 349562 349676 349865 349793 ] 2798987
+Transient_Local_GETS [349784 349993 349848 349731 349725 349779 350000 350006 ] 2798866
 Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-Transient_Local_GETS_Last_Token [1 1 1 0 1 0 1 0 ] 5
-Persistent_GETX [63290 63349 63338 63218 63414 63370 63215 63283 ] 506477
-Persistent_GETS [117375 117192 117390 117254 117011 117217 117177 117246 ] 937862
-Persistent_GETS_Last_Token [0 0 0 0 0 0 1 0 ] 1
-Own_Lock_or_Unlock [229765 229889 229702 229958 230005 229843 230037 229901 ] 1839100
-Request_Timeout [490512 494638 490301 490311 493060 493644 493295 485817 ] 3931578
-Use_TimeoutStarverX [6 4 5 6 0 3 4 9 ] 37
-Use_TimeoutStarverS [12 18 9 7 5 3 13 9 ] 76
-Use_TimeoutNoStarvers [76249 76442 76272 76789 76882 76734 76675 76961 ] 613004
+Transient_Local_GETS_Last_Token [2 1 1 1 0 1 1 0 ] 7
+Persistent_GETX [63219 62991 63051 63029 63043 63030 63120 63186 ] 504669
+Persistent_GETS [116839 117030 116963 116632 116869 116995 116945 117021 ] 935294
+Persistent_GETS_Last_Token [0 1 0 0 1 0 1 0 ] 3
+Own_Lock_or_Unlock [229138 229174 229182 229535 229283 229171 229130 228989 ] 1833602
+Request_Timeout [493475 496675 494238 497044 493350 493296 492735 489501 ] 3950314
+Use_TimeoutStarverX [9 11 10 5 3 3 5 4 ] 50
+Use_TimeoutStarverS [14 12 13 14 1 7 20 7 ] 88
+Use_TimeoutNoStarvers [76389 76563 76693 76698 77115 76714 76389 76537 ] 613098
 Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0
 
  - Transitions -
-NP  Load [49577 49883 49528 49948 50192 50080 49879 49958 ] 399045
+NP  Load [49951 49739 49879 49987 50006 49959 49727 49727 ] 398975
 NP  Ifetch [0 0 0 0 0 0 0 0 ] 0
-NP  Store [26838 26735 26909 27000 26843 26777 26936 27143 ] 215181
+NP  Store [26591 26993 26943 26840 27222 26901 26786 26933 ] 215209
 NP  Atomic [0 0 0 0 0 0 0 0 ] 0
-NP  Data_Shared [0 0 0 1 0 0 0 0 ] 1
-NP  Data_Owner [4 4 5 8 9 1 8 8 ] 47
-NP  Data_All_Tokens [68 70 66 85 68 64 49 57 ] 527
-NP  Ack [0 0 0 1 0 0 0 1 ] 2
+NP  Data_Shared [0 0 0 0 0 0 0 0 ] 0
+NP  Data_Owner [1 3 3 4 5 11 6 2 ] 35
+NP  Data_All_Tokens [71 66 79 71 68 65 64 58 ] 542
+NP  Ack [2 0 0 0 0 0 0 0 ] 2
 NP  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-NP  Transient_Local_GETX [188060 188135 187942 187878 188024 188099 187945 187729 ] 1503812
+NP  Transient_Local_GETX [188319 187906 187930 188079 187687 187997 188114 188005 ] 1504037
 NP  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-NP  Transient_Local_GETS [348916 348636 348950 348528 348293 348374 348601 348501 ] 2788799
+NP  Transient_Local_GETS [348384 348668 348524 348411 348418 348421 348646 348662 ] 2788134
 NP  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
 NP  Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
 NP  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-NP  Own_Lock_or_Unlock [199095 199187 199157 199216 199244 199357 199305 199312 ] 1593873
+NP  Own_Lock_or_Unlock [198434 198575 198742 198423 198646 198582 198558 198633 ] 1588593
 
-I  Load [0 0 0 0 0 0 0 0 ] 0
+I  Load [0 0 0 0 1 0 0 0 ] 1
 I  Ifetch [0 0 0 0 0 0 0 0 ] 0
-I  Store [0 0 1 0 0 0 0 1 ] 2
+I  Store [0 0 0 0 0 0 0 0 ] 0
 I  Atomic [0 0 0 0 0 0 0 0 ] 0
-I  L1_Replacement [211 228 237 217 226 247 239 226 ] 1831
+I  L1_Replacement [241 227 217 230 252 253 255 243 ] 1918
 I  Data_Shared [0 0 0 0 0 0 0 0 ] 0
 I  Data_Owner [0 0 0 0 0 0 0 0 ] 0
 I  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
 I  Ack [0 0 0 0 0 0 0 0 ] 0
 I  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-I  Transient_Local_GETX [2 1 0 0 0 0 0 0 ] 3
+I  Transient_Local_GETX [1 0 1 0 0 0 0 1 ] 3
 I  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-I  Transient_Local_GETS [2 0 0 2 0 1 1 1 ] 7
+I  Transient_Local_GETS [0 1 1 0 1 0 1 1 ] 5
 I  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 I  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 I  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
-I  Persistent_GETS [0 1 0 0 0 0 1 0 ] 2
+I  Persistent_GETS [0 1 0 1 0 0 0 0 ] 2
 I  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 I  Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
 
@@ -517,122 +511,122 @@ S  Load [0 0 0 0 0 0 0 0 ] 0
 S  Ifetch [0 0 0 0 0 0 0 0 ] 0
 S  Store [0 0 0 0 0 0 0 0 ] 0
 S  Atomic [0 0 0 0 0 0 0 0 ] 0
-S  L1_Replacement [319 311 290 284 299 283 290 272 ] 2348
-S  Data_Shared [0 0 0 0 0 1 0 1 ] 2
-S  Data_Owner [0 1 0 0 0 0 0 0 ] 1
+S  L1_Replacement [296 296 271 286 260 285 287 269 ] 2250
+S  Data_Shared [0 1 0 1 0 0 0 0 ] 2
+S  Data_Owner [1 0 0 0 1 1 0 0 ] 3
 S  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
 S  Ack [0 0 0 0 0 0 0 0 ] 0
 S  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-S  Transient_Local_GETX [0 0 0 0 0 0 1 0 ] 1
+S  Transient_Local_GETX [0 0 1 0 1 0 0 0 ] 2
 S  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-S  Transient_Local_GETS [1 0 0 0 0 0 0 0 ] 1
+S  Transient_Local_GETS [0 1 0 1 0 0 1 0 ] 3
 S  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-S  Transient_Local_GETS_Last_Token [1 1 1 0 1 0 1 0 ] 5
-S  Persistent_GETX [0 0 1 0 0 0 0 0 ] 1
+S  Transient_Local_GETS_Last_Token [2 1 1 1 0 1 1 0 ] 7
+S  Persistent_GETX [0 0 0 1 0 0 0 1 ] 2
 S  Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
-S  Persistent_GETS_Last_Token [0 0 0 0 0 0 1 0 ] 1
+S  Persistent_GETS_Last_Token [0 1 0 0 1 0 1 0 ] 3
 S  Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
 
 O  Load [0 0 0 0 0 0 0 0 ] 0
 O  Ifetch [0 0 0 0 0 0 0 0 ] 0
 O  Store [0 0 0 0 0 0 0 0 ] 0
 O  Atomic [0 0 0 0 0 0 0 0 ] 0
-O  L1_Replacement [153 182 161 192 182 167 153 188 ] 1378
+O  L1_Replacement [163 169 151 160 159 184 161 154 ] 1301
 O  Data_Shared [0 0 0 0 0 0 0 0 ] 0
 O  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
 O  Ack [0 0 0 0 0 0 0 0 ] 0
-O  Ack_All_Tokens [0 0 0 0 0 0 0 1 ] 1
+O  Ack_All_Tokens [0 0 0 0 0 0 0 0 ] 0
 O  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-O  Transient_Local_GETX [0 0 0 0 0 0 0 1 ] 1
+O  Transient_Local_GETX [2 0 0 0 0 0 0 0 ] 2
 O  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-O  Transient_Local_GETS [1 0 0 2 0 0 0 0 ] 3
+O  Transient_Local_GETS [1 0 2 0 0 2 0 1 ] 6
 O  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 O  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 O  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
-O  Persistent_GETS [0 0 0 0 2 1 0 0 ] 3
+O  Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
 O  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-O  Own_Lock_or_Unlock [16 16 25 18 18 10 18 19 ] 140
+O  Own_Lock_or_Unlock [11 14 22 12 16 11 6 13 ] 105
 
-M  Load [4 7 7 7 6 6 8 8 ] 53
+M  Load [6 7 10 9 4 8 7 7 ] 58
 M  Ifetch [0 0 0 0 0 0 0 0 ] 0
-M  Store [2 2 1 1 4 3 7 2 ] 22
+M  Store [1 3 4 6 2 9 2 9 ] 36
 M  Atomic [0 0 0 0 0 0 0 0 ] 0
-M  L1_Replacement [49126 49389 49077 49486 49717 49626 49450 49528 ] 395399
+M  L1_Replacement [49496 49294 49471 49566 49592 49476 49288 49311 ] 395494
 M  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-M  Transient_Local_GETX [56 69 55 60 63 64 64 45 ] 476
+M  Transient_Local_GETX [61 53 60 64 59 74 65 53 ] 489
 M  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-M  Transient_Local_GETS [100 120 99 133 126 122 103 134 ] 937
-M  Persistent_GETX [20 28 27 15 24 31 20 16 ] 181
-M  Persistent_GETS [47 54 45 47 52 51 41 43 ] 380
-M  Own_Lock_or_Unlock [2949 2916 2889 2948 2917 2850 2824 2858 ] 23151
+M  Transient_Local_GETS [128 123 115 109 108 134 117 118 ] 952
+M  Persistent_GETX [24 22 23 19 35 25 27 32 ] 207
+M  Persistent_GETS [40 32 30 34 41 35 42 33 ] 287
+M  Own_Lock_or_Unlock [3047 2879 2828 3000 2831 2866 2941 2876 ] 23268
 
-MM  Load [3 3 3 2 4 3 4 1 ] 23
+MM  Load [5 4 9 3 1 5 3 5 ] 35
 MM  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MM  Store [0 3 2 1 2 5 4 1 ] 18
+MM  Store [1 1 1 1 2 1 4 3 ] 14
 MM  Atomic [0 0 0 0 0 0 0 0 ] 0
-MM  L1_Replacement [26772 26662 26820 26911 26761 26690 26850 27040 ] 214506
+MM  L1_Replacement [26500 26904 26874 26769 27124 26822 26698 26840 ] 214531
 MM  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-MM  Transient_Local_GETX [30 28 41 35 44 40 37 28 ] 283
+MM  Transient_Local_GETX [31 32 38 35 41 40 40 28 ] 285
 MM  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-MM  Transient_Local_GETS [53 57 74 68 53 66 69 88 ] 528
-MM  Persistent_GETX [15 14 9 10 15 14 16 16 ] 109
-MM  Persistent_GETS [29 20 25 23 26 29 24 23 ] 199
-MM  Own_Lock_or_Unlock [1614 1548 1613 1522 1530 1479 1526 1529 ] 12361
+MM  Transient_Local_GETS [75 61 50 63 73 55 76 79 ] 532
+MM  Persistent_GETX [10 17 13 9 15 11 12 13 ] 100
+MM  Persistent_GETS [24 25 18 30 25 41 23 29 ] 215
+MM  Own_Lock_or_Unlock [1583 1584 1504 1627 1576 1603 1541 1560 ] 12578
 
-M_W  Load [1 1 1 1 0 1 3 0 ] 8
+M_W  Load [1 1 1 1 0 0 2 0 ] 6
 M_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
-M_W  Store [0 0 0 1 1 0 0 0 ] 2
+M_W  Store [0 0 0 1 0 1 2 0 ] 4
 M_W  Atomic [0 0 0 0 0 0 0 0 ] 0
-M_W  L1_Replacement [220700 219307 219095 219747 220275 220407 219276 220317 ] 1759124
+M_W  L1_Replacement [220446 219952 218923 221066 221838 221045 220014 221393 ] 1764677
 M_W  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-M_W  Transient_Local_GETX [9 9 11 11 9 9 17 9 ] 84
+M_W  Transient_Local_GETX [18 12 11 13 13 15 6 12 ] 100
 M_W  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-M_W  Transient_Local_GETS [23 14 21 21 17 25 24 15 ] 160
-M_W  Persistent_GETX [3 2 2 3 0 3 2 7 ] 22
-M_W  Persistent_GETS [10 10 8 6 3 3 8 6 ] 54
-M_W  Own_Lock_or_Unlock [145 136 179 143 176 142 165 174 ] 1260
-M_W  Use_TimeoutStarverX [3 2 3 3 0 3 3 8 ] 25
-M_W  Use_TimeoutStarverS [10 10 8 7 4 3 9 8 ] 59
-M_W  Use_TimeoutNoStarvers [49352 49663 49304 49742 49987 49897 49685 49768 ] 397398
+M_W  Transient_Local_GETS [12 20 17 17 22 21 15 22 ] 146
+M_W  Persistent_GETX [7 5 6 1 3 2 3 2 ] 29
+M_W  Persistent_GETS [9 6 7 9 0 3 13 2 ] 49
+M_W  Own_Lock_or_Unlock [154 148 142 150 154 164 163 169 ] 1244
+M_W  Use_TimeoutStarverX [8 8 6 2 3 2 3 2 ] 34
+M_W  Use_TimeoutStarverS [9 6 9 10 0 3 13 3 ] 53
+M_W  Use_TimeoutNoStarvers [49750 49527 49704 49798 49839 49754 49541 49556 ] 397469
 M_W  Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0
 
-MM_W  Load [0 0 0 0 0 0 1 1 ] 2
+MM_W  Load [2 0 1 1 1 0 0 0 ] 5
 MM_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MM_W  Store [0 1 1 0 0 0 0 1 ] 3
+MM_W  Store [1 0 1 0 0 0 0 0 ] 2
 MM_W  Atomic [0 0 0 0 0 0 0 0 ] 0
-MM_W  L1_Replacement [120344 118153 120667 120138 118740 118451 120032 120021 ] 956546
+MM_W  L1_Replacement [118638 120623 119771 118934 120300 120552 119544 120447 ] 958809
 MM_W  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-MM_W  Transient_Local_GETX [7 5 5 3 4 9 3 5 ] 41
+MM_W  Transient_Local_GETX [5 1 7 8 5 6 7 9 ] 48
 MM_W  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-MM_W  Transient_Local_GETS [10 9 14 10 6 13 8 11 ] 81
-MM_W  Persistent_GETX [3 1 2 3 0 0 1 1 ] 11
-MM_W  Persistent_GETS [2 7 1 0 0 0 4 1 ] 15
-MM_W  Own_Lock_or_Unlock [96 78 73 80 92 111 93 104 ] 727
-MM_W  Use_TimeoutStarverX [3 2 2 3 0 0 1 1 ] 12
-MM_W  Use_TimeoutStarverS [2 8 1 0 1 0 4 1 ] 17
-MM_W  Use_TimeoutNoStarvers [26897 26779 26968 27047 26895 26837 26990 27193 ] 215606
+MM_W  Transient_Local_GETS [11 8 10 15 8 13 14 13 ] 92
+MM_W  Persistent_GETX [1 3 3 3 0 1 1 2 ] 14
+MM_W  Persistent_GETS [4 6 4 3 1 4 7 4 ] 33
+MM_W  Own_Lock_or_Unlock [87 84 100 86 91 89 84 102 ] 723
+MM_W  Use_TimeoutStarverX [1 3 4 3 0 1 2 2 ] 16
+MM_W  Use_TimeoutStarverS [5 6 4 4 1 4 7 4 ] 35
+MM_W  Use_TimeoutNoStarvers [26639 27036 26989 26900 27276 26960 26848 26981 ] 215629
 MM_W  Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0
 
 IM  Load [0 0 0 0 0 0 0 0 ] 0
 IM  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IM  Store [0 0 0 0 0 0 0 0 ] 0
 IM  Atomic [0 0 0 0 0 0 0 0 ] 0
-IM  L1_Replacement [301391 304654 304665 306965 304178 304263 304380 303335 ] 2433831
+IM  L1_Replacement [298819 304518 304460 302190 305979 304258 303791 302725 ] 2426740
 IM  Data_Shared [0 0 0 0 0 0 0 0 ] 0
-IM  Data_Owner [0 0 0 1 0 0 0 0 ] 1
-IM  Data_All_Tokens [26902 26787 26971 27049 26894 26837 26995 27195 ] 215630
-IM  Ack [1 0 1 0 0 1 0 0 ] 3
+IM  Data_Owner [0 0 1 0 0 0 0 0 ] 1
+IM  Data_All_Tokens [26645 27046 26995 26905 27277 26964 26854 26987 ] 215673
+IM  Ack [1 1 2 0 1 0 0 0 ] 5
 IM  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-IM  Transient_Local_GETX [81 92 95 92 96 89 75 101 ] 721
+IM  Transient_Local_GETX [92 103 98 98 79 83 85 72 ] 710
 IM  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-IM  Transient_Local_GETS [146 170 156 155 165 163 162 147 ] 1264
+IM  Transient_Local_GETS [183 171 176 158 171 191 142 185 ] 1377
 IM  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 IM  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-IM  Persistent_GETX [43 52 38 56 39 37 50 38 ] 353
-IM  Persistent_GETS [78 85 94 92 56 58 77 65 ] 605
+IM  Persistent_GETX [46 55 43 42 33 40 48 33 ] 340
+IM  Persistent_GETS [76 81 83 93 63 79 51 79 ] 605
 IM  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-IM  Own_Lock_or_Unlock [8886 8829 8871 8962 8795 8820 8972 8897 ] 71032
-IM  Request_Timeout [173243 171251 171891 171981 171016 170371 172749 170073 ] 1372575
+IM  Own_Lock_or_Unlock [8718 8931 8869 8889 8914 8908 8835 8741 ] 70805
+IM  Request_Timeout [173130 177820 171948 172223 170303 169179 174498 173026 ] 1382127
 
 SM  Load [0 0 0 0 0 0 0 0 ] 0
 SM  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -663,7 +657,7 @@ OM  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 OM  Data_Shared [0 0 0 0 0 0 0 0 ] 0
 OM  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
 OM  Ack [0 0 0 0 0 0 0 0 ] 0
-OM  Ack_All_Tokens [0 0 0 1 0 0 0 0 ] 1
+OM  Ack_All_Tokens [0 0 1 0 0 0 0 0 ] 1
 OM  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
 OM  Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
 OM  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
@@ -680,48 +674,48 @@ IS  Load [0 0 0 0 0 0 0 0 ] 0
 IS  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IS  Store [0 0 0 0 0 0 0 0 ] 0
 IS  Atomic [0 0 0 0 0 0 0 0 ] 0
-IS  L1_Replacement [558391 559786 557026 559859 565174 562983 561754 565799 ] 4490772
-IS  Data_Shared [262 248 238 230 241 228 241 221 ] 1909
-IS  Data_Owner [53 61 62 59 58 46 50 56 ] 445
-IS  Data_All_Tokens [49365 49675 49314 49752 49992 49903 49695 49781 ] 397477
+IS  L1_Replacement [565054 560250 560752 564542 563977 561580 558502 560185 ] 4494842
+IS  Data_Shared [248 258 233 243 221 248 232 234 ] 1917
+IS  Data_Owner [36 46 36 51 50 49 44 36 ] 348
+IS  Data_All_Tokens [49766 49538 49717 49809 49842 49760 49559 49560 ] 397551
 IS  Ack [0 0 0 0 0 0 0 0 ] 0
 IS  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-IS  Transient_Local_GETX [152 165 194 154 155 145 162 176 ] 1303
+IS  Transient_Local_GETX [161 174 184 133 159 144 158 159 ] 1272
 IS  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-IS  Transient_Local_GETS [307 263 305 268 293 329 302 280 ] 2347
+IS  Transient_Local_GETS [316 275 309 312 280 284 305 264 ] 2345
 IS  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 IS  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-IS  Persistent_GETX [74 71 106 80 51 70 64 83 ] 599
-IS  Persistent_GETS [161 147 137 141 126 112 141 118 ] 1083
+IS  Persistent_GETX [70 82 101 76 68 77 75 70 ] 619
+IS  Persistent_GETS [141 146 152 152 129 126 131 120 ] 1097
 IS  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-IS  Own_Lock_or_Unlock [16309 16529 16248 16447 16685 16505 16513 16434 ] 131670
-IS  Request_Timeout [313059 320314 315804 315404 319222 320475 317516 312314 ] 2534108
+IS  Own_Lock_or_Unlock [16494 16315 16326 16687 16478 16340 16388 16314 ] 131342
+IS  Request_Timeout [317408 315566 318533 322146 320140 320154 314719 313887 ] 2542553
 
-I_L  Load [105 103 90 96 101 100 111 105 ] 811
+I_L  Load [102 106 111 120 107 100 111 106 ] 863
 I_L  Ifetch [0 0 0 0 0 0 0 0 ] 0
-I_L  Store [65 55 62 50 53 60 60 52 ] 457
+I_L  Store [56 56 55 68 56 64 69 55 ] 479
 I_L  Atomic [0 0 0 0 0 0 0 0 ] 0
-I_L  L1_Replacement [25 126 71 53 116 66 12 64 ] 533
+I_L  L1_Replacement [89 72 47 109 96 84 43 117 ] 657
 I_L  Data_Shared [0 0 0 0 0 0 0 0 ] 0
 I_L  Data_Owner [0 0 0 0 0 0 0 0 ] 0
-I_L  Data_All_Tokens [0 0 0 0 1 1 0 0 ] 2
+I_L  Data_All_Tokens [1 0 0 0 1 0 0 0 ] 2
 I_L  Ack [0 0 0 0 0 0 0 0 ] 0
 I_L  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-I_L  Transient_Local_GETX [339 346 324 355 348 347 338 348 ] 2745
+I_L  Transient_Local_GETX [350 358 360 349 366 364 358 361 ] 2866
 I_L  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-I_L  Transient_Local_GETS [612 599 617 623 607 583 593 613 ] 4847
+I_L  Transient_Local_GETS [673 663 642 644 642 658 683 660 ] 5265
 I_L  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 I_L  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-I_L  Persistent_GETX [63107 63144 63106 63004 63284 63208 63045 63090 ] 504988
-I_L  Persistent_GETS [116967 116795 117007 116853 116744 116946 116855 116933 ] 935100
+I_L  Persistent_GETX [63036 62768 62815 62839 62889 62863 62943 63016 ] 503169
+I_L  Persistent_GETS [116485 116671 116569 116206 116607 116685 116643 116715 ] 932581
 I_L  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-I_L  Own_Lock_or_Unlock [72 75 68 54 66 77 69 65 ] 546
+I_L  Own_Lock_or_Unlock [72 82 68 69 79 84 74 83 ] 611
 
 S_L  Load [0 0 0 0 0 0 0 0 ] 0
 S_L  Ifetch [0 0 0 0 0 0 0 0 ] 0
 S_L  Store [0 0 0 0 0 0 0 0 ] 0
 S_L  Atomic [0 0 0 0 0 0 0 0 ] 0
-S_L  L1_Replacement [0 32 14 9 5 4 36 16 ] 116
+S_L  L1_Replacement [3 16 7 0 8 10 1 10 ] 55
 S_L  Data_Shared [0 0 0 0 0 0 0 0 ] 0
 S_L  Data_Owner [0 0 0 0 0 0 0 0 ] 0
 S_L  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
@@ -733,29 +727,29 @@ S_L  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
 S_L  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 S_L  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 S_L  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
-S_L  Persistent_GETS [8 9 6 7 0 0 3 7 ] 40
+S_L  Persistent_GETS [7 4 7 8 0 3 6 1 ] 36
 S_L  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-S_L  Own_Lock_or_Unlock [57 64 53 54 58 55 51 51 ] 443
+S_L  Own_Lock_or_Unlock [49 39 39 44 42 38 56 36 ] 343
 
 IM_L  Load [0 0 0 0 0 0 0 0 ] 0
 IM_L  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IM_L  Store [0 0 0 0 0 0 0 0 ] 0
 IM_L  Atomic [0 0 0 0 0 0 0 0 ] 0
-IM_L  L1_Replacement [1324 1203 1265 1139 949 800 1068 1198 ] 8946
+IM_L  L1_Replacement [1075 981 1271 1397 864 1093 964 890 ] 8535
 IM_L  Data_Shared [0 0 0 0 0 0 0 0 ] 0
 IM_L  Data_Owner [0 0 0 0 0 0 0 0 ] 0
-IM_L  Data_All_Tokens [0 2 0 0 1 0 0 0 ] 3
+IM_L  Data_All_Tokens [1 0 1 1 0 0 1 0 ] 4
 IM_L  Ack [0 0 0 0 0 0 0 0 ] 0
 IM_L  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-IM_L  Transient_Local_GETX [0 0 0 0 0 0 1 0 ] 1
+IM_L  Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
 IM_L  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-IM_L  Transient_Local_GETS [0 0 1 0 0 0 1 1 ] 3
+IM_L  Transient_Local_GETS [0 0 0 0 0 0 0 1 ] 1
 IM_L  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 IM_L  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-IM_L  Persistent_GETX [10 17 13 21 0 0 3 10 ] 74
-IM_L  Persistent_GETS [29 21 28 30 1 6 6 17 ] 138
-IM_L  Own_Lock_or_Unlock [186 190 194 198 147 155 187 155 ] 1412
-IM_L  Request_Timeout [1228 1042 1147 1157 934 789 1235 918 ] 8450
+IM_L  Persistent_GETX [9 17 7 17 0 4 4 5 ] 63
+IM_L  Persistent_GETS [19 15 32 38 0 6 12 15 ] 137
+IM_L  Own_Lock_or_Unlock [177 192 180 202 152 183 167 167 ] 1420
+IM_L  Request_Timeout [1324 944 1204 1019 734 1314 835 879 ] 8253
 
 SM_L  Load [0 0 0 0 0 0 0 0 ] 0
 SM_L  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -782,21 +776,21 @@ IS_L  Load [0 0 0 0 0 0 0 0 ] 0
 IS_L  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IS_L  Store [0 0 0 0 0 0 0 0 ] 0
 IS_L  Atomic [0 0 0 0 0 0 0 0 ] 0
-IS_L  L1_Replacement [2333 1922 2073 2176 1449 1940 1847 1902 ] 15642
+IS_L  L1_Replacement [2243 2416 2615 2434 1854 1672 2179 1758 ] 17171
 IS_L  Data_Shared [0 0 0 0 0 0 0 0 ] 0
 IS_L  Data_Owner [0 0 0 0 0 0 0 0 ] 0
-IS_L  Data_All_Tokens [0 0 1 1 1 0 2 3 ] 8
+IS_L  Data_All_Tokens [1 3 2 2 0 0 0 1 ] 9
 IS_L  Ack [0 0 0 0 0 0 0 0 ] 0
 IS_L  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-IS_L  Transient_Local_GETX [0 0 0 1 0 0 0 1 ] 2
+IS_L  Transient_Local_GETX [1 0 0 1 0 0 0 0 ] 2
 IS_L  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-IS_L  Transient_Local_GETS [2 1 0 2 2 0 1 2 ] 10
+IS_L  Transient_Local_GETS [1 2 2 1 2 0 0 0 ] 8
 IS_L  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 IS_L  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-IS_L  Persistent_GETX [15 20 34 26 1 7 14 22 ] 139
-IS_L  Persistent_GETS [44 43 39 55 1 11 17 33 ] 243
-IS_L  Own_Lock_or_Unlock [340 321 332 316 277 282 314 303 ] 2485
-IS_L  Request_Timeout [2982 2031 1459 1769 1888 2009 1795 2512 ] 16445
+IS_L  Persistent_GETX [16 22 40 22 0 7 7 12 ] 126
+IS_L  Persistent_GETS [34 43 61 58 3 13 17 23 ] 252
+IS_L  Own_Lock_or_Unlock [312 331 362 346 304 303 317 295 ] 2570
+IS_L  Request_Timeout [1613 2345 2553 1656 2173 2649 2683 1709 ] 17381
 
 Cache Stats: system.l1_cntrl1.L1IcacheMemory
   system.l1_cntrl1.L1IcacheMemory_total_misses: 0
@@ -807,16 +801,16 @@ Cache Stats: system.l1_cntrl1.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl1.L1DcacheMemory
-  system.l1_cntrl1.L1DcacheMemory_total_misses: 77017
-  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 77017
+  system.l1_cntrl1.L1DcacheMemory_total_misses: 77024
+  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 77024
   system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl1.L1DcacheMemory_request_type_LD:   65.1544%
-  system.l1_cntrl1.L1DcacheMemory_request_type_ST:   34.8456%
+  system.l1_cntrl1.L1DcacheMemory_request_type_LD:   64.9914%
+  system.l1_cntrl1.L1DcacheMemory_request_type_ST:   35.0086%
 
-  system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor:   77017    100%
+  system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor:   77024    100%
 
 Cache Stats: system.l1_cntrl2.L1IcacheMemory
   system.l1_cntrl2.L1IcacheMemory_total_misses: 0
@@ -827,16 +821,16 @@ Cache Stats: system.l1_cntrl2.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl2.L1DcacheMemory
-  system.l1_cntrl2.L1DcacheMemory_total_misses: 76986
-  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76986
+  system.l1_cntrl2.L1DcacheMemory_total_misses: 76693
+  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76693
   system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl2.L1DcacheMemory_request_type_LD:   64.9339%
-  system.l1_cntrl2.L1DcacheMemory_request_type_ST:   35.0661%
+  system.l1_cntrl2.L1DcacheMemory_request_type_LD:   64.9838%
+  system.l1_cntrl2.L1DcacheMemory_request_type_ST:   35.0162%
 
-  system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor:   76986    100%
+  system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor:   76693    100%
 
 Cache Stats: system.l1_cntrl3.L1IcacheMemory
   system.l1_cntrl3.L1IcacheMemory_total_misses: 0
@@ -847,16 +841,16 @@ Cache Stats: system.l1_cntrl3.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl3.L1DcacheMemory
-  system.l1_cntrl3.L1DcacheMemory_total_misses: 77259
-  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 77259
+  system.l1_cntrl3.L1DcacheMemory_total_misses: 76821
+  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 76821
   system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl3.L1DcacheMemory_request_type_LD:   64.7989%
-  system.l1_cntrl3.L1DcacheMemory_request_type_ST:   35.2011%
+  system.l1_cntrl3.L1DcacheMemory_request_type_LD:   64.869%
+  system.l1_cntrl3.L1DcacheMemory_request_type_ST:   35.131%
 
-  system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor:   77259    100%
+  system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor:   76821    100%
 
 Cache Stats: system.l1_cntrl4.L1IcacheMemory
   system.l1_cntrl4.L1IcacheMemory_total_misses: 0
@@ -867,16 +861,16 @@ Cache Stats: system.l1_cntrl4.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl4.L1DcacheMemory
-  system.l1_cntrl4.L1DcacheMemory_total_misses: 76585
-  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 76585
+  system.l1_cntrl4.L1DcacheMemory_total_misses: 76700
+  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 76700
   system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl4.L1DcacheMemory_request_type_LD:   64.8717%
-  system.l1_cntrl4.L1DcacheMemory_request_type_ST:   35.1283%
+  system.l1_cntrl4.L1DcacheMemory_request_type_LD:   65.2581%
+  system.l1_cntrl4.L1DcacheMemory_request_type_ST:   34.7419%
 
-  system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor:   76585    100%
+  system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor:   76700    100%
 
 Cache Stats: system.l1_cntrl5.L1IcacheMemory
   system.l1_cntrl5.L1IcacheMemory_total_misses: 0
@@ -887,16 +881,16 @@ Cache Stats: system.l1_cntrl5.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl5.L1DcacheMemory
-  system.l1_cntrl5.L1DcacheMemory_total_misses: 76776
-  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 76776
+  system.l1_cntrl5.L1DcacheMemory_total_misses: 76894
+  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 76894
   system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl5.L1DcacheMemory_request_type_LD:   65.1063%
-  system.l1_cntrl5.L1DcacheMemory_request_type_ST:   34.8937%
+  system.l1_cntrl5.L1DcacheMemory_request_type_LD:   64.823%
+  system.l1_cntrl5.L1DcacheMemory_request_type_ST:   35.177%
 
-  system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor:   76776    100%
+  system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor:   76894    100%
 
 Cache Stats: system.l1_cntrl6.L1IcacheMemory
   system.l1_cntrl6.L1IcacheMemory_total_misses: 0
@@ -907,16 +901,16 @@ Cache Stats: system.l1_cntrl6.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl6.L1DcacheMemory
-  system.l1_cntrl6.L1DcacheMemory_total_misses: 76590
-  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 76590
+  system.l1_cntrl6.L1DcacheMemory_total_misses: 76988
+  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 76988
   system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl6.L1DcacheMemory_request_type_LD:   64.7839%
-  system.l1_cntrl6.L1DcacheMemory_request_type_ST:   35.2161%
+  system.l1_cntrl6.L1DcacheMemory_request_type_LD:   64.9322%
+  system.l1_cntrl6.L1DcacheMemory_request_type_ST:   35.0678%
 
-  system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor:   76590    100%
+  system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor:   76988    100%
 
 Cache Stats: system.l1_cntrl7.L1IcacheMemory
   system.l1_cntrl7.L1IcacheMemory_total_misses: 0
@@ -927,63 +921,63 @@ Cache Stats: system.l1_cntrl7.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl7.L1DcacheMemory
-  system.l1_cntrl7.L1DcacheMemory_total_misses: 77094
-  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 77094
+  system.l1_cntrl7.L1DcacheMemory_total_misses: 77015
+  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 77015
   system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl7.L1DcacheMemory_request_type_LD:   64.913%
-  system.l1_cntrl7.L1DcacheMemory_request_type_ST:   35.087%
+  system.l1_cntrl7.L1DcacheMemory_request_type_LD:   65.0614%
+  system.l1_cntrl7.L1DcacheMemory_request_type_ST:   34.9386%
 
-  system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor:   77094    100%
+  system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor:   77015    100%
 
 Cache Stats: system.l2_cntrl0.L2cacheMemory
-  system.l2_cntrl0.L2cacheMemory_total_misses: 613969
-  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 613969
+  system.l2_cntrl0.L2cacheMemory_total_misses: 614008
+  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 614008
   system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l2_cntrl0.L2cacheMemory_request_type_GETS:   64.9684%
-  system.l2_cntrl0.L2cacheMemory_request_type_GETX:   35.0316%
+  system.l2_cntrl0.L2cacheMemory_request_type_GETS:   64.9635%
+  system.l2_cntrl0.L2cacheMemory_request_type_GETX:   35.0365%
 
-  system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   613969    100%
+  system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   614008    100%
 
  --- L2Cache ---
  - Event Counts -
-L1_GETS [399854 ] 399854
-L1_GETS_Last_Token [2 ] 2
-L1_GETX [215639 ] 215639
-L1_INV [1833 ] 1833
+L1_GETS [399838 ] 399838
+L1_GETS_Last_Token [1 ] 1
+L1_GETX [215688 ] 215688
+L1_INV [1919 ] 1919
 Transient_GETX [0 ] 0
 Transient_GETS [0 ] 0
 Transient_GETS_Last_Token [0 ] 0
-L2_Replacement [610216 ] 610216
+L2_Replacement [610254 ] 610254
 Writeback_Tokens [0 ] 0
-Writeback_Shared_Data [1536 ] 1536
-Writeback_All_Tokens [610964 ] 610964
-Writeback_Owned [1130 ] 1130
+Writeback_Shared_Data [1540 ] 1540
+Writeback_All_Tokens [610986 ] 610986
+Writeback_Owned [1050 ] 1050
 Data_Shared [0 ] 0
 Data_Owner [0 ] 0
 Data_All_Tokens [0 ] 0
 Ack [0 ] 0
 Ack_All_Tokens [0 ] 0
-Persistent_GETX [72354 ] 72354
-Persistent_GETS [133978 ] 133978
-Persistent_GETS_Last_Token [2 ] 2
-Own_Lock_or_Unlock [204096 ] 204096
+Persistent_GETX [72096 ] 72096
+Persistent_GETS [133613 ] 133613
+Persistent_GETS_Last_Token [1 ] 1
+Own_Lock_or_Unlock [203486 ] 203486
 
  - Transitions -
-NP  L1_GETS [398076 ] 398076
-NP  L1_GETX [214623 ] 214623
-NP  L1_INV [1288 ] 1288
+NP  L1_GETS [398004 ] 398004
+NP  L1_GETX [214650 ] 214650
+NP  L1_INV [1310 ] 1310
 NP  Transient_GETX [0 ] 0
 NP  Transient_GETS [0 ] 0
 NP  Writeback_Tokens [0 ] 0
-NP  Writeback_Shared_Data [1529 ] 1529
-NP  Writeback_All_Tokens [607613 ] 607613
-NP  Writeback_Owned [1082 ] 1082
+NP  Writeback_Shared_Data [1535 ] 1535
+NP  Writeback_All_Tokens [607716 ] 607716
+NP  Writeback_Owned [1011 ] 1011
 NP  Data_Shared [0 ] 0
 NP  Data_Owner [0 ] 0
 NP  Data_All_Tokens [0 ] 0
@@ -991,19 +985,19 @@ NP  Ack [0 ] 0
 NP  Persistent_GETX [0 ] 0
 NP  Persistent_GETS [0 ] 0
 NP  Persistent_GETS_Last_Token [0 ] 0
-NP  Own_Lock_or_Unlock [203275 ] 203275
+NP  Own_Lock_or_Unlock [202659 ] 202659
 
-I  L1_GETS [1 ] 1
+I  L1_GETS [0 ] 0
 I  L1_GETS_Last_Token [0 ] 0
 I  L1_GETX [0 ] 0
-I  L1_INV [1 ] 1
+I  L1_INV [0 ] 0
 I  Transient_GETX [0 ] 0
 I  Transient_GETS [0 ] 0
 I  Transient_GETS_Last_Token [0 ] 0
-I  L2_Replacement [533 ] 533
+I  L2_Replacement [522 ] 522
 I  Writeback_Tokens [0 ] 0
 I  Writeback_Shared_Data [1 ] 1
-I  Writeback_All_Tokens [846 ] 846
+I  Writeback_All_Tokens [864 ] 864
 I  Writeback_Owned [0 ] 0
 I  Data_Shared [0 ] 0
 I  Data_Owner [0 ] 0
@@ -1015,74 +1009,74 @@ I  Persistent_GETS_Last_Token [0 ] 0
 I  Own_Lock_or_Unlock [0 ] 0
 
 S  L1_GETS [1 ] 1
-S  L1_GETS_Last_Token [2 ] 2
+S  L1_GETS_Last_Token [1 ] 1
 S  L1_GETX [1 ] 1
 S  L1_INV [0 ] 0
 S  Transient_GETX [0 ] 0
 S  Transient_GETS [0 ] 0
 S  Transient_GETS_Last_Token [0 ] 0
-S  L2_Replacement [1276 ] 1276
+S  L2_Replacement [1281 ] 1281
 S  Writeback_Tokens [0 ] 0
-S  Writeback_Shared_Data [0 ] 0
-S  Writeback_All_Tokens [248 ] 248
-S  Writeback_Owned [1 ] 1
+S  Writeback_Shared_Data [2 ] 2
+S  Writeback_All_Tokens [251 ] 251
+S  Writeback_Owned [4 ] 4
 S  Data_Shared [0 ] 0
 S  Data_Owner [0 ] 0
 S  Data_All_Tokens [0 ] 0
 S  Ack [0 ] 0
 S  Persistent_GETX [0 ] 0
 S  Persistent_GETS [0 ] 0
-S  Persistent_GETS_Last_Token [2 ] 2
+S  Persistent_GETS_Last_Token [1 ] 1
 S  Own_Lock_or_Unlock [0 ] 0
 
-O  L1_GETS [4 ] 4
+O  L1_GETS [2 ] 2
 O  L1_GETS_Last_Token [0 ] 0
 O  L1_GETX [0 ] 0
 O  L1_INV [0 ] 0
 O  Transient_GETX [0 ] 0
 O  Transient_GETS [0 ] 0
 O  Transient_GETS_Last_Token [0 ] 0
-O  L2_Replacement [1234 ] 1234
+O  L2_Replacement [1255 ] 1255
 O  Writeback_Tokens [0 ] 0
-O  Writeback_Shared_Data [5 ] 5
-O  Writeback_All_Tokens [812 ] 812
+O  Writeback_Shared_Data [2 ] 2
+O  Writeback_All_Tokens [710 ] 710
 O  Data_Shared [0 ] 0
 O  Data_All_Tokens [0 ] 0
 O  Ack [0 ] 0
 O  Ack_All_Tokens [0 ] 0
-O  Persistent_GETX [0 ] 0
-O  Persistent_GETS [0 ] 0
+O  Persistent_GETX [1 ] 1
+O  Persistent_GETS [3 ] 3
 O  Persistent_GETS_Last_Token [0 ] 0
 O  Own_Lock_or_Unlock [0 ] 0
 
-M  L1_GETS [963 ] 963
-M  L1_GETX [556 ] 556
+M  L1_GETS [954 ] 954
+M  L1_GETX [561 ] 561
 M  L1_INV [0 ] 0
 M  Transient_GETX [0 ] 0
 M  Transient_GETS [0 ] 0
-M  L2_Replacement [606686 ] 606686
-M  Persistent_GETX [487 ] 487
-M  Persistent_GETS [819 ] 819
+M  L2_Replacement [606691 ] 606691
+M  Persistent_GETX [443 ] 443
+M  Persistent_GETS [884 ] 884
 M  Own_Lock_or_Unlock [0 ] 0
 
-I_L  L1_GETS [809 ] 809
-I_L  L1_GETX [459 ] 459
-I_L  L1_INV [544 ] 544
+I_L  L1_GETS [877 ] 877
+I_L  L1_GETX [476 ] 476
+I_L  L1_INV [609 ] 609
 I_L  Transient_GETX [0 ] 0
 I_L  Transient_GETS [0 ] 0
 I_L  Transient_GETS_Last_Token [0 ] 0
-I_L  L2_Replacement [485 ] 485
+I_L  L2_Replacement [504 ] 504
 I_L  Writeback_Tokens [0 ] 0
-I_L  Writeback_Shared_Data [1 ] 1
+I_L  Writeback_Shared_Data [0 ] 0
 I_L  Writeback_All_Tokens [1445 ] 1445
-I_L  Writeback_Owned [47 ] 47
+I_L  Writeback_Owned [34 ] 34
 I_L  Data_Shared [0 ] 0
 I_L  Data_Owner [0 ] 0
 I_L  Data_All_Tokens [0 ] 0
 I_L  Ack [0 ] 0
-I_L  Persistent_GETX [71867 ] 71867
-I_L  Persistent_GETS [133159 ] 133159
-I_L  Own_Lock_or_Unlock [821 ] 821
+I_L  Persistent_GETX [71652 ] 71652
+I_L  Persistent_GETS [132726 ] 132726
+I_L  Own_Lock_or_Unlock [824 ] 824
 
 S_L  L1_GETS [0 ] 0
 S_L  L1_GETS_Last_Token [0 ] 0
@@ -1091,11 +1085,11 @@ S_L  L1_INV [0 ] 0
 S_L  Transient_GETX [0 ] 0
 S_L  Transient_GETS [0 ] 0
 S_L  Transient_GETS_Last_Token [0 ] 0
-S_L  L2_Replacement [2 ] 2
+S_L  L2_Replacement [1 ] 1
 S_L  Writeback_Tokens [0 ] 0
 S_L  Writeback_Shared_Data [0 ] 0
 S_L  Writeback_All_Tokens [0 ] 0
-S_L  Writeback_Owned [0 ] 0
+S_L  Writeback_Owned [1 ] 1
 S_L  Data_Shared [0 ] 0
 S_L  Data_Owner [0 ] 0
 S_L  Data_All_Tokens [0 ] 0
@@ -1103,113 +1097,113 @@ S_L  Ack [0 ] 0
 S_L  Persistent_GETX [0 ] 0
 S_L  Persistent_GETS [0 ] 0
 S_L  Persistent_GETS_Last_Token [0 ] 0
-S_L  Own_Lock_or_Unlock [0 ] 0
+S_L  Own_Lock_or_Unlock [3 ] 3
 
 Memory controller: system.dir_cntrl0.memBuffer:
-  memory_total_requests: 823553
-  memory_reads: 608473
-  memory_writes: 215049
-  memory_refreshes: 40955
-  memory_total_request_delays: 49483061
-  memory_delays_per_request: 60.0849
-  memory_delays_in_input_queue: 412614
-  memory_delays_behind_head_of_bank_queue: 20169004
-  memory_delays_stalled_at_head_of_bank_queue: 28901443
-  memory_stalls_for_bank_busy: 4444487
+  memory_total_requests: 823669
+  memory_reads: 608495
+  memory_writes: 215141
+  memory_refreshes: 40970
+  memory_total_request_delays: 49399101
+  memory_delays_per_request: 59.9745
+  memory_delays_in_input_queue: 411894
+  memory_delays_behind_head_of_bank_queue: 20188400
+  memory_delays_stalled_at_head_of_bank_queue: 28798807
+  memory_stalls_for_bank_busy: 4435508
   memory_stalls_for_random_busy: 0
-  memory_stalls_for_anti_starvation: 6925202
-  memory_stalls_for_arbitration: 5968951
-  memory_stalls_for_bus: 8105541
+  memory_stalls_for_anti_starvation: 6882411
+  memory_stalls_for_arbitration: 5945554
+  memory_stalls_for_bus: 8083401
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 2060025
-  memory_stalls_for_read_read_turnaround: 1397237
-  accesses_per_bank: 25898  25514  25666  25899  25982  25832  26034  25723  25946  25743  25754  25919  25502  25605  25766  25591  25671  25693  25738  25726  25790  25650  25833  25622  25617  25329  25704  25328  25634  25911  26070  25863  
+  memory_stalls_for_read_write_turnaround: 2055519
+  memory_stalls_for_read_read_turnaround: 1396414
+  accesses_per_bank: 25915  25519  25693  25866  25936  25821  26007  25777  25934  25745  25819  25922  25509  25555  25730  25568  25729  25737  25756  25703  25805  25671  25858  25625  25624  25316  25682  25315  25693  25911  26065  25863  
 
  --- Directory ---
  - Event Counts -
-GETX [402036 ] 402036
-GETS [737914 ] 737914
-Lockdown [206334 ] 206334
-Unlockdown [204096 ] 204096
+GETX [396726 ] 396726
+GETS [740556 ] 740556
+Lockdown [205710 ] 205710
+Unlockdown [203486 ] 203486
 Own_Lock_or_Unlock [0 ] 0
 Own_Lock_or_Unlock_Tokens [0 ] 0
-Data_Owner [210 ] 210
-Data_All_Tokens [214914 ] 214914
-Ack_Owner [665 ] 665
-Ack_Owner_All_Tokens [392751 ] 392751
-Tokens [512 ] 512
-Ack_All_Tokens [8723 ] 8723
+Data_Owner [205 ] 205
+Data_All_Tokens [214974 ] 214974
+Ack_Owner [695 ] 695
+Ack_Owner_All_Tokens [392649 ] 392649
+Tokens [449 ] 449
+Ack_All_Tokens [8751 ] 8751
 Request_Timeout [0 ] 0
-Memory_Data [608472 ] 608472
-Memory_Ack [215045 ] 215045
+Memory_Data [608491 ] 608491
+Memory_Ack [215141 ] 215141
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
 DMA_WRITE_All_Tokens [0 ] 0
 
  - Transitions -
-O  GETX [211925 ] 211925
-O  GETS [393078 ] 393078
-O  Lockdown [1855 ] 1855
+O  GETX [211966 ] 211966
+O  GETS [393002 ] 393002
+O  Lockdown [1895 ] 1895
 O  Unlockdown [0 ] 0
 O  Own_Lock_or_Unlock [0 ] 0
 O  Own_Lock_or_Unlock_Tokens [0 ] 0
 O  Data_Owner [0 ] 0
-O  Data_All_Tokens [1 ] 1
+O  Data_All_Tokens [0 ] 0
 O  Tokens [1 ] 1
-O  Ack_All_Tokens [867 ] 867
+O  Ack_All_Tokens [889 ] 889
 O  DMA_READ [0 ] 0
 O  DMA_WRITE [0 ] 0
 O  DMA_WRITE_All_Tokens [0 ] 0
 
-NO  GETX [1680 ] 1680
-NO  GETS [3187 ] 3187
-NO  Lockdown [8635 ] 8635
+NO  GETX [1693 ] 1693
+NO  GETS [3156 ] 3156
+NO  Lockdown [8727 ] 8727
 NO  Unlockdown [0 ] 0
 NO  Own_Lock_or_Unlock [0 ] 0
 NO  Own_Lock_or_Unlock_Tokens [0 ] 0
-NO  Data_Owner [210 ] 210
-NO  Data_All_Tokens [214850 ] 214850
-NO  Ack_Owner [665 ] 665
-NO  Ack_Owner_All_Tokens [392729 ] 392729
-NO  Tokens [410 ] 410
+NO  Data_Owner [205 ] 205
+NO  Data_All_Tokens [214949 ] 214949
+NO  Ack_Owner [695 ] 695
+NO  Ack_Owner_All_Tokens [392626 ] 392626
+NO  Tokens [392 ] 392
 NO  DMA_READ [0 ] 0
 NO  DMA_WRITE [0 ] 0
 
-L  GETX [1478 ] 1478
-L  GETS [2620 ] 2620
-L  Lockdown [1289 ] 1289
-L  Unlockdown [204096 ] 204096
+L  GETX [1468 ] 1468
+L  GETS [2722 ] 2722
+L  Lockdown [1284 ] 1284
+L  Unlockdown [203486 ] 203486
 L  Own_Lock_or_Unlock [0 ] 0
 L  Own_Lock_or_Unlock_Tokens [0 ] 0
 L  Data_Owner [0 ] 0
-L  Data_All_Tokens [18 ] 18
+L  Data_All_Tokens [25 ] 25
 L  Ack_Owner [0 ] 0
-L  Ack_Owner_All_Tokens [22 ] 22
+L  Ack_Owner_All_Tokens [23 ] 23
 L  Tokens [2 ] 2
 L  DMA_READ [0 ] 0
 L  DMA_WRITE [0 ] 0
 L  DMA_WRITE_All_Tokens [0 ] 0
 
-O_W  GETX [47833 ] 47833
-O_W  GETS [90041 ] 90041
-O_W  Lockdown [1635 ] 1635
+O_W  GETX [48157 ] 48157
+O_W  GETS [90657 ] 90657
+O_W  Lockdown [1652 ] 1652
 O_W  Unlockdown [0 ] 0
 O_W  Own_Lock_or_Unlock [0 ] 0
 O_W  Own_Lock_or_Unlock_Tokens [0 ] 0
 O_W  Data_Owner [0 ] 0
-O_W  Data_All_Tokens [45 ] 45
+O_W  Data_All_Tokens [0 ] 0
 O_W  Ack_Owner [0 ] 0
-O_W  Tokens [99 ] 99
-O_W  Ack_All_Tokens [7756 ] 7756
+O_W  Tokens [54 ] 54
+O_W  Ack_All_Tokens [7620 ] 7620
 O_W  Memory_Data [0 ] 0
-O_W  Memory_Ack [213410 ] 213410
+O_W  Memory_Ack [213489 ] 213489
 O_W  DMA_READ [0 ] 0
 O_W  DMA_WRITE [0 ] 0
 O_W  DMA_WRITE_All_Tokens [0 ] 0
 
-L_O_W  GETX [46215 ] 46215
-L_O_W  GETS [84470 ] 84470
-L_O_W  Lockdown [45 ] 45
+L_O_W  GETX [41565 ] 41565
+L_O_W  GETS [77934 ] 77934
+L_O_W  Lockdown [23 ] 23
 L_O_W  Unlockdown [0 ] 0
 L_O_W  Own_Lock_or_Unlock [0 ] 0
 L_O_W  Own_Lock_or_Unlock_Tokens [0 ] 0
@@ -1217,16 +1211,16 @@ L_O_W  Data_Owner [0 ] 0
 L_O_W  Data_All_Tokens [0 ] 0
 L_O_W  Ack_Owner [0 ] 0
 L_O_W  Tokens [0 ] 0
-L_O_W  Ack_All_Tokens [88 ] 88
-L_O_W  Memory_Data [3490 ] 3490
-L_O_W  Memory_Ack [1635 ] 1635
+L_O_W  Ack_All_Tokens [92 ] 92
+L_O_W  Memory_Data [3546 ] 3546
+L_O_W  Memory_Ack [1652 ] 1652
 L_O_W  DMA_READ [0 ] 0
 L_O_W  DMA_WRITE [0 ] 0
 L_O_W  DMA_WRITE_All_Tokens [0 ] 0
 
-L_NO_W  GETX [42129 ] 42129
-L_NO_W  GETS [75055 ] 75055
-L_NO_W  Lockdown [898 ] 898
+L_NO_W  GETX [43001 ] 43001
+L_NO_W  GETS [81958 ] 81958
+L_NO_W  Lockdown [911 ] 911
 L_NO_W  Unlockdown [0 ] 0
 L_NO_W  Own_Lock_or_Unlock [0 ] 0
 L_NO_W  Own_Lock_or_Unlock_Tokens [0 ] 0
@@ -1234,8 +1228,8 @@ L_NO_W  Data_Owner [0 ] 0
 L_NO_W  Data_All_Tokens [0 ] 0
 L_NO_W  Ack_Owner [0 ] 0
 L_NO_W  Tokens [0 ] 0
-L_NO_W  Ack_All_Tokens [12 ] 12
-L_NO_W  Memory_Data [191972 ] 191972
+L_NO_W  Ack_All_Tokens [33 ] 33
+L_NO_W  Memory_Data [191213 ] 191213
 L_NO_W  DMA_READ [0 ] 0
 L_NO_W  DMA_WRITE [0 ] 0
 L_NO_W  DMA_WRITE_All_Tokens [0 ] 0
@@ -1274,9 +1268,9 @@ DW_L_W  DMA_READ [0 ] 0
 DW_L_W  DMA_WRITE [0 ] 0
 DW_L_W  DMA_WRITE_All_Tokens [0 ] 0
 
-NO_W  GETX [50776 ] 50776
-NO_W  GETS [89463 ] 89463
-NO_W  Lockdown [191977 ] 191977
+NO_W  GETX [48876 ] 48876
+NO_W  GETS [91127 ] 91127
+NO_W  Lockdown [191218 ] 191218
 NO_W  Unlockdown [0 ] 0
 NO_W  Own_Lock_or_Unlock [0 ] 0
 NO_W  Own_Lock_or_Unlock_Tokens [0 ] 0
@@ -1284,8 +1278,8 @@ NO_W  Data_Owner [0 ] 0
 NO_W  Data_All_Tokens [0 ] 0
 NO_W  Ack_Owner [0 ] 0
 NO_W  Tokens [0 ] 0
-NO_W  Ack_All_Tokens [0 ] 0
-NO_W  Memory_Data [413010 ] 413010
+NO_W  Ack_All_Tokens [117 ] 117
+NO_W  Memory_Data [413732 ] 413732
 NO_W  DMA_READ [0 ] 0
 NO_W  DMA_WRITE [0 ] 0
 NO_W  DMA_WRITE_All_Tokens [0 ] 0
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
index 5a17811d1..88920eb84 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
@@ -1,74 +1,74 @@
-system.cpu1: completed 10000 read, 5259 write accesses @1943940
-system.cpu2: completed 10000 read, 5332 write accesses @1962761
-system.cpu3: completed 10000 read, 5358 write accesses @1964980
-system.cpu7: completed 10000 read, 5453 write accesses @1976539
-system.cpu4: completed 10000 read, 5456 write accesses @1987569
-system.cpu5: completed 10000 read, 5433 write accesses @1990190
-system.cpu6: completed 10000 read, 5519 write accesses @1993800
-system.cpu0: completed 10000 read, 5421 write accesses @2013689
-system.cpu2: completed 20000 read, 10590 write accesses @3882080
-system.cpu5: completed 20000 read, 10671 write accesses @3928400
-system.cpu7: completed 20000 read, 10790 write accesses @3932180
-system.cpu1: completed 20000 read, 10547 write accesses @3932310
-system.cpu0: completed 20000 read, 10834 write accesses @3948113
-system.cpu6: completed 20000 read, 10955 write accesses @3962050
-system.cpu3: completed 20000 read, 10821 write accesses @3971009
-system.cpu4: completed 20000 read, 10681 write accesses @3977300
-system.cpu2: completed 30000 read, 16006 write accesses @5865020
-system.cpu1: completed 30000 read, 15879 write accesses @5876820
-system.cpu7: completed 30000 read, 16218 write accesses @5900140
-system.cpu5: completed 30000 read, 15930 write accesses @5906200
-system.cpu0: completed 30000 read, 16190 write accesses @5930280
-system.cpu4: completed 30000 read, 16199 write accesses @5936740
-system.cpu3: completed 30000 read, 16401 write accesses @5958400
-system.cpu6: completed 30000 read, 16369 write accesses @5969590
-system.cpu2: completed 40000 read, 21434 write accesses @7815170
-system.cpu7: completed 40000 read, 21668 write accesses @7856120
-system.cpu1: completed 40000 read, 21296 write accesses @7859890
-system.cpu5: completed 40000 read, 21183 write accesses @7885749
-system.cpu0: completed 40000 read, 21572 write accesses @7901159
-system.cpu6: completed 40000 read, 21926 write accesses @7959459
-system.cpu3: completed 40000 read, 21755 write accesses @7975160
-system.cpu4: completed 40000 read, 21520 write accesses @8005850
-system.cpu2: completed 50000 read, 26840 write accesses @9789230
-system.cpu1: completed 50000 read, 26675 write accesses @9813220
-system.cpu0: completed 50000 read, 26961 write accesses @9857191
-system.cpu7: completed 50000 read, 27124 write accesses @9870470
-system.cpu5: completed 50000 read, 26683 write accesses @9908920
-system.cpu3: completed 50000 read, 27202 write accesses @9939500
-system.cpu6: completed 50000 read, 27538 write accesses @10014701
-system.cpu4: completed 50000 read, 26958 write accesses @10027591
-system.cpu2: completed 60000 read, 32206 write accesses @11734940
-system.cpu1: completed 60000 read, 32043 write accesses @11782013
-system.cpu5: completed 60000 read, 31930 write accesses @11824240
-system.cpu7: completed 60000 read, 32526 write accesses @11842030
-system.cpu0: completed 60000 read, 32219 write accesses @11858030
-system.cpu3: completed 60000 read, 32666 write accesses @11893660
-system.cpu6: completed 60000 read, 32876 write accesses @11988610
-system.cpu4: completed 60000 read, 32390 write accesses @11997042
-system.cpu2: completed 70000 read, 37578 write accesses @13743359
-system.cpu5: completed 70000 read, 37050 write accesses @13756570
-system.cpu1: completed 70000 read, 37370 write accesses @13758070
-system.cpu0: completed 70000 read, 37494 write accesses @13761040
-system.cpu7: completed 70000 read, 37955 write accesses @13842700
-system.cpu3: completed 70000 read, 38057 write accesses @13861012
-system.cpu4: completed 70000 read, 37766 write accesses @13960260
-system.cpu6: completed 70000 read, 38323 write accesses @14032912
-system.cpu2: completed 80000 read, 42857 write accesses @15688757
-system.cpu0: completed 80000 read, 42870 write accesses @15694240
-system.cpu5: completed 80000 read, 42300 write accesses @15735600
-system.cpu1: completed 80000 read, 42715 write accesses @15772000
-system.cpu7: completed 80000 read, 43184 write accesses @15806450
-system.cpu3: completed 80000 read, 43353 write accesses @15812610
-system.cpu4: completed 80000 read, 43208 write accesses @15920280
-system.cpu6: completed 80000 read, 43672 write accesses @16021870
-system.cpu0: completed 90000 read, 48147 write accesses @17663030
-system.cpu2: completed 90000 read, 48318 write accesses @17663170
-system.cpu1: completed 90000 read, 47923 write accesses @17705777
-system.cpu5: completed 90000 read, 47730 write accesses @17748050
-system.cpu7: completed 90000 read, 48616 write accesses @17754820
-system.cpu3: completed 90000 read, 48969 write accesses @17819630
-system.cpu4: completed 90000 read, 48647 write accesses @17880960
-system.cpu6: completed 90000 read, 49180 write accesses @18069050
-system.cpu0: completed 100000 read, 53504 write accesses @19658320
+system.cpu4: completed 10000 read, 5358 write accesses @1929263
+system.cpu0: completed 10000 read, 5517 write accesses @1938193
+system.cpu6: completed 10000 read, 5282 write accesses @1960370
+system.cpu2: completed 10000 read, 5370 write accesses @1983069
+system.cpu3: completed 10000 read, 5219 write accesses @1986540
+system.cpu5: completed 10000 read, 5534 write accesses @2010490
+system.cpu1: completed 10000 read, 5481 write accesses @2016799
+system.cpu7: completed 10000 read, 5483 write accesses @2027000
+system.cpu0: completed 20000 read, 10906 write accesses @3889460
+system.cpu6: completed 20000 read, 10539 write accesses @3890430
+system.cpu4: completed 20000 read, 10737 write accesses @3908329
+system.cpu2: completed 20000 read, 10719 write accesses @3939180
+system.cpu3: completed 20000 read, 10494 write accesses @3943600
+system.cpu5: completed 20000 read, 10848 write accesses @3948219
+system.cpu1: completed 20000 read, 10769 write accesses @4005719
+system.cpu7: completed 20000 read, 10891 write accesses @4012914
+system.cpu6: completed 30000 read, 15919 write accesses @5839330
+system.cpu4: completed 30000 read, 15999 write accesses @5874900
+system.cpu0: completed 30000 read, 16423 write accesses @5898830
+system.cpu5: completed 30000 read, 16404 write accesses @5936061
+system.cpu1: completed 30000 read, 16153 write accesses @5948410
+system.cpu7: completed 30000 read, 16256 write accesses @5950050
+system.cpu2: completed 30000 read, 16157 write accesses @5958790
+system.cpu3: completed 30000 read, 15885 write accesses @5959680
+system.cpu4: completed 40000 read, 21342 write accesses @7808600
+system.cpu6: completed 40000 read, 21196 write accesses @7836451
+system.cpu0: completed 40000 read, 21854 write accesses @7880130
+system.cpu1: completed 40000 read, 21631 write accesses @7920239
+system.cpu7: completed 40000 read, 21703 write accesses @7933959
+system.cpu5: completed 40000 read, 21772 write accesses @7955069
+system.cpu3: completed 40000 read, 21372 write accesses @7959100
+system.cpu2: completed 40000 read, 21557 write accesses @7981970
+system.cpu6: completed 50000 read, 26595 write accesses @9809169
+system.cpu4: completed 50000 read, 26864 write accesses @9817559
+system.cpu7: completed 50000 read, 27042 write accesses @9902500
+system.cpu0: completed 50000 read, 27271 write accesses @9906269
+system.cpu1: completed 50000 read, 27124 write accesses @9934930
+system.cpu3: completed 50000 read, 26755 write accesses @9946640
+system.cpu5: completed 50000 read, 27198 write accesses @9946679
+system.cpu2: completed 50000 read, 27060 write accesses @9974740
+system.cpu6: completed 60000 read, 32039 write accesses @11769919
+system.cpu4: completed 60000 read, 32173 write accesses @11822509
+system.cpu1: completed 60000 read, 32379 write accesses @11844429
+system.cpu0: completed 60000 read, 32699 write accesses @11852900
+system.cpu7: completed 60000 read, 32457 write accesses @11873181
+system.cpu5: completed 60000 read, 32557 write accesses @11887270
+system.cpu3: completed 60000 read, 32167 write accesses @11912630
+system.cpu2: completed 60000 read, 32437 write accesses @11967610
+system.cpu4: completed 70000 read, 37476 write accesses @13774590
+system.cpu1: completed 70000 read, 37764 write accesses @13776500
+system.cpu6: completed 70000 read, 37423 write accesses @13811110
+system.cpu0: completed 70000 read, 38112 write accesses @13822360
+system.cpu7: completed 70000 read, 37768 write accesses @13852100
+system.cpu3: completed 70000 read, 37356 write accesses @13890992
+system.cpu5: completed 70000 read, 38000 write accesses @13891330
+system.cpu2: completed 70000 read, 37653 write accesses @13903529
+system.cpu4: completed 80000 read, 42652 write accesses @15714260
+system.cpu1: completed 80000 read, 43161 write accesses @15743660
+system.cpu0: completed 80000 read, 43377 write accesses @15747360
+system.cpu6: completed 80000 read, 42650 write accesses @15761321
+system.cpu7: completed 80000 read, 43147 write accesses @15846829
+system.cpu2: completed 80000 read, 42984 write accesses @15878720
+system.cpu3: completed 80000 read, 42913 write accesses @15881610
+system.cpu5: completed 80000 read, 43333 write accesses @15910140
+system.cpu4: completed 90000 read, 48050 write accesses @17730480
+system.cpu1: completed 90000 read, 48527 write accesses @17731920
+system.cpu0: completed 90000 read, 48688 write accesses @17739870
+system.cpu6: completed 90000 read, 48114 write accesses @17751610
+system.cpu7: completed 90000 read, 48607 write accesses @17816041
+system.cpu2: completed 90000 read, 48386 write accesses @17847760
+system.cpu3: completed 90000 read, 48361 write accesses @17860389
+system.cpu5: completed 90000 read, 48782 write accesses @17871890
+system.cpu4: completed 100000 read, 53373 write accesses @19665440
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
index 0dc21efd5..7601ab137 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:50:16
-gem5 started Jan 23 2012 04:22:27
-gem5 executing on zizzer
-command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
+gem5 compiled May  8 2012 15:11:25
+gem5 started May  8 2012 15:36:42
+gem5 executing on piton
+command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 19658320 because maximum number of loads reached
+Exiting @ tick 19665440 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
index 6b763036e..d352be3a5 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.019665                       # Nu
 sim_ticks                                    19665440                       # Number of ticks simulated
 final_tick                                   19665440                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 164666                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 347552                       # Number of bytes of host memory used
-host_seconds                                   119.38                       # Real time elapsed on the host
+host_tick_rate                                 119847                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 369752                       # Number of bytes of host memory used
+host_seconds                                   164.09                       # Real time elapsed on the host
 system.physmem.bytes_read                           0                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
index de7170126..34695a208 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem system.funcmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -193,7 +192,7 @@ version=0
 type=RubyDirectoryMemory
 map_levels=4
 numa_high_bit=6
-size=134217728
+size=268435456
 use_map=false
 version=0
 
@@ -228,8 +227,10 @@ size=1024
 start_index_bit=6
 
 [system.funcmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=false
 latency=30
 latency_var=0
 null=false
@@ -742,8 +743,10 @@ version=7
 slave=system.cpu7.test
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
@@ -755,7 +758,7 @@ type=RubySystem
 children=network profiler
 block_size_bytes=64
 clock=1
-mem_size=134217728
+mem_size=268435456
 no_mem_vec=false
 random_seed=1234
 randomization=false
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
index d3a40e0ac..08a16b146 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
@@ -7,8 +7,8 @@ RubySystem config:
   cycle_period: 1
   block_size_bytes: 64
   block_size_bits: 6
-  memory_size_bytes: 134217728
-  memory_size_bits: 27
+  memory_size_bytes: 268435456
+  memory_size_bits: 28
 
 Network Configuration
 ---------------------
@@ -34,29 +34,29 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/04/2012 14:29:53
+Real time: May/08/2012 15:38:42
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 160
-Elapsed_time_in_minutes: 2.66667
-Elapsed_time_in_hours: 0.0444444
-Elapsed_time_in_days: 0.00185185
+Elapsed_time_in_seconds: 131
+Elapsed_time_in_minutes: 2.18333
+Elapsed_time_in_hours: 0.0363889
+Elapsed_time_in_days: 0.0015162
 
-Virtual_time_in_seconds: 160.79
-Virtual_time_in_minutes: 2.67983
-Virtual_time_in_hours:   0.0446639
-Virtual_time_in_days:    0.001861
+Virtual_time_in_seconds: 129.82
+Virtual_time_in_minutes: 2.16367
+Virtual_time_in_hours:   0.0360611
+Virtual_time_in_days:    0.00150255
 
-Ruby_current_time: 19116079
+Ruby_current_time: 19129199
 Ruby_start_time: 0
-Ruby_cycles: 19116079
+Ruby_cycles: 19129199
 
-mbytes_resident: 43.5117
-mbytes_total: 354.867
-resident_ratio: 0.122625
+mbytes_resident: 59.6641
+mbytes_total: 360.938
+resident_ratio: 0.165303
 
-ruby_cycles_executed: [ 19116080 19116080 19116080 19116080 19116080 19116080 19116080 19116080 ]
+ruby_cycles_executed: [ 19129200 19129200 19129200 19129200 19129200 19129200 19129200 19129200 ]
 
 Busy Controller Counts:
 L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
@@ -66,35 +66,35 @@ Directory-0:0
 
 Busy Bank Count:0
 
-sequencer_requests_outstanding: [binsize: 1 max: 16 count: 614570 average: 15.9984 | standard deviation: 0.127042 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 614450 ]
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 615043 average: 15.9984 | standard deviation: 0.126994 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 614923 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 128 max: 18350 count: 614442 average: 3981.53 | standard deviation: 2989.78 | 1907 7019 12665 16541 15742 19140 20959 22230 19207 17080 17998 17060 14460 12997 11622 11229 9707 9001 8837 7331 7037 7060 6936 6302 5630 6165 6165 5733 5588 5325 5586 5582 5526 5744 5305 5564 5863 6226 5864 5550 6129 6480 6314 6511 6516 6820 6777 6993 7318 6574 6909 7222 7526 6978 6340 6986 7199 6566 6478 6155 6463 5912 5673 5627 4908 4847 4730 4633 4101 3433 3594 3457 2967 2780 2446 2453 2028 1942 1892 1470 1365 1274 1260 1026 813 802 743 698 600 536 493 411 386 287 264 228 229 209 161 127 127 117 98 81 63 62 36 37 38 26 31 29 20 13 16 15 11 13 9 9 5 10 5 3 4 6 2 4 0 2 2 0 0 1 0 1 0 1 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 128 max: 18350 count: 399124 average: 3979.99 | standard deviation: 2988.88 | 1240 4533 8195 10754 10269 12478 13588 14402 12431 11054 11651 11148 9445 8400 7655 7292 6305 5886 5799 4766 4559 4600 4478 4147 3658 3989 4064 3681 3601 3408 3670 3623 3613 3706 3428 3618 3823 3956 3776 3620 3993 4222 4120 4179 4244 4475 4398 4561 4743 4338 4565 4631 4856 4542 4070 4548 4691 4306 4226 4002 4137 3857 3663 3562 3211 3164 3046 2970 2700 2215 2355 2306 1904 1785 1598 1605 1303 1276 1178 953 893 822 831 666 529 511 496 433 379 341 315 256 244 180 167 154 162 139 113 85 87 79 66 54 42 44 26 26 25 18 16 20 13 7 12 9 8 9 5 8 1 7 3 2 2 4 1 2 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 128 max: 18350 count: 215318 average: 3984.38 | standard deviation: 2991.46 | 667 2486 4470 5787 5473 6662 7371 7828 6776 6026 6347 5912 5015 4597 3967 3937 3402 3115 3038 2565 2478 2460 2458 2155 1972 2176 2101 2052 1987 1917 1916 1959 1913 2038 1877 1946 2040 2270 2088 1930 2136 2258 2194 2332 2272 2345 2379 2432 2575 2236 2344 2591 2670 2436 2270 2438 2508 2260 2252 2153 2326 2055 2010 2065 1697 1683 1684 1663 1401 1218 1239 1151 1063 995 848 848 725 666 714 517 472 452 429 360 284 291 247 265 221 195 178 155 142 107 97 74 67 70 48 42 40 38 32 27 21 18 10 11 13 8 15 9 7 6 4 6 3 4 4 1 4 3 2 1 2 2 1 2 0 1 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache: [binsize: 1 max: 2 count: 145 average:     2 | standard deviation: 0 | 0 0 145 ]
-miss_latency_L2Cache: [binsize: 32 max: 4732 count: 555 average: 530.014 | standard deviation: 610.685 | 122 25 15 16 13 9 15 14 7 15 12 17 10 11 16 14 21 10 12 8 15 12 7 7 5 2 8 9 4 8 6 9 5 4 2 3 6 4 5 2 3 2 1 2 3 0 2 2 1 1 2 0 2 2 1 0 1 3 1 0 1 2 1 0 0 0 2 0 1 1 1 1 1 0 0 2 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Directory: [binsize: 128 max: 18350 count: 593609 average: 4003.37 | standard deviation: 2988.26 | 0 6237 11905 15728 14902 18438 20399 21630 18706 16670 17622 16698 14182 12731 11356 10995 9476 8767 8612 7136 6831 6850 6762 6117 5466 5974 5985 5566 5409 5140 5399 5394 5345 5555 5114 5363 5644 6012 5652 5341 5913 6258 6087 6285 6270 6591 6561 6761 7056 6328 6693 7009 7272 6769 6138 6788 6963 6353 6309 5966 6279 5744 5537 5491 4764 4738 4624 4533 4015 3343 3520 3380 2907 2713 2391 2398 1982 1911 1854 1451 1330 1247 1237 1012 795 787 729 689 586 518 486 401 375 283 260 225 223 206 157 126 127 114 97 77 62 60 36 36 37 26 30 29 20 13 16 15 10 12 9 9 4 10 5 3 4 6 2 4 0 2 2 0 0 1 0 1 0 1 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache_wCC: [binsize: 128 max: 15385 count: 20133 average: 3461.42 | standard deviation: 2963.37 | 1584 731 709 762 789 661 536 573 487 393 368 355 274 261 261 230 229 230 222 195 206 208 174 184 163 189 180 167 179 185 187 187 181 189 191 201 218 214 212 209 216 222 227 226 246 229 216 232 262 246 216 213 254 209 202 198 236 213 169 189 184 168 136 136 144 109 106 100 86 90 74 77 60 67 55 55 46 31 38 19 35 27 23 14 18 15 14 9 14 18 7 10 11 4 4 3 6 3 4 1 0 3 1 4 1 2 0 1 1 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_wCC_issue_to_initial_request: [binsize: 128 max: 15351 count: 20094 average: 3277.29 | standard deviation: 2943.79 | 2358 828 788 877 739 618 509 510 387 271 295 296 246 207 210 191 206 211 202 173 195 197 193 157 164 169 187 175 198 180 184 186 188 188 191 214 207 224 225 217 234 234 233 232 215 236 227 240 236 229 199 253 242 220 185 189 233 186 164 174 168 141 121 141 118 101 106 99 66 69 65 65 62 58 43 48 30 29 25 20 27 19 13 11 19 14 14 12 10 12 5 7 5 3 4 1 2 2 3 2 1 2 0 2 1 0 0 3 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_wCC_initial_forward_request: [binsize: 32 max: 4197 count: 20094 average: 157.427 | standard deviation: 330.601 | 14389 309 258 265 238 217 214 214 265 190 165 166 213 262 212 191 173 176 151 111 103 103 73 112 79 83 75 73 99 86 62 61 60 52 47 29 44 26 30 34 16 29 33 26 28 19 19 16 17 12 11 17 13 13 8 14 12 6 12 7 4 5 5 1 4 2 6 2 4 2 3 2 0 0 1 0 2 1 0 0 0 0 1 0 2 1 3 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 36 count: 20094 average: 24.6305 | standard deviation: 1.17282 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14623 155 4686 53 185 200 151 18 8 9 2 2 2 ]
-miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 13 count: 20094 average: 1.76023 | standard deviation: 1.58033 | 4572 5207 5248 3155 595 510 640 32 61 36 26 10 0 2 ]
-imcomplete_wCC_Times: 39
-miss_latency_dir_issue_to_initial_request: [binsize: 128 max: 17631 count: 593609 average: 3282.65 | standard deviation: 2953.96 | 71048 23805 22449 26807 20923 17680 15613 15372 11499 8618 8923 8252 6928 6580 6180 6287 5835 5527 5921 5322 5416 5272 5711 5197 4844 5317 5540 5157 5231 5153 5633 5396 5492 5976 5561 5862 6065 6365 6142 5948 6681 7014 6851 6796 6743 7289 6900 6930 7370 6520 6800 6722 7007 6352 5511 6237 5955 5571 5089 4639 4839 4354 4076 3931 3368 3226 3002 2929 2561 2146 2128 1990 1683 1461 1294 1265 1124 1000 905 767 691 620 595 498 411 405 336 310 256 210 180 163 152 132 106 101 87 71 56 48 53 33 23 22 19 21 10 14 8 17 14 10 12 9 3 8 4 5 2 6 3 1 0 3 1 0 3 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_dir_initial_forward_request: [binsize: 16 max: 2913 count: 593609 average: 11.5086 | standard deviation: 54.2704 | 590100 308 39 70 66 73 35 114 95 53 76 54 78 78 37 64 45 57 74 41 57 21 58 48 19 47 26 28 49 30 52 22 61 55 31 54 36 70 53 28 59 23 60 52 27 64 25 33 34 22 32 19 25 25 11 27 8 24 31 13 20 12 25 27 19 29 14 29 24 9 18 9 19 13 7 20 10 14 19 3 17 3 5 3 6 9 5 6 7 3 2 11 4 7 7 8 6 6 5 0 10 3 5 5 2 5 2 5 6 0 5 2 5 4 6 5 0 4 3 2 6 0 2 4 0 1 2 1 3 3 2 1 2 1 1 3 0 1 1 0 0 0 2 2 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 ]
-miss_latency_dir_forward_to_first_response: [binsize: 1 max: 40 count: 593609 average: 24.8344 | standard deviation: 1.28611 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 380894 4962 182637 1567 7848 8354 5839 653 419 263 63 70 34 4 0 1 1 ]
-miss_latency_dir_first_response_to_completion: [binsize: 32 max: 4657 count: 593609 average: 684.377 | standard deviation: 462.221 | 0 0 0 14410 19440 17147 19285 22209 25177 21201 20304 20400 22338 24085 19226 18041 16523 16788 17261 13656 13602 13430 14616 15700 13338 13169 13155 14028 14485 10838 9306 8183 7920 7835 5913 5699 5252 5347 5691 4527 4513 4409 4615 4813 3625 3308 2736 2688 2618 2089 1943 1776 1872 1873 1516 1384 1427 1512 1496 1167 1035 906 898 826 683 649 615 618 607 479 446 442 448 407 310 287 292 247 225 217 184 157 165 154 122 133 116 96 114 80 75 54 44 47 54 50 37 34 36 36 29 22 21 25 23 17 12 16 14 6 8 9 3 10 6 8 5 5 8 5 2 2 5 2 2 2 1 2 1 1 1 2 1 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 128 max: 18900 count: 614915 average: 3981.3 | standard deviation: 2986.1 | 1991 6993 12404 16523 15657 18812 21262 22001 19358 16982 17990 17284 14291 13245 11746 11099 9546 9067 8838 7383 7263 6912 6937 6275 5713 6163 6114 5737 5691 5559 5692 5576 5725 5862 5374 5738 5858 6099 5905 5641 6259 6426 6341 6488 6342 6973 6779 6697 7287 6506 7005 7198 7360 7091 6321 6932 7190 6637 6481 6112 6504 5878 5770 5732 5000 4795 4742 4494 4004 3591 3643 3328 2997 2812 2462 2352 2122 1895 1861 1524 1359 1274 1220 1060 817 870 732 663 569 534 478 366 343 306 232 229 203 170 178 115 119 105 100 72 79 51 44 47 39 35 32 34 33 21 15 16 20 20 9 12 6 9 5 7 4 4 1 4 2 1 3 2 1 2 0 1 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 128 max: 18900 count: 399418 average: 3983.57 | standard deviation: 2986.25 | 1313 4603 7965 10808 10031 12189 13838 14378 12608 10911 11638 11250 9324 8501 7610 7277 6187 5882 5740 4827 4748 4488 4491 4070 3663 3968 4016 3706 3673 3625 3712 3578 3714 3819 3472 3789 3825 3950 3845 3623 4115 4212 4111 4207 4134 4490 4388 4343 4720 4241 4523 4573 4812 4572 4072 4553 4743 4386 4208 3968 4277 3830 3738 3706 3282 3173 3061 2927 2608 2329 2413 2138 1923 1817 1568 1493 1385 1260 1208 974 885 824 832 702 542 580 475 435 347 344 315 245 224 210 158 148 141 101 105 70 74 65 66 47 44 37 29 30 29 21 19 24 19 9 8 9 15 9 4 8 2 5 5 5 3 2 0 2 0 1 0 1 1 1 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 128 max: 17580 count: 215497 average: 3977.07 | standard deviation: 2985.81 | 678 2390 4439 5715 5626 6623 7424 7623 6750 6071 6352 6034 4967 4744 4136 3822 3359 3185 3098 2556 2515 2424 2446 2205 2050 2195 2098 2031 2018 1934 1980 1998 2011 2043 1902 1949 2033 2149 2060 2018 2144 2214 2230 2281 2208 2483 2391 2354 2567 2265 2482 2625 2548 2519 2249 2379 2447 2251 2273 2144 2227 2048 2032 2026 1718 1622 1681 1567 1396 1262 1230 1190 1074 995 894 859 737 635 653 550 474 450 388 358 275 290 257 228 222 190 163 121 119 96 74 81 62 69 73 45 45 40 34 25 35 14 15 17 10 14 13 10 14 12 7 7 5 11 5 4 4 4 0 2 1 2 1 2 2 0 3 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache: [binsize: 1 max: 2 count: 146 average:     2 | standard deviation: 0 | 0 0 146 ]
+miss_latency_L2Cache: [binsize: 32 max: 4896 count: 577 average: 518.646 | standard deviation: 644.572 | 150 22 11 14 10 15 13 14 10 13 10 17 17 13 15 17 16 10 13 10 13 11 12 5 5 6 6 5 4 3 6 7 2 2 6 5 5 5 4 1 3 4 1 1 2 3 2 4 1 0 3 1 0 0 1 0 1 0 2 1 1 1 1 0 0 2 0 0 2 1 1 0 0 0 1 0 0 1 0 2 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Directory: [binsize: 128 max: 18900 count: 594143 average: 4002.99 | standard deviation: 2984.35 | 0 6267 11714 15661 14872 18114 20672 21402 18868 16538 17610 16906 13985 12986 11489 10864 9318 8883 8638 7173 7052 6713 6742 6100 5537 5991 5933 5545 5525 5393 5499 5387 5550 5688 5190 5545 5661 5895 5694 5419 6034 6209 6144 6254 6105 6751 6523 6475 7026 6279 6782 6966 7142 6877 6082 6718 6968 6449 6284 5911 6346 5717 5615 5584 4865 4675 4629 4394 3896 3524 3551 3265 2936 2762 2403 2300 2065 1854 1818 1488 1332 1245 1200 1048 799 855 724 650 554 524 471 364 339 302 225 223 200 169 177 113 119 103 99 69 79 50 41 47 38 34 32 34 33 21 15 14 19 20 8 12 6 9 5 7 4 4 1 4 2 1 3 2 1 2 0 1 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache_wCC: [binsize: 128 max: 15203 count: 20049 average: 3467.17 | standard deviation: 2965.96 | 1648 674 640 800 736 657 568 579 475 429 371 367 301 258 253 232 226 180 199 207 210 198 193 175 175 171 180 191 166 166 191 189 175 174 184 193 197 204 210 222 225 217 197 234 237 222 256 222 261 227 223 232 218 214 239 214 222 188 197 201 158 161 155 148 135 120 113 100 108 67 92 63 61 50 59 52 57 41 43 36 27 29 20 12 18 15 8 13 15 10 7 2 4 4 7 6 3 1 1 2 0 2 1 3 0 1 3 0 1 1 0 0 0 0 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 128 max: 15171 count: 20013 average: 3285.71 | standard deviation: 2948.63 | 2368 814 723 904 678 636 545 508 401 319 300 294 220 208 194 216 192 185 203 167 197 190 187 182 167 169 182 172 171 168 196 182 164 194 192 184 217 204 234 191 223 227 235 230 200 257 261 248 243 231 196 254 209 213 205 223 218 185 190 174 158 152 139 145 113 95 103 86 83 69 66 65 53 42 51 47 40 41 27 24 23 19 16 14 13 11 9 12 7 6 6 6 3 4 3 3 4 1 1 0 0 1 2 2 0 1 2 1 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 32 max: 3522 count: 20013 average: 154.025 | standard deviation: 321.512 | 14313 336 276 277 227 222 194 207 257 178 202 197 189 281 212 180 162 181 147 117 101 97 73 124 81 77 57 76 98 76 71 60 58 58 43 40 36 20 37 32 27 27 28 34 21 15 15 14 13 12 11 15 10 7 8 6 8 3 3 6 5 4 6 2 6 2 1 5 2 1 1 4 2 2 1 2 3 3 0 1 1 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 36 count: 20013 average: 24.6151 | standard deviation: 1.14519 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14654 147 4602 55 197 210 122 9 4 7 2 3 1 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 14 count: 20013 average: 1.75611 | standard deviation: 1.57695 | 4592 5185 5189 3122 599 522 649 37 57 27 22 9 1 1 1 ]
+imcomplete_wCC_Times: 36
+miss_latency_dir_issue_to_initial_request: [binsize: 128 max: 17751 count: 594143 average: 3281.6 | standard deviation: 2948.63 | 70459 23636 22470 26815 21073 17834 15569 15256 11489 8692 8858 8535 6953 6461 6209 6394 5831 5705 5951 5300 5371 5506 5686 5410 4771 5356 5585 5329 5323 5170 5762 5501 5637 6026 5516 5826 6170 6573 6296 5868 6645 6887 6688 6652 6642 7117 6992 6896 7344 6456 6743 6766 6983 6503 5557 6088 6033 5549 5152 4707 4962 4414 4059 4047 3285 3235 2984 2762 2505 2115 2147 1973 1607 1490 1369 1271 1134 976 879 727 688 601 569 497 395 377 340 255 258 192 194 157 159 120 94 91 79 69 63 47 50 48 37 30 23 24 21 21 19 18 15 12 10 8 8 10 8 2 1 3 2 2 3 0 2 1 0 2 2 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_dir_initial_forward_request: [binsize: 32 max: 3413 count: 594143 average: 11.5407 | standard deviation: 54.8335 | 590975 126 129 122 130 112 152 110 106 86 80 96 57 71 55 74 120 108 112 87 106 121 81 59 55 45 41 49 33 43 36 46 35 44 44 34 51 26 15 21 11 18 15 2 17 9 14 12 14 7 7 14 11 10 7 6 8 7 5 2 3 4 2 3 3 2 5 5 4 1 1 2 1 1 1 2 1 0 1 3 1 0 0 1 1 0 1 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 39 count: 594143 average: 24.8323 | standard deviation: 1.2805 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 381121 5028 183309 1629 7600 8210 5800 607 392 287 60 63 33 3 0 1 ]
+miss_latency_dir_first_response_to_completion: [binsize: 32 max: 4786 count: 594143 average: 685.013 | standard deviation: 462.654 | 0 0 0 14569 19552 16984 18956 21831 25498 21270 20601 20164 22271 24246 19384 17880 16629 16644 17418 13914 13519 13446 14462 15723 13379 13279 13011 13909 14567 10666 9436 8186 7949 7755 5930 5689 5412 5522 5680 4515 4518 4289 4761 4798 3591 3222 2904 2669 2658 2080 1990 1847 1910 1906 1483 1470 1347 1505 1527 1157 1030 856 893 875 669 615 565 586 613 480 455 402 445 430 335 328 258 251 242 186 180 182 159 182 128 110 102 127 92 92 76 67 59 62 43 54 39 42 44 40 33 22 27 23 26 18 18 11 7 7 9 10 6 6 7 3 1 4 8 2 3 3 5 2 0 0 1 2 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 imcomplete_dir_Times: 0
-miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 98 average:     2 | standard deviation: 0 | 0 0 98 ]
-miss_latency_LD_L2Cache: [binsize: 32 max: 4732 count: 372 average: 557.742 | standard deviation: 655.44 | 86 14 9 10 9 6 7 8 5 12 4 11 5 7 11 10 17 6 8 7 11 7 6 5 3 2 5 6 3 5 2 6 3 3 1 1 4 3 4 1 3 1 1 2 1 0 2 1 1 1 2 0 1 1 1 0 1 2 1 0 1 2 1 0 0 0 1 0 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD_Directory: [binsize: 128 max: 18350 count: 385675 average: 4002.51 | standard deviation: 2987.6 | 0 4035 7726 10215 9706 12023 13244 14012 12102 10793 11397 10910 9258 8226 7473 7137 6159 5719 5649 4636 4425 4457 4364 4018 3557 3867 3951 3580 3493 3291 3552 3517 3488 3587 3309 3503 3691 3814 3629 3491 3854 4068 3973 4042 4070 4314 4251 4431 4575 4182 4413 4495 4691 4414 3942 4439 4528 4167 4116 3884 4021 3752 3589 3476 3116 3091 2979 2906 2642 2157 2311 2254 1873 1739 1561 1573 1277 1257 1153 943 871 803 814 659 518 502 488 428 373 326 313 246 235 177 166 152 159 137 109 84 87 77 65 51 41 44 26 26 24 18 15 20 13 7 12 9 8 9 5 8 1 7 3 2 2 4 1 2 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 14183 count: 12979 average: 3439.08 | standard deviation: 2951.32 | 1023 468 437 506 525 426 328 374 321 249 247 234 183 171 178 151 145 164 148 130 134 142 114 128 100 120 113 101 108 117 118 105 125 119 119 115 131 142 147 129 139 154 147 137 174 161 147 130 168 156 152 136 165 128 128 109 163 139 110 118 116 105 74 86 95 73 67 64 58 58 44 52 31 46 37 32 26 19 25 10 22 19 17 7 11 9 8 5 6 15 2 10 9 3 1 2 3 2 4 1 0 2 1 3 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 47 average:     2 | standard deviation: 0 | 0 0 47 ]
-miss_latency_ST_L2Cache: [binsize: 16 max: 2772 count: 183 average: 473.65 | standard deviation: 504.689 | 36 0 4 7 2 4 3 3 2 2 2 1 5 3 2 4 2 0 3 0 6 2 2 4 2 3 0 4 4 1 1 3 3 1 1 3 2 2 0 1 2 2 4 1 0 1 1 1 1 1 0 0 1 2 0 3 1 0 2 1 3 1 1 2 0 2 0 1 0 1 2 0 2 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_Directory: [binsize: 128 max: 18350 count: 207934 average: 4004.97 | standard deviation: 2989.48 | 0 2202 4179 5513 5196 6415 7155 7618 6604 5877 6225 5788 4924 4505 3883 3858 3317 3048 2963 2500 2406 2393 2398 2099 1909 2107 2034 1986 1916 1849 1847 1877 1857 1968 1805 1860 1953 2198 2023 1850 2059 2190 2114 2243 2200 2277 2310 2330 2481 2146 2280 2514 2581 2355 2196 2349 2435 2186 2193 2082 2258 1992 1948 2015 1648 1647 1645 1627 1373 1186 1209 1126 1034 974 830 825 705 654 701 508 459 444 423 353 277 285 241 261 213 192 173 155 140 106 94 73 64 69 48 42 40 37 32 26 21 16 10 10 13 8 15 9 7 6 4 6 2 3 4 1 3 3 2 1 2 2 1 2 0 1 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 15385 count: 7154 average: 3501.97 | standard deviation: 2984.9 | 561 263 272 256 264 235 208 199 166 144 121 121 91 90 83 79 84 66 74 65 72 66 60 56 63 69 67 66 71 68 69 82 56 70 72 86 87 72 65 80 77 68 80 89 72 68 69 102 94 90 64 77 89 81 74 89 73 74 59 71 68 63 62 50 49 36 39 36 28 32 30 25 29 21 18 23 20 12 13 9 13 8 6 7 7 6 6 4 8 3 5 0 2 1 3 1 3 1 0 0 0 1 0 1 0 2 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 97 average:     2 | standard deviation: 0 | 0 0 97 ]
+miss_latency_LD_L2Cache: [binsize: 32 max: 3932 count: 386 average: 537.611 | standard deviation: 654.97 | 100 16 5 9 6 7 9 10 8 8 7 14 11 9 8 11 11 8 10 6 6 9 6 4 2 3 2 5 3 3 5 2 2 1 5 4 2 4 3 1 3 3 0 1 2 3 2 1 0 0 2 1 0 0 1 0 1 0 1 1 1 1 1 0 0 1 0 0 2 1 1 0 0 0 1 0 0 0 0 2 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_Directory: [binsize: 128 max: 18900 count: 385845 average: 4005.31 | standard deviation: 2984.21 | 0 4148 7498 10241 9525 11737 13456 13972 12273 10628 11381 11011 9118 8333 7448 7123 6040 5760 5611 4696 4619 4353 4368 3962 3550 3855 3912 3575 3574 3519 3588 3453 3595 3704 3359 3663 3696 3813 3727 3478 3965 4069 3984 4058 3982 4336 4217 4188 4535 4090 4370 4427 4662 4421 3918 4414 4607 4255 4078 3839 4176 3728 3651 3612 3183 3090 2996 2869 2536 2282 2341 2093 1885 1787 1528 1464 1349 1233 1185 952 866 804 818 694 529 570 470 429 337 335 309 244 221 208 153 144 138 100 104 68 74 63 66 44 44 36 27 30 28 21 19 24 19 9 8 8 14 9 3 8 2 5 5 5 3 2 0 2 0 1 0 1 1 1 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 15203 count: 13090 average: 3473.87 | standard deviation: 2975.32 | 1086 423 430 528 471 427 370 393 323 273 250 231 203 167 159 151 146 118 128 129 128 134 121 108 113 112 104 130 99 106 122 125 119 115 113 126 129 137 118 145 150 143 127 149 152 154 171 155 185 151 153 146 150 151 154 139 136 131 130 129 101 102 87 94 99 83 65 58 72 47 72 45 38 30 40 29 36 27 23 22 19 20 14 8 13 10 5 6 10 9 6 1 3 2 5 4 3 1 1 2 0 2 0 3 0 1 2 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 49 average:     2 | standard deviation: 0 | 0 0 49 ]
+miss_latency_ST_L2Cache: [binsize: 32 max: 4896 count: 191 average: 480.319 | standard deviation: 622.956 | 50 6 6 5 4 8 4 4 2 5 3 3 6 4 7 6 5 2 3 4 7 2 6 1 3 3 4 0 1 0 1 5 0 1 1 1 3 1 1 0 0 1 1 0 0 0 0 3 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_Directory: [binsize: 128 max: 17580 count: 208298 average: 3998.67 | standard deviation: 2984.61 | 0 2119 4216 5420 5347 6377 7216 7430 6595 5910 6229 5895 4867 4653 4041 3741 3278 3123 3027 2477 2433 2360 2374 2138 1987 2136 2021 1970 1951 1874 1911 1934 1955 1984 1831 1882 1965 2082 1967 1941 2069 2140 2160 2196 2123 2415 2306 2287 2491 2189 2412 2539 2480 2456 2164 2304 2361 2194 2206 2072 2170 1989 1964 1972 1682 1585 1633 1525 1360 1242 1210 1172 1051 975 875 836 716 621 633 536 466 441 382 354 270 285 254 221 217 189 162 120 118 94 72 79 62 69 73 45 45 40 33 25 35 14 14 17 10 13 13 10 14 12 7 6 5 11 5 4 4 4 0 2 1 2 1 2 2 0 3 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 14806 count: 6959 average: 3454.58 | standard deviation: 2948.43 | 562 251 210 272 265 230 198 186 152 156 121 136 98 91 94 81 80 62 71 78 82 64 72 67 62 59 76 61 67 60 69 64 56 59 71 67 68 67 92 77 75 74 70 85 85 68 85 67 76 76 70 86 68 63 85 75 86 57 67 72 57 59 68 54 36 37 48 42 36 20 20 18 23 20 19 23 21 14 20 14 8 9 6 4 5 5 3 7 5 1 1 1 1 2 2 2 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -124,242 +124,242 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
 Resource Usage
 --------------
 page_size: 4096
-user_time: 160
+user_time: 129
 system_time: 0
-page_reclaims: 12321
+page_reclaims: 15794
 page_faults: 0
 swaps: 0
-block_inputs: 184
-block_outputs: 0
+block_inputs: 16
+block_outputs: 256
 
 Network Stats
 -------------
 
-total_msg_count_Request_Control: 1841400 14731200
-total_msg_count_Response_Data: 1841217 132567624
-total_msg_count_Response_Control: 12827847 102622776
-total_msg_count_Writeback_Data: 637776 45919872
-total_msg_count_Writeback_Control: 4570782 36566256
-total_msg_count_Broadcast_Control: 9205802 73646416
-total_msg_count_Unblock_Control: 1841253 14730024
-total_msgs: 32766077 total_bytes: 420784168
+total_msg_count_Request_Control: 1842744 14741952
+total_msg_count_Response_Data: 1842572 132665184
+total_msg_count_Response_Control: 12837681 102701448
+total_msg_count_Writeback_Data: 638442 45967824
+total_msg_count_Writeback_Control: 4571118 36568944
+total_msg_count_Broadcast_Control: 9212655 73701240
+total_msg_count_Unblock_Control: 1842609 14740872
+total_msgs: 32787821 total_bytes: 421087464
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 3.80091
-  links_utilized_percent_switch_0_link_0: 4.80628 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 2.79553 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_0_link_0_Request_Control: 6 48 [ 0 0 0 6 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Response_Data: 76925 5538600 [ 0 0 0 0 76925 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Response_Control: 535897 4287176 [ 0 0 0 0 535897 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Control: 72514 580112 [ 0 0 0 72514 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Broadcast_Control: 536803 4294424 [ 0 0 0 536803 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Request_Control: 76926 615408 [ 0 0 76926 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Data: 2460 177120 [ 0 0 0 0 2460 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Control: 534349 4274792 [ 0 0 0 0 534349 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Data: 26678 1920816 [ 0 0 0 0 0 26678 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Control: 118349 946792 [ 0 0 72514 0 0 45835 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Unblock_Control: 76926 615408 [ 0 0 0 0 0 76926 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_0: 3.80272
+  links_utilized_percent_switch_0_link_0: 4.8098 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 2.79565 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_0_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 77060 5548320 [ 0 0 0 0 77060 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Control: 536853 4294824 [ 0 0 0 0 536853 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 72638 581104 [ 0 0 0 72638 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Broadcast_Control: 537121 4296968 [ 0 0 0 537121 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Request_Control: 77062 616496 [ 0 0 77062 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 2513 180936 [ 0 0 0 0 2513 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Control: 534611 4276888 [ 0 0 0 0 534611 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Data: 26618 1916496 [ 0 0 0 0 0 26618 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Control: 118656 949248 [ 0 0 72638 0 0 46018 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Unblock_Control: 77061 616488 [ 0 0 0 0 0 77061 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 3.79679
-  links_utilized_percent_switch_1_link_0: 4.80165 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 2.79193 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_1_link_0_Request_Control: 9 72 [ 0 0 0 9 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Response_Data: 76815 5530680 [ 0 0 0 0 76815 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Response_Control: 535127 4281016 [ 0 0 0 0 535127 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Writeback_Control: 72393 579144 [ 0 0 0 72393 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Broadcast_Control: 536912 4295296 [ 0 0 0 536912 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Request_Control: 76818 614544 [ 0 0 76818 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 2496 179712 [ 0 0 0 0 2496 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Control: 534425 4275400 [ 0 0 0 0 534425 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Data: 26513 1908936 [ 0 0 0 0 0 26513 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 118272 946176 [ 0 0 72395 0 0 45877 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Unblock_Control: 76818 614544 [ 0 0 0 0 0 76818 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_1: 3.7784
+  links_utilized_percent_switch_1_link_0: 4.77704 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 2.77977 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_1_link_0_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Data: 76262 5490864 [ 0 0 0 0 76262 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Control: 531458 4251664 [ 0 0 0 0 531458 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Writeback_Control: 71882 575056 [ 0 0 0 71882 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Broadcast_Control: 537917 4303336 [ 0 0 0 537917 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Request_Control: 76266 610128 [ 0 0 76266 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 2510 180720 [ 0 0 0 0 2510 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Control: 535411 4283288 [ 0 0 0 0 535411 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Data: 26150 1882800 [ 0 0 0 0 0 26150 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 117611 940888 [ 0 0 71882 0 0 45729 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Unblock_Control: 76266 610128 [ 0 0 0 0 0 76266 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 3.79246
-  links_utilized_percent_switch_2_link_0: 4.79461 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 2.79032 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_2_link_0_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Response_Data: 76635 5517720 [ 0 0 0 0 76635 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Response_Control: 533994 4271952 [ 0 0 0 0 533994 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 72284 578272 [ 0 0 0 72284 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Broadcast_Control: 537084 4296672 [ 0 0 0 537084 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Request_Control: 76637 613096 [ 0 0 76637 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Data: 2531 182232 [ 0 0 0 0 2531 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Control: 534557 4276456 [ 0 0 0 0 534557 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Writeback_Data: 26453 1904616 [ 0 0 0 0 0 26453 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Writeback_Control: 118113 944904 [ 0 0 72284 0 0 45829 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Unblock_Control: 76637 613096 [ 0 0 0 0 0 76637 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_2: 3.7996
+  links_utilized_percent_switch_2_link_0: 4.8032 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 2.796 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_2_link_0_Request_Control: 5 40 [ 0 0 0 5 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 76897 5536584 [ 0 0 0 0 76897 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Control: 535696 4285568 [ 0 0 0 0 535696 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 72576 580608 [ 0 0 0 72576 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Broadcast_Control: 537278 4298224 [ 0 0 0 537278 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Request_Control: 76901 615208 [ 0 0 76901 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Data: 2501 180072 [ 0 0 0 0 2501 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Control: 534782 4278256 [ 0 0 0 0 534782 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Data: 26683 1921176 [ 0 0 0 0 0 26683 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Control: 118468 947744 [ 0 0 72576 0 0 45892 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Unblock_Control: 76898 615184 [ 0 0 0 0 0 76898 0 0 0 0 ] base_latency: 1
 
 switch_3_inlinks: 2
 switch_3_outlinks: 2
-links_utilized_percent_switch_3: 3.78928
-  links_utilized_percent_switch_3_link_0: 4.78637 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_3_link_1: 2.79219 bw: 16000 base_latency: 1
+links_utilized_percent_switch_3: 3.80001
+  links_utilized_percent_switch_3_link_0: 4.80241 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 2.7976 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_3_link_0_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Response_Data: 76439 5503608 [ 0 0 0 0 76439 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Response_Control: 532555 4260440 [ 0 0 0 0 532555 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Writeback_Control: 72144 577152 [ 0 0 0 72144 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Broadcast_Control: 537280 4298240 [ 0 0 0 537280 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Request_Control: 76442 611536 [ 0 0 76442 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Response_Data: 2483 178776 [ 0 0 0 0 2483 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Response_Control: 534799 4278392 [ 0 0 0 0 534799 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Writeback_Data: 26650 1918800 [ 0 0 0 0 0 26650 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Writeback_Control: 117637 941096 [ 0 0 72144 0 0 45493 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Unblock_Control: 76440 611520 [ 0 0 0 0 0 76440 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Data: 76881 5535432 [ 0 0 0 0 76881 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Control: 535602 4284816 [ 0 0 0 0 535602 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Writeback_Control: 72495 579960 [ 0 0 0 72495 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Broadcast_Control: 537298 4298384 [ 0 0 0 537298 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Request_Control: 76883 615064 [ 0 0 76883 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Data: 2442 175824 [ 0 0 0 0 2442 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Control: 534858 4278864 [ 0 0 0 0 534858 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Writeback_Data: 26841 1932552 [ 0 0 0 0 0 26841 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Writeback_Control: 118149 945192 [ 0 0 72495 0 0 45654 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Unblock_Control: 76881 615048 [ 0 0 0 0 0 76881 0 0 0 0 ] base_latency: 1
 
 switch_4_inlinks: 2
 switch_4_outlinks: 2
-links_utilized_percent_switch_4: 3.78981
-  links_utilized_percent_switch_4_link_0: 4.78749 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_4_link_1: 2.79214 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_4_link_0_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Response_Data: 76472 5505984 [ 0 0 0 0 76472 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Response_Control: 532781 4262248 [ 0 0 0 0 532781 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Writeback_Control: 72081 576648 [ 0 0 0 72081 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Broadcast_Control: 537248 4297984 [ 0 0 0 537248 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Request_Control: 76475 611800 [ 0 0 76475 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Response_Data: 2594 186768 [ 0 0 0 0 2594 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Response_Control: 534656 4277248 [ 0 0 0 0 534656 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Writeback_Data: 26548 1911456 [ 0 0 0 0 0 26548 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Writeback_Control: 117613 940904 [ 0 0 72081 0 0 45532 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Unblock_Control: 76473 611784 [ 0 0 0 0 0 76473 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_4: 3.79333
+  links_utilized_percent_switch_4_link_0: 4.7963 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_4_link_1: 2.79036 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_4_link_0_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Data: 76730 5524560 [ 0 0 0 0 76730 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Control: 534710 4277680 [ 0 0 0 0 534710 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Writeback_Control: 72256 578048 [ 0 0 0 72256 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Broadcast_Control: 537447 4299576 [ 0 0 0 537447 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Request_Control: 76733 613864 [ 0 0 76733 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Data: 2540 182880 [ 0 0 0 0 2540 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Control: 534911 4279288 [ 0 0 0 0 534911 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Writeback_Data: 26475 1906200 [ 0 0 0 0 0 26475 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Writeback_Control: 118034 944272 [ 0 0 72256 0 0 45778 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Unblock_Control: 76733 613864 [ 0 0 0 0 0 76733 0 0 0 0 ] base_latency: 1
 
 switch_5_inlinks: 2
 switch_5_outlinks: 2
-links_utilized_percent_switch_5: 3.797
-  links_utilized_percent_switch_5_link_0: 4.8 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_5_link_1: 2.79399 bw: 16000 base_latency: 1
+links_utilized_percent_switch_5: 3.79978
+  links_utilized_percent_switch_5_link_0: 4.80536 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_1: 2.79419 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_5_link_0_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Response_Data: 76761 5526792 [ 0 0 0 0 76761 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Response_Control: 534872 4278976 [ 0 0 0 0 534872 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Writeback_Control: 72462 579696 [ 0 0 0 72462 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Broadcast_Control: 536957 4295656 [ 0 0 0 536957 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Request_Control: 76765 614120 [ 0 0 76765 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Response_Data: 2522 181584 [ 0 0 0 0 2522 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Response_Control: 534439 4275512 [ 0 0 0 0 534439 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Writeback_Data: 26577 1913544 [ 0 0 0 0 0 26577 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Writeback_Control: 118345 946760 [ 0 0 72462 0 0 45883 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Unblock_Control: 76764 614112 [ 0 0 0 0 0 76764 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Data: 76949 5540328 [ 0 0 0 0 76949 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Control: 536186 4289488 [ 0 0 0 0 536186 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Writeback_Control: 72495 579960 [ 0 0 0 72495 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Broadcast_Control: 537229 4297832 [ 0 0 0 537229 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Request_Control: 76952 615616 [ 0 0 76952 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Data: 2529 182088 [ 0 0 0 0 2529 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Control: 534704 4277632 [ 0 0 0 0 534704 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Writeback_Data: 26582 1913904 [ 0 0 0 0 0 26582 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Writeback_Control: 118406 947248 [ 0 0 72495 0 0 45911 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Unblock_Control: 76951 615608 [ 0 0 0 0 0 76951 0 0 0 0 ] base_latency: 1
 
 switch_6_inlinks: 2
 switch_6_outlinks: 2
-links_utilized_percent_switch_6: 3.80454
-  links_utilized_percent_switch_6_link_0: 4.81281 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_6_link_1: 2.79627 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_6_link_0_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Response_Data: 77086 5550192 [ 0 0 0 0 77086 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Response_Control: 536995 4295960 [ 0 0 0 0 536995 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Writeback_Control: 72631 581048 [ 0 0 0 72631 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Broadcast_Control: 536640 4293120 [ 0 0 0 536640 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Request_Control: 77089 616712 [ 0 0 77089 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Response_Data: 2494 179568 [ 0 0 0 0 2494 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Response_Control: 534150 4273200 [ 0 0 0 0 534150 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Writeback_Data: 26630 1917360 [ 0 0 0 0 0 26630 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Writeback_Control: 118632 949056 [ 0 0 72631 0 0 46001 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Unblock_Control: 77086 616688 [ 0 0 0 0 0 77086 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_6: 3.80784
+  links_utilized_percent_switch_6_link_0: 4.81587 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_6_link_1: 2.79982 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_6_link_0_Request_Control: 6 48 [ 0 0 0 6 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Data: 77215 5559480 [ 0 0 0 0 77215 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Control: 537866 4302928 [ 0 0 0 0 537866 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Writeback_Control: 72700 581600 [ 0 0 0 72700 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Broadcast_Control: 536967 4295736 [ 0 0 0 536967 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Request_Control: 77217 617736 [ 0 0 77217 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Data: 2515 181080 [ 0 0 0 0 2515 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Control: 534458 4275664 [ 0 0 0 0 534458 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Writeback_Data: 26780 1928160 [ 0 0 0 0 0 26780 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Writeback_Control: 118620 948960 [ 0 0 72700 0 0 45920 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Unblock_Control: 77215 617720 [ 0 0 0 0 0 77215 0 0 0 0 ] base_latency: 1
 
 switch_7_inlinks: 2
 switch_7_outlinks: 2
-links_utilized_percent_switch_7: 3.79269
-  links_utilized_percent_switch_7_link_0: 4.79316 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_7_link_1: 2.79223 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_7_link_0_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Response_Data: 76606 5515632 [ 0 0 0 0 76606 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Response_Control: 533728 4269824 [ 0 0 0 0 533728 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Writeback_Control: 72222 577776 [ 0 0 0 72222 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Broadcast_Control: 537116 4296928 [ 0 0 0 537116 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Request_Control: 76609 612872 [ 0 0 76609 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Response_Data: 2550 183600 [ 0 0 0 0 2550 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Response_Control: 534574 4276592 [ 0 0 0 0 534574 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Writeback_Data: 26543 1911096 [ 0 0 0 0 0 26543 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Writeback_Control: 117901 943208 [ 0 0 72222 0 0 45679 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Unblock_Control: 76607 612856 [ 0 0 0 0 0 76607 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_7: 3.782
+  links_utilized_percent_switch_7_link_0: 4.77391 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_7_link_1: 2.79009 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_7_link_0_Request_Control: 7 56 [ 0 0 0 7 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Data: 76197 5486184 [ 0 0 0 0 76197 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Control: 530856 4246848 [ 0 0 0 0 530856 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Writeback_Control: 71802 574416 [ 0 0 0 71802 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Broadcast_Control: 537982 4303856 [ 0 0 0 537982 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Request_Control: 76199 609592 [ 0 0 76199 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Data: 2497 179784 [ 0 0 0 0 2497 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Control: 535492 4283936 [ 0 0 0 0 535492 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Writeback_Data: 26685 1921320 [ 0 0 0 0 0 26685 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Writeback_Control: 116918 935344 [ 0 0 71802 0 0 45116 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Unblock_Control: 76198 609584 [ 0 0 0 0 0 76198 0 0 0 0 ] base_latency: 1
 
 switch_8_inlinks: 2
 switch_8_outlinks: 2
-links_utilized_percent_switch_8: 13.8897
-  links_utilized_percent_switch_8_link_0: 10.6866 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_8_link_1: 17.0929 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_8_link_0_Request_Control: 613761 4910088 [ 0 0 613761 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Writeback_Data: 212592 15306624 [ 0 0 0 0 0 212592 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Writeback_Control: 944862 7558896 [ 0 0 578733 0 0 366129 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Unblock_Control: 613751 4910008 [ 0 0 0 0 0 613751 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Request_Control: 39 312 [ 0 0 0 39 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Response_Data: 593609 42739848 [ 0 0 0 0 593609 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Writeback_Control: 578733 4629864 [ 0 0 0 578733 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Broadcast_Control: 613722 4909776 [ 0 0 0 613722 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_8: 13.891
+  links_utilized_percent_switch_8_link_0: 10.6868 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_8_link_1: 17.0952 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_8_link_0_Request_Control: 614213 4913704 [ 0 0 614213 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Writeback_Data: 212814 15322608 [ 0 0 0 0 0 212814 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Writeback_Control: 944862 7558896 [ 0 0 578844 0 0 366018 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Unblock_Control: 614203 4913624 [ 0 0 0 0 0 614203 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Request_Control: 35 280 [ 0 0 0 35 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Response_Data: 594143 42778296 [ 0 0 0 0 594143 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Writeback_Control: 578844 4630752 [ 0 0 0 578844 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Broadcast_Control: 614177 4913416 [ 0 0 0 614177 0 0 0 0 0 0 ] base_latency: 1
 
 switch_9_inlinks: 9
 switch_9_outlinks: 9
-links_utilized_percent_switch_9: 5.4521
-  links_utilized_percent_switch_9_link_0: 4.80628 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_1: 4.80166 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_2: 4.79461 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_3: 4.78637 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_4: 4.78749 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_5: 4.8 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_6: 4.81282 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_7: 4.79316 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_8: 10.6866 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_9_link_0_Request_Control: 6 48 [ 0 0 0 6 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Response_Data: 76925 5538600 [ 0 0 0 0 76925 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Response_Control: 535897 4287176 [ 0 0 0 0 535897 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Writeback_Control: 72514 580112 [ 0 0 0 72514 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Broadcast_Control: 536803 4294424 [ 0 0 0 536803 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Request_Control: 9 72 [ 0 0 0 9 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Response_Data: 76815 5530680 [ 0 0 0 0 76815 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Response_Control: 535127 4281016 [ 0 0 0 0 535127 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Writeback_Control: 72394 579152 [ 0 0 0 72394 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Broadcast_Control: 536912 4295296 [ 0 0 0 536912 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Response_Data: 76635 5517720 [ 0 0 0 0 76635 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Response_Control: 533994 4271952 [ 0 0 0 0 533994 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Writeback_Control: 72284 578272 [ 0 0 0 72284 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Broadcast_Control: 537084 4296672 [ 0 0 0 537084 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_9: 5.4523
+  links_utilized_percent_switch_9_link_0: 4.80981 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_1: 4.77704 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_2: 4.8032 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_3: 4.80241 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_4: 4.7963 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_5: 4.80536 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_6: 4.81587 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_7: 4.77391 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_8: 10.6868 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_9_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Response_Data: 77060 5548320 [ 0 0 0 0 77060 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Response_Control: 536853 4294824 [ 0 0 0 0 536853 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Writeback_Control: 72638 581104 [ 0 0 0 72638 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Broadcast_Control: 537121 4296968 [ 0 0 0 537121 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Data: 76262 5490864 [ 0 0 0 0 76262 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Control: 531458 4251664 [ 0 0 0 0 531458 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Writeback_Control: 71882 575056 [ 0 0 0 71882 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Broadcast_Control: 537917 4303336 [ 0 0 0 537917 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Request_Control: 5 40 [ 0 0 0 5 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Response_Data: 76897 5536584 [ 0 0 0 0 76897 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Response_Control: 535696 4285568 [ 0 0 0 0 535696 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Writeback_Control: 72576 580608 [ 0 0 0 72576 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Broadcast_Control: 537278 4298224 [ 0 0 0 537278 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_9_link_3_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Response_Data: 76439 5503608 [ 0 0 0 0 76439 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Response_Control: 532555 4260440 [ 0 0 0 0 532555 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Writeback_Control: 72144 577152 [ 0 0 0 72144 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Broadcast_Control: 537280 4298240 [ 0 0 0 537280 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Response_Data: 76472 5505984 [ 0 0 0 0 76472 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Response_Control: 532781 4262248 [ 0 0 0 0 532781 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Writeback_Control: 72081 576648 [ 0 0 0 72081 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Broadcast_Control: 537248 4297984 [ 0 0 0 537248 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Response_Data: 76881 5535432 [ 0 0 0 0 76881 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Response_Control: 535602 4284816 [ 0 0 0 0 535602 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Writeback_Control: 72495 579960 [ 0 0 0 72495 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Broadcast_Control: 537298 4298384 [ 0 0 0 537298 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Response_Data: 76730 5524560 [ 0 0 0 0 76730 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Response_Control: 534710 4277680 [ 0 0 0 0 534710 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Writeback_Control: 72256 578048 [ 0 0 0 72256 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Broadcast_Control: 537447 4299576 [ 0 0 0 537447 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_9_link_5_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Response_Data: 76761 5526792 [ 0 0 0 0 76761 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Response_Control: 534872 4278976 [ 0 0 0 0 534872 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Writeback_Control: 72462 579696 [ 0 0 0 72462 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Broadcast_Control: 536957 4295656 [ 0 0 0 536957 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Response_Data: 77086 5550192 [ 0 0 0 0 77086 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Response_Control: 536995 4295960 [ 0 0 0 0 536995 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Writeback_Control: 72631 581048 [ 0 0 0 72631 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Broadcast_Control: 536640 4293120 [ 0 0 0 536640 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Response_Data: 76606 5515632 [ 0 0 0 0 76606 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Response_Control: 533728 4269824 [ 0 0 0 0 533728 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Writeback_Control: 72222 577776 [ 0 0 0 72222 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Broadcast_Control: 537116 4296928 [ 0 0 0 537116 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_8_Request_Control: 613761 4910088 [ 0 0 613761 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_8_Writeback_Data: 212592 15306624 [ 0 0 0 0 0 212592 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_8_Writeback_Control: 944862 7558896 [ 0 0 578733 0 0 366129 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_8_Unblock_Control: 613751 4910008 [ 0 0 0 0 0 613751 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Response_Data: 76949 5540328 [ 0 0 0 0 76949 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Response_Control: 536186 4289488 [ 0 0 0 0 536186 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Writeback_Control: 72495 579960 [ 0 0 0 72495 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Broadcast_Control: 537229 4297832 [ 0 0 0 537229 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Request_Control: 6 48 [ 0 0 0 6 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Response_Data: 77215 5559480 [ 0 0 0 0 77215 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Response_Control: 537866 4302928 [ 0 0 0 0 537866 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Writeback_Control: 72700 581600 [ 0 0 0 72700 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Broadcast_Control: 536967 4295736 [ 0 0 0 536967 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Request_Control: 7 56 [ 0 0 0 7 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Response_Data: 76197 5486184 [ 0 0 0 0 76197 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Response_Control: 530856 4246848 [ 0 0 0 0 530856 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Writeback_Control: 71802 574416 [ 0 0 0 71802 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Broadcast_Control: 537982 4303856 [ 0 0 0 537982 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Request_Control: 614213 4913704 [ 0 0 614213 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Writeback_Data: 212814 15322608 [ 0 0 0 0 0 212814 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Writeback_Control: 944862 7558896 [ 0 0 578844 0 0 366018 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Unblock_Control: 614203 4913624 [ 0 0 0 0 0 614203 0 0 0 0 ] base_latency: 1
 
 Cache Stats: system.l1_cntrl0.L1IcacheMemory
   system.l1_cntrl0.L1IcacheMemory_total_misses: 0
@@ -370,81 +370,81 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 76996
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 76996
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 77130
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 77130
   system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   64.9332%
-  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   35.0668%
+  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   65.0538%
+  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   34.9462%
 
-  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   76996    100%
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   77130    100%
 
 Cache Stats: system.l1_cntrl0.L2cacheMemory
-  system.l1_cntrl0.L2cacheMemory_total_misses: 76996
-  system.l1_cntrl0.L2cacheMemory_total_demand_misses: 76996
+  system.l1_cntrl0.L2cacheMemory_total_misses: 77130
+  system.l1_cntrl0.L2cacheMemory_total_demand_misses: 77130
   system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L2cacheMemory_request_type_LD:   64.9332%
-  system.l1_cntrl0.L2cacheMemory_request_type_ST:   35.0668%
+  system.l1_cntrl0.L2cacheMemory_request_type_LD:   65.0538%
+  system.l1_cntrl0.L2cacheMemory_request_type_ST:   34.9462%
 
-  system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   76996    100%
+  system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   77130    100%
 
  --- L1Cache ---
  - Event Counts -
-Load [49688 49974 50197 49871 50032 50118 49889 49611 ] 399380
+Load [49960 50097 50251 49306 50224 49889 50058 49872 ] 399657
 Ifetch [0 0 0 0 0 0 0 0 ] 0
-Store [26926 26927 27030 26872 27014 26861 26863 26957 ] 215450
-L2_Replacement [76463 76752 77078 76593 76911 76806 76626 76428 ] 613657
-L1_to_L2 [836160 839124 842521 838664 840655 840442 836366 836722 ] 6710654
-Trigger_L2_to_L1D [73 61 74 84 70 82 57 76 ] 577
+Store [26893 26978 27110 27052 26969 26517 26946 27164 ] 215629
+L2_Replacement [76719 76942 77202 76188 77047 76251 76888 76870 ] 614107
+L1_to_L2 [836726 839447 842010 836009 838835 834429 841329 840056 ] 6708841
+Trigger_L2_to_L1D [63 67 79 89 68 80 62 90 ] 598
 Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-Complete_L2_to_L1 [73 61 74 84 70 82 57 76 ] 577
-Other_GETX [188217 188208 188109 188265 188117 188284 188272 188179 ] 1505651
-Other_GETS [349031 348749 348531 348851 348686 348628 348812 349101 ] 2790389
-Merged_GETS [2 4 4 8 6 9 4 2 ] 39
+Complete_L2_to_L1 [63 67 79 89 68 80 62 90 ] 598
+Other_GETX [188409 188326 188206 188273 188332 188797 188348 188164 ] 1506855
+Other_GETS [349038 348903 348761 349709 348789 349120 348930 349134 ] 2792384
+Merged_GETS [4 4 6 7 3 4 5 2 ] 35
 Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 Invalidate [0 0 0 0 0 0 0 0 ] 0
-Ack [532715 534820 536935 533668 535835 535073 533934 532497 ] 4275477
-Shared_Ack [66 52 60 60 62 54 60 58 ] 472
-Data [2867 2770 2888 2837 2925 2969 2847 2862 ] 22965
-Shared_Data [1047 1013 1104 1046 1030 1019 1021 1023 ] 8303
-Exclusive_Data [72558 72978 73094 72723 72970 72827 72767 72554 ] 582471
-Writeback_Ack [72081 72462 72631 72222 72514 72393 72284 72144 ] 578731
+Ack [534644 536131 537807 530800 536790 531405 535642 535541 ] 4278760
+Shared_Ack [66 55 59 56 63 53 54 61 ] 467
+Data [2935 2984 2978 2948 2936 2963 2884 2931 ] 23559
+Shared_Data [1031 1085 1122 1041 1068 998 1047 1069 ] 8461
+Exclusive_Data [72764 72880 73115 72208 73056 72301 72966 72881 ] 582171
+Writeback_Ack [72256 72495 72700 71802 72638 71882 72576 72495 ] 578844
 Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
-All_acks [1108 1061 1151 1098 1087 1067 1066 1076 ] 8714
-All_acks_no_sharers [75364 75701 75936 75509 75838 75748 75569 75363 ] 605028
+All_acks [1093 1136 1173 1091 1122 1044 1097 1120 ] 8876
+All_acks_no_sharers [75637 75813 76042 75106 75938 75219 75800 75761 ] 605316
 Flush_line [0 0 0 0 0 0 0 0 ] 0
 Block_Ack [0 0 0 0 0 0 0 0 ] 0
 
  - Transitions -
-I  Load [49599 49880 50105 49777 49949 50008 49815 49526 ] 398659
+I  Load [49877 50013 50158 49207 50127 49797 49982 49781 ] 398942
 I  Ifetch [0 0 0 0 0 0 0 0 ] 0
-I  Store [26875 26882 26983 26827 26973 26808 26820 26911 ] 215079
-I  L2_Replacement [1543 1500 1505 1512 1513 1513 1528 1452 ] 12066
-I  L1_to_L2 [368 345 309 324 312 336 300 306 ] 2600
-I  Trigger_L2_to_L1D [0 0 1 4 2 1 2 3 ] 13
+I  Store [26853 26938 27055 26990 26931 26464 26916 27099 ] 215246
+I  L2_Replacement [1507 1492 1482 1481 1477 1477 1457 1439 ] 11812
+I  L1_to_L2 [349 350 324 338 297 333 341 292 ] 2624
+I  Trigger_L2_to_L1D [1 0 1 0 3 2 2 1 ] 10
 I  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-I  Other_GETX [187271 187305 187180 187321 187175 187369 187342 187248 ] 1498211
-I  Other_GETS [347280 347038 346871 347146 347053 346962 347125 347449 ] 2776924
+I  Other_GETX [187532 187410 187293 187372 187420 187856 187432 187303 ] 1499618
+I  Other_GETS [347295 347206 347055 348026 347085 347452 347243 347456 ] 2778818
 I  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 I  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 I  Invalidate [0 0 0 0 0 0 0 0 ] 0
 I  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
-S  Load [1 0 2 0 1 1 0 0 ] 5
+S  Load [1 2 1 0 3 0 0 0 ] 7
 S  Ifetch [0 0 0 0 0 0 0 0 ] 0
-S  Store [0 1 1 0 0 0 0 1 ] 3
-S  L2_Replacement [2839 2790 2940 2859 2884 2898 2814 2832 ] 22856
-S  L1_to_L2 [2859 2822 2968 2891 2911 2928 2836 2866 ] 23081
-S  Trigger_L2_to_L1D [2 2 1 2 5 7 0 3 ] 22
+S  Store [1 0 2 1 0 0 0 0 ] 4
+S  L2_Replacement [2956 2955 3020 2905 2932 2892 2855 2936 ] 23451
+S  L1_to_L2 [2978 2979 3046 2934 2956 2916 2881 2969 ] 23659
+S  Trigger_L2_to_L1D [4 2 3 2 3 2 1 5 ] 22
 S  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-S  Other_GETX [26 39 31 37 32 29 30 39 ] 263
-S  Other_GETS [73 50 55 60 75 52 54 53 ] 472
+S  Other_GETX [26 33 32 33 28 27 39 34 ] 252
+S  Other_GETS [53 51 65 57 65 63 61 52 ] 467
 S  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 S  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 S  Invalidate [0 0 0 0 0 0 0 0 ] 0
@@ -453,105 +453,105 @@ S  Flush_line [0 0 0 0 0 0 0 0 ] 0
 O  Load [0 0 0 0 0 0 0 0 ] 0
 O  Ifetch [0 0 0 0 0 0 0 0 ] 0
 O  Store [0 0 0 0 0 0 0 0 ] 0
-O  L2_Replacement [1050 1039 994 1041 948 983 1010 1045 ] 8110
-O  L1_to_L2 [232 213 223 242 216 223 218 247 ] 1814
-O  Trigger_L2_to_L1D [1 2 1 3 1 0 1 3 ] 12
+O  L2_Replacement [1023 1045 1039 1022 1042 1034 1063 1013 ] 8281
+O  L1_to_L2 [239 208 209 230 230 241 206 221 ] 1784
+O  Trigger_L2_to_L1D [1 1 2 2 1 2 0 0 ] 9
 O  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-O  Other_GETX [10 8 13 15 9 8 6 3 ] 72
-O  Other_GETS [13 6 8 10 12 10 11 16 ] 86
-O  Merged_GETS [0 1 3 0 2 4 2 1 ] 13
+O  Other_GETX [11 8 9 9 7 4 3 9 ] 60
+O  Other_GETS [14 13 11 10 5 13 9 10 ] 85
+O  Merged_GETS [2 0 3 2 2 2 2 1 ] 14
 O  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 O  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 O  Invalidate [0 0 0 0 0 0 0 0 ] 0
 O  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
-M  Load [5 11 9 6 7 14 4 8 ] 64
+M  Load [8 7 5 11 13 9 6 5 ] 64
 M  Ifetch [0 0 0 0 0 0 0 0 ] 0
-M  Store [2 3 4 3 1 6 5 5 ] 29
-M  L2_Replacement [45052 45437 45535 45236 45476 45508 45390 45035 ] 362669
-M  L1_to_L2 [46391 46737 46827 46553 46724 46764 46652 46319 ] 372967
-M  Trigger_L2_to_L1D [48 39 47 53 31 49 31 49 ] 347
+M  Store [5 3 6 2 4 5 3 4 ] 32
+M  L2_Replacement [45292 45401 45474 44677 45551 45247 45472 45230 ] 362344
+M  L1_to_L2 [46556 46716 46794 45948 46839 46538 46795 46516 ] 372702
+M  Trigger_L2_to_L1D [37 46 39 56 37 44 44 51 ] 354
 M  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-M  Other_GETX [591 546 567 567 584 554 542 543 ] 4494
-M  Other_GETS [1058 1045 1007 1049 953 986 1014 1048 ] 8160
-M  Merged_GETS [1 2 0 4 2 1 1 1 ] 12
+M  Other_GETX [546 544 560 530 548 567 532 530 ] 4357
+M  Other_GETS [1032 1049 1045 1028 1048 1037 1063 1021 ] 8323
+M  Merged_GETS [0 3 2 2 1 2 2 1 ] 13
 M  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 M  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 M  Invalidate [0 0 0 0 0 0 0 0 ] 0
 M  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
-MM  Load [4 6 1 2 3 6 5 2 ] 29
+MM  Load [4 4 2 0 8 4 1 3 ] 26
 MM  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MM  Store [5 3 1 1 3 1 2 2 ] 18
-MM  L2_Replacement [25979 25986 26104 25945 26090 25904 25884 26064 ] 207956
-MM  L1_to_L2 [26693 26702 26831 26673 26825 26643 26682 26771 ] 213820
-MM  Trigger_L2_to_L1D [22 18 24 22 31 25 23 18 ] 183
+MM  Store [1 0 5 4 1 1 4 1 ] 17
+MM  L2_Replacement [25941 26049 26187 26103 26045 25601 26041 26252 ] 208219
+MM  L1_to_L2 [26666 26761 26914 26832 26800 26309 26733 26968 ] 213983
+MM  Trigger_L2_to_L1D [20 18 34 29 24 30 15 33 ] 203
 MM  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-MM  Other_GETX [317 304 313 325 311 316 347 342 ] 2575
-MM  Other_GETS [599 603 582 573 579 607 605 528 ] 4676
-MM  Merged_GETS [1 1 1 4 2 4 1 0 ] 14
+MM  Other_GETX [291 327 310 327 322 332 338 282 ] 2529
+MM  Other_GETS [636 580 573 582 575 549 548 586 ] 4629
+MM  Merged_GETS [2 1 1 3 0 0 1 0 ] 8
 MM  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 MM  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 MM  Invalidate [0 0 0 0 0 0 0 0 ] 0
 MM  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
-IR  Load [0 0 1 4 1 0 1 2 ] 9
+IR  Load [0 0 0 0 2 1 2 1 ] 6
 IR  Ifetch [0 0 0 0 0 0 0 0 ] 0
-IR  Store [0 0 0 0 1 1 1 1 ] 4
-IR  L1_to_L2 [0 0 0 16 9 4 7 7 ] 43
+IR  Store [1 0 1 0 1 1 0 0 ] 4
+IR  L1_to_L2 [0 0 0 0 3 5 19 0 ] 27
 IR  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
-SR  Load [1 1 1 2 3 6 0 2 ] 16
+SR  Load [3 1 2 1 2 0 0 3 ] 12
 SR  Ifetch [0 0 0 0 0 0 0 0 ] 0
-SR  Store [1 1 0 0 2 1 0 1 ] 6
-SR  L1_to_L2 [7 0 0 10 13 6 0 7 ] 43
+SR  Store [1 1 1 1 1 2 1 2 ] 10
+SR  L1_to_L2 [13 0 21 13 0 11 0 0 ] 58
 SR  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
-OR  Load [1 1 0 2 1 0 1 3 ] 9
+OR  Load [1 1 2 2 1 1 0 0 ] 8
 OR  Ifetch [0 0 0 0 0 0 0 0 ] 0
-OR  Store [0 1 1 1 0 0 0 0 ] 3
-OR  L1_to_L2 [1 0 0 11 0 0 9 9 ] 30
+OR  Store [0 0 0 0 0 1 0 0 ] 1
+OR  L1_to_L2 [0 0 15 0 0 0 0 0 ] 15
 OR  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
-MR  Load [30 29 32 33 20 32 18 30 ] 224
+MR  Load [24 28 28 34 27 32 31 31 ] 235
 MR  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MR  Store [18 10 15 20 11 17 13 19 ] 123
-MR  L1_to_L2 [73 73 72 61 19 112 86 51 ] 547
+MR  Store [13 18 11 22 10 12 13 20 ] 119
+MR  L1_to_L2 [75 65 70 103 69 85 38 78 ] 583
 MR  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
-MMR  Load [17 8 18 13 21 15 17 14 ] 123
+MMR  Load [15 15 23 18 15 17 11 17 ] 131
 MMR  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MMR  Store [5 10 6 9 10 10 6 4 ] 60
-MMR  L1_to_L2 [30 31 37 45 39 44 29 32 ] 287
+MMR  Store [5 3 11 11 9 13 4 16 ] 72
+MMR  L1_to_L2 [7 33 106 71 11 46 26 72 ] 372
 MMR  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 IM  Load [0 0 0 0 0 0 0 0 ] 0
 IM  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IM  Store [0 0 0 0 0 0 0 0 ] 0
 IM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-IM  L1_to_L2 [264533 264240 265708 266614 267406 266948 265798 264955 ] 2126202
-IM  Other_GETX [0 2 2 0 1 1 1 1 ] 8
-IM  Other_GETS [1 0 2 4 2 1 3 4 ] 17
+IM  L1_to_L2 [266014 266954 266850 265662 266025 261151 267188 267580 ] 2127424
+IM  Other_GETX [0 1 0 0 3 3 1 3 ] 11
+IM  Other_GETS [1 1 2 0 3 1 3 4 ] 15
 IM  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 IM  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 IM  Invalidate [0 0 0 0 0 0 0 0 ] 0
-IM  Ack [184504 184764 185096 184349 185242 184037 184240 184831 ] 1477063
-IM  Data [1047 948 1018 987 1034 1059 1024 1010 ] 8127
-IM  Exclusive_Data [25828 25932 25964 25839 25939 25749 25797 25901 ] 206949
+IM  Ack [184642 185262 185836 185503 184898 182051 184879 186155 ] 1479226
+IM  Data [980 1079 1042 1047 1041 1037 1034 1026 ] 8286
+IM  Exclusive_Data [25873 25859 26013 25943 25890 25427 25880 26071 ] 206956
 IM  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 SM  Load [0 0 0 0 0 0 0 0 ] 0
 SM  Ifetch [0 0 0 0 0 0 0 0 ] 0
 SM  Store [0 0 0 0 0 0 0 0 ] 0
 SM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-SM  L1_to_L2 [0 14 0 0 18 22 0 2 ] 56
+SM  L1_to_L2 [19 0 0 21 57 38 12 0 ] 147
 SM  Other_GETX [0 0 0 0 0 0 0 0 ] 0
 SM  Other_GETS [0 0 0 0 0 0 0 0 ] 0
 SM  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 SM  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 SM  Invalidate [0 0 0 0 0 0 0 0 ] 0
-SM  Ack [4 14 0 0 14 7 0 11 ] 50
-SM  Data [1 2 1 0 2 1 0 2 ] 9
+SM  Ack [14 7 14 14 7 14 7 14 ] 91
+SM  Data [2 1 3 2 1 2 1 2 ] 14
 SM  Exclusive_Data [0 0 0 0 0 0 0 0 ] 0
 SM  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
@@ -559,16 +559,16 @@ OM  Load [0 0 0 0 0 0 0 0 ] 0
 OM  Ifetch [0 0 0 0 0 0 0 0 ] 0
 OM  Store [0 0 0 0 0 0 0 0 ] 0
 OM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-OM  L1_to_L2 [0 4 0 0 0 0 0 0 ] 4
+OM  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
 OM  Other_GETX [0 0 0 0 0 0 0 0 ] 0
 OM  Other_GETS [0 0 0 0 0 0 0 0 ] 0
 OM  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 OM  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 OM  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 OM  Invalidate [0 0 0 0 0 0 0 0 ] 0
-OM  Ack [0 7 7 7 0 0 0 0 ] 21
+OM  Ack [0 0 0 0 0 7 0 0 ] 7
 OM  All_acks [0 0 0 0 0 0 0 0 ] 0
-OM  All_acks_no_sharers [0 1 1 1 0 0 0 0 ] 3
+OM  All_acks_no_sharers [0 0 0 0 0 1 0 0 ] 1
 OM  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 ISM  Load [0 0 0 0 0 0 0 0 ] 0
@@ -576,59 +576,59 @@ ISM  Ifetch [0 0 0 0 0 0 0 0 ] 0
 ISM  Store [0 0 0 0 0 0 0 0 ] 0
 ISM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
 ISM  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
-ISM  Ack [44 20 30 27 24 25 36 25 ] 231
-ISM  All_acks_no_sharers [1048 950 1019 987 1036 1060 1024 1012 ] 8136
+ISM  Ack [22 37 35 20 24 15 35 28 ] 216
+ISM  All_acks_no_sharers [982 1080 1045 1049 1042 1039 1035 1028 ] 8300
 ISM  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 M_W  Load [0 0 0 0 0 0 0 0 ] 0
 M_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
 M_W  Store [0 0 0 0 0 0 0 0 ] 0
 M_W  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-M_W  L1_to_L2 [382 490 447 566 427 335 385 442 ] 3474
-M_W  Ack [1654 1801 1575 1681 1754 1866 1695 1775 ] 13801
-M_W  All_acks_no_sharers [46730 47046 47130 46884 47031 47078 46970 46653 ] 375522
+M_W  L1_to_L2 [461 361 651 660 482 490 479 531 ] 4115
+M_W  Ack [1518 1555 1755 1715 1738 1699 1935 1901 ] 13816
+M_W  All_acks_no_sharers [46891 47021 47102 46265 47166 46874 47086 46810 ] 375215
 M_W  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 MM_W  Load [0 0 0 0 0 0 0 0 ] 0
 MM_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
 MM_W  Store [0 0 0 0 0 0 0 0 ] 0
 MM_W  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-MM_W  L1_to_L2 [771 629 867 688 821 706 544 740 ] 5766
-MM_W  Ack [2679 2527 2817 2557 2639 2689 2606 2621 ] 21135
-MM_W  All_acks_no_sharers [25828 25932 25964 25839 25939 25749 25797 25901 ] 206949
+MM_W  L1_to_L2 [686 568 622 740 617 785 679 746 ] 5443
+MM_W  Ack [2474 2435 2636 2518 2705 2372 2595 2622 ] 20357
+MM_W  All_acks_no_sharers [25873 25859 26013 25943 25890 25427 25880 26071 ] 206956
 MM_W  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 IS  Load [0 0 0 0 0 0 0 0 ] 0
 IS  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IS  Store [0 0 0 0 0 0 0 0 ] 0
 IS  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-IS  L1_to_L2 [492793 495699 497214 492941 493897 494126 491880 492991 ] 3951541
-IS  Other_GETX [1 2 3 0 4 4 2 2 ] 18
-IS  Other_GETS [4 3 6 6 7 7 0 3 ] 36
+IS  L1_to_L2 [491681 493311 495276 491402 493448 494573 495016 492834 ] 3947541
+IS  Other_GETX [0 1 2 1 2 5 2 3 ] 16
+IS  Other_GETS [4 1 9 3 5 4 1 3 ] 30
 IS  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 IS  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 IS  Invalidate [0 0 0 0 0 0 0 0 ] 0
-IS  Ack [340795 342596 344094 342035 343123 343445 342303 340049 ] 2738440
-IS  Shared_Ack [63 50 57 54 60 52 49 55 ] 440
-IS  Data [1819 1820 1869 1850 1889 1909 1823 1850 ] 14829
-IS  Shared_Data [1047 1013 1104 1046 1030 1019 1021 1023 ] 8303
-IS  Exclusive_Data [46730 47046 47130 46884 47031 47078 46970 46653 ] 375522
+IS  Ack [342945 343676 344139 337911 344178 342290 343041 341535 ] 2739715
+IS  Shared_Ack [65 54 54 52 58 49 50 56 ] 438
+IS  Data [1953 1904 1933 1899 1894 1924 1849 1903 ] 15259
+IS  Shared_Data [1031 1085 1122 1041 1068 998 1047 1069 ] 8461
+IS  Exclusive_Data [46891 47021 47102 46265 47166 46874 47086 46810 ] 375215
 IS  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 SS  Load [0 0 0 0 0 0 0 0 ] 0
 SS  Ifetch [0 0 0 0 0 0 0 0 ] 0
 SS  Store [0 0 0 0 0 0 0 0 ] 0
 SS  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-SS  L1_to_L2 [835 899 807 727 760 923 728 746 ] 6425
-SS  Ack [3035 3091 3316 3012 3039 3004 3054 3185 ] 24736
-SS  Shared_Ack [3 2 3 6 2 2 11 3 ] 32
-SS  All_acks [1108 1061 1151 1098 1087 1067 1066 1076 ] 8714
-SS  All_acks_no_sharers [1758 1772 1822 1798 1832 1861 1778 1797 ] 14418
+SS  L1_to_L2 [745 939 852 749 800 595 748 851 ] 6279
+SS  Ack [3029 3159 3392 3119 3240 2957 3150 3286 ] 25332
+SS  Shared_Ack [1 1 5 4 5 4 4 5 ] 29
+SS  All_acks [1093 1136 1173 1091 1122 1044 1097 1120 ] 8876
+SS  All_acks_no_sharers [1891 1853 1882 1849 1840 1878 1799 1852 ] 14844
 SS  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
-OI  Load [0 0 0 0 1 0 0 0 ] 1
+OI  Load [0 0 0 1 1 0 0 0 ] 2
 OI  Ifetch [0 0 0 0 0 0 0 0 ] 0
-OI  Store [0 0 0 0 0 0 1 0 ] 1
+OI  Store [0 0 0 0 0 0 0 0 ] 0
 OI  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
 OI  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
 OI  Other_GETX [0 0 0 0 0 0 0 0 ] 0
@@ -637,21 +637,21 @@ OI  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 OI  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 OI  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 OI  Invalidate [0 0 0 0 0 0 0 0 ] 0
-OI  Writeback_Ack [1053 1043 994 1044 953 986 1010 1045 ] 8128
+OI  Writeback_Ack [1026 1047 1040 1025 1045 1035 1065 1015 ] 8298
 OI  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
-MI  Load [10 17 7 7 11 15 9 8 ] 84
+MI  Load [8 7 5 6 9 5 4 8 ] 52
 MI  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MI  Store [4 7 9 6 4 4 3 6 ] 43
+MI  Store [5 8 4 6 3 5 2 4 ] 37
 MI  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
 MI  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
-MI  Other_GETX [1 2 0 0 1 3 2 1 ] 10
-MI  Other_GETS [3 4 0 3 5 3 0 0 ] 18
+MI  Other_GETX [3 2 0 1 2 3 1 0 ] 12
+MI  Other_GETS [3 2 1 3 3 1 2 2 ] 17
 MI  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 MI  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 MI  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 MI  Invalidate [0 0 0 0 0 0 0 0 ] 0
-MI  Writeback_Ack [71027 71417 71637 71178 71560 71404 71272 71098 ] 570593
+MI  Writeback_Ack [71227 71446 71660 70776 71591 70844 71510 71480 ] 570534
 MI  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 II  Load [0 0 0 0 0 0 0 0 ] 0
@@ -664,44 +664,44 @@ II  Other_GETS [0 0 0 0 0 0 0 0 ] 0
 II  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 II  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 II  Invalidate [0 0 0 0 0 0 0 0 ] 0
-II  Writeback_Ack [1 2 0 0 1 3 2 1 ] 10
+II  Writeback_Ack [3 2 0 1 2 3 1 0 ] 12
 II  Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
 II  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
-IT  Load [0 0 0 2 1 0 1 1 ] 5
+IT  Load [0 0 0 0 1 1 2 1 ] 5
 IT  Ifetch [0 0 0 0 0 0 0 0 ] 0
-IT  Store [0 0 0 0 0 1 0 0 ] 1
+IT  Store [1 0 1 0 0 1 0 0 ] 3
 IT  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-IT  L1_to_L2 [0 0 4 17 9 4 11 7 ] 52
-IT  Complete_L2_to_L1 [0 0 1 4 2 1 2 3 ] 13
+IT  L1_to_L2 [0 0 0 0 3 5 19 0 ] 27
+IT  Complete_L2_to_L1 [1 0 1 0 3 2 2 1 ] 10
 
-ST  Load [1 0 0 1 2 1 0 1 ] 6
+ST  Load [1 0 2 1 0 0 0 0 ] 4
 ST  Ifetch [0 0 0 0 0 0 0 0 ] 0
-ST  Store [1 0 0 0 1 0 0 0 ] 2
+ST  Store [1 0 1 1 0 1 0 0 ] 4
 ST  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-ST  L1_to_L2 [7 8 1 10 35 19 0 8 ] 88
-ST  Complete_L2_to_L1 [2 2 1 2 5 7 0 3 ] 22
+ST  L1_to_L2 [13 0 21 13 22 21 6 17 ] 113
+ST  Complete_L2_to_L1 [4 2 3 2 3 2 1 5 ] 22
 
-OT  Load [1 0 0 1 0 0 1 1 ] 4
+OT  Load [1 1 2 0 0 0 0 0 ] 4
 OT  Ifetch [0 0 0 0 0 0 0 0 ] 0
 OT  Store [0 0 0 0 0 0 0 0 ] 0
 OT  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-OT  L1_to_L2 [1 13 0 11 3 0 9 14 ] 51
-OT  Complete_L2_to_L1 [1 2 1 3 1 0 1 3 ] 12
+OT  L1_to_L2 [0 0 15 9 3 0 0 0 ] 27
+OT  Complete_L2_to_L1 [1 1 2 2 1 2 0 0 ] 9
 
-MT  Load [13 18 12 13 2 15 10 9 ] 92
+MT  Load [12 13 10 13 9 15 15 15 ] 102
 MT  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MT  Store [12 6 8 3 5 9 9 5 ] 57
+MT  Store [6 7 7 10 6 7 2 10 ] 55
 MT  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-MT  L1_to_L2 [140 158 137 149 48 194 131 150 ] 1107
-MT  Complete_L2_to_L1 [48 39 47 53 31 49 31 49 ] 347
+MT  L1_to_L2 [172 140 96 193 118 125 106 184 ] 1134
+MT  Complete_L2_to_L1 [37 46 39 56 37 44 44 51 ] 354
 
-MMT  Load [5 3 9 8 9 5 7 4 ] 50
+MMT  Load [5 5 11 12 6 7 4 7 ] 57
 MMT  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MMT  Store [3 3 2 2 3 3 3 2 ] 21
+MMT  Store [0 0 5 4 3 4 1 8 ] 25
 MMT  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-MMT  L1_to_L2 [44 47 69 115 163 105 61 52 ] 656
-MMT  Complete_L2_to_L1 [22 18 24 22 31 25 23 18 ] 183
+MMT  L1_to_L2 [52 62 128 91 55 162 37 197 ] 784
+MMT  Complete_L2_to_L1 [20 18 34 29 24 30 15 33 ] 203
 
 MI_F  Load [0 0 0 0 0 0 0 0 ] 0
 MI_F  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -799,28 +799,28 @@ Cache Stats: system.l1_cntrl1.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl1.L1DcacheMemory
-  system.l1_cntrl1.L1DcacheMemory_total_misses: 76900
-  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 76900
+  system.l1_cntrl1.L1DcacheMemory_total_misses: 76346
+  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 76346
   system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl1.L1DcacheMemory_request_type_LD:   65.0988%
-  system.l1_cntrl1.L1DcacheMemory_request_type_ST:   34.9012%
+  system.l1_cntrl1.L1DcacheMemory_request_type_LD:   65.2935%
+  system.l1_cntrl1.L1DcacheMemory_request_type_ST:   34.7065%
 
-  system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor:   76900    100%
+  system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor:   76346    100%
 
 Cache Stats: system.l1_cntrl1.L2cacheMemory
-  system.l1_cntrl1.L2cacheMemory_total_misses: 76900
-  system.l1_cntrl1.L2cacheMemory_total_demand_misses: 76900
+  system.l1_cntrl1.L2cacheMemory_total_misses: 76346
+  system.l1_cntrl1.L2cacheMemory_total_demand_misses: 76346
   system.l1_cntrl1.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl1.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl1.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl1.L2cacheMemory_request_type_LD:   65.0988%
-  system.l1_cntrl1.L2cacheMemory_request_type_ST:   34.9012%
+  system.l1_cntrl1.L2cacheMemory_request_type_LD:   65.2935%
+  system.l1_cntrl1.L2cacheMemory_request_type_ST:   34.7065%
 
-  system.l1_cntrl1.L2cacheMemory_access_mode_type_Supervisor:   76900    100%
+  system.l1_cntrl1.L2cacheMemory_access_mode_type_Supervisor:   76346    100%
 
 Cache Stats: system.l1_cntrl2.L1IcacheMemory
   system.l1_cntrl2.L1IcacheMemory_total_misses: 0
@@ -831,28 +831,28 @@ Cache Stats: system.l1_cntrl2.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl2.L1DcacheMemory
-  system.l1_cntrl2.L1DcacheMemory_total_misses: 76694
-  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76694
+  system.l1_cntrl2.L1DcacheMemory_total_misses: 76963
+  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76963
   system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl2.L1DcacheMemory_request_type_LD:   65.0025%
-  system.l1_cntrl2.L1DcacheMemory_request_type_ST:   34.9975%
+  system.l1_cntrl2.L1DcacheMemory_request_type_LD:   65.0027%
+  system.l1_cntrl2.L1DcacheMemory_request_type_ST:   34.9973%
 
-  system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor:   76694    100%
+  system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor:   76963    100%
 
 Cache Stats: system.l1_cntrl2.L2cacheMemory
-  system.l1_cntrl2.L2cacheMemory_total_misses: 76694
-  system.l1_cntrl2.L2cacheMemory_total_demand_misses: 76694
+  system.l1_cntrl2.L2cacheMemory_total_misses: 76963
+  system.l1_cntrl2.L2cacheMemory_total_demand_misses: 76963
   system.l1_cntrl2.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl2.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl2.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl2.L2cacheMemory_request_type_LD:   65.0025%
-  system.l1_cntrl2.L2cacheMemory_request_type_ST:   34.9975%
+  system.l1_cntrl2.L2cacheMemory_request_type_LD:   65.0027%
+  system.l1_cntrl2.L2cacheMemory_request_type_ST:   34.9973%
 
-  system.l1_cntrl2.L2cacheMemory_access_mode_type_Supervisor:   76694    100%
+  system.l1_cntrl2.L2cacheMemory_access_mode_type_Supervisor:   76963    100%
 
 Cache Stats: system.l1_cntrl3.L1IcacheMemory
   system.l1_cntrl3.L1IcacheMemory_total_misses: 0
@@ -863,28 +863,28 @@ Cache Stats: system.l1_cntrl3.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl3.L1DcacheMemory
-  system.l1_cntrl3.L1DcacheMemory_total_misses: 76518
-  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 76518
+  system.l1_cntrl3.L1DcacheMemory_total_misses: 76973
+  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 76973
   system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl3.L1DcacheMemory_request_type_LD:   64.7939%
-  system.l1_cntrl3.L1DcacheMemory_request_type_ST:   35.2061%
+  system.l1_cntrl3.L1DcacheMemory_request_type_LD:   64.7422%
+  system.l1_cntrl3.L1DcacheMemory_request_type_ST:   35.2578%
 
-  system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor:   76518    100%
+  system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor:   76973    100%
 
 Cache Stats: system.l1_cntrl3.L2cacheMemory
-  system.l1_cntrl3.L2cacheMemory_total_misses: 76518
-  system.l1_cntrl3.L2cacheMemory_total_demand_misses: 76518
+  system.l1_cntrl3.L2cacheMemory_total_misses: 76973
+  system.l1_cntrl3.L2cacheMemory_total_demand_misses: 76973
   system.l1_cntrl3.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl3.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl3.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl3.L2cacheMemory_request_type_LD:   64.7939%
-  system.l1_cntrl3.L2cacheMemory_request_type_ST:   35.2061%
+  system.l1_cntrl3.L2cacheMemory_request_type_LD:   64.7422%
+  system.l1_cntrl3.L2cacheMemory_request_type_ST:   35.2578%
 
-  system.l1_cntrl3.L2cacheMemory_access_mode_type_Supervisor:   76518    100%
+  system.l1_cntrl3.L2cacheMemory_access_mode_type_Supervisor:   76973    100%
 
 Cache Stats: system.l1_cntrl4.L1IcacheMemory
   system.l1_cntrl4.L1IcacheMemory_total_misses: 0
@@ -895,28 +895,28 @@ Cache Stats: system.l1_cntrl4.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl4.L1DcacheMemory
-  system.l1_cntrl4.L1DcacheMemory_total_misses: 76548
-  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 76548
+  system.l1_cntrl4.L1DcacheMemory_total_misses: 76796
+  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 76796
   system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl4.L1DcacheMemory_request_type_LD:   64.8587%
-  system.l1_cntrl4.L1DcacheMemory_request_type_ST:   35.1413%
+  system.l1_cntrl4.L1DcacheMemory_request_type_LD:   65.0034%
+  system.l1_cntrl4.L1DcacheMemory_request_type_ST:   34.9966%
 
-  system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor:   76548    100%
+  system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor:   76796    100%
 
 Cache Stats: system.l1_cntrl4.L2cacheMemory
-  system.l1_cntrl4.L2cacheMemory_total_misses: 76548
-  system.l1_cntrl4.L2cacheMemory_total_demand_misses: 76548
+  system.l1_cntrl4.L2cacheMemory_total_misses: 76796
+  system.l1_cntrl4.L2cacheMemory_total_demand_misses: 76796
   system.l1_cntrl4.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl4.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl4.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl4.L2cacheMemory_request_type_LD:   64.8587%
-  system.l1_cntrl4.L2cacheMemory_request_type_ST:   35.1413%
+  system.l1_cntrl4.L2cacheMemory_request_type_LD:   65.0034%
+  system.l1_cntrl4.L2cacheMemory_request_type_ST:   34.9966%
 
-  system.l1_cntrl4.L2cacheMemory_access_mode_type_Supervisor:   76548    100%
+  system.l1_cntrl4.L2cacheMemory_access_mode_type_Supervisor:   76796    100%
 
 Cache Stats: system.l1_cntrl5.L1IcacheMemory
   system.l1_cntrl5.L1IcacheMemory_total_misses: 0
@@ -927,28 +927,28 @@ Cache Stats: system.l1_cntrl5.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl5.L1DcacheMemory
-  system.l1_cntrl5.L1DcacheMemory_total_misses: 76826
-  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 76826
+  system.l1_cntrl5.L1DcacheMemory_total_misses: 77019
+  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 77019
   system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl5.L1DcacheMemory_request_type_LD:   64.9767%
-  system.l1_cntrl5.L1DcacheMemory_request_type_ST:   35.0233%
+  system.l1_cntrl5.L1DcacheMemory_request_type_LD:   64.9944%
+  system.l1_cntrl5.L1DcacheMemory_request_type_ST:   35.0056%
 
-  system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor:   76826    100%
+  system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor:   77019    100%
 
 Cache Stats: system.l1_cntrl5.L2cacheMemory
-  system.l1_cntrl5.L2cacheMemory_total_misses: 76826
-  system.l1_cntrl5.L2cacheMemory_total_demand_misses: 76826
+  system.l1_cntrl5.L2cacheMemory_total_misses: 77019
+  system.l1_cntrl5.L2cacheMemory_total_demand_misses: 77019
   system.l1_cntrl5.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl5.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl5.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl5.L2cacheMemory_request_type_LD:   64.9767%
-  system.l1_cntrl5.L2cacheMemory_request_type_ST:   35.0233%
+  system.l1_cntrl5.L2cacheMemory_request_type_LD:   64.9944%
+  system.l1_cntrl5.L2cacheMemory_request_type_ST:   35.0056%
 
-  system.l1_cntrl5.L2cacheMemory_access_mode_type_Supervisor:   76826    100%
+  system.l1_cntrl5.L2cacheMemory_access_mode_type_Supervisor:   77019    100%
 
 Cache Stats: system.l1_cntrl6.L1IcacheMemory
   system.l1_cntrl6.L1IcacheMemory_total_misses: 0
@@ -959,28 +959,28 @@ Cache Stats: system.l1_cntrl6.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl6.L1DcacheMemory
-  system.l1_cntrl6.L1DcacheMemory_total_misses: 77165
-  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 77165
+  system.l1_cntrl6.L1DcacheMemory_total_misses: 77296
+  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 77296
   system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl6.L1DcacheMemory_request_type_LD:   65.001%
-  system.l1_cntrl6.L1DcacheMemory_request_type_ST:   34.999%
+  system.l1_cntrl6.L1DcacheMemory_request_type_LD:   64.962%
+  system.l1_cntrl6.L1DcacheMemory_request_type_ST:   35.038%
 
-  system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor:   77165    100%
+  system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor:   77296    100%
 
 Cache Stats: system.l1_cntrl6.L2cacheMemory
-  system.l1_cntrl6.L2cacheMemory_total_misses: 77165
-  system.l1_cntrl6.L2cacheMemory_total_demand_misses: 77165
+  system.l1_cntrl6.L2cacheMemory_total_misses: 77296
+  system.l1_cntrl6.L2cacheMemory_total_demand_misses: 77296
   system.l1_cntrl6.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl6.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl6.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl6.L2cacheMemory_request_type_LD:   65.001%
-  system.l1_cntrl6.L2cacheMemory_request_type_ST:   34.999%
+  system.l1_cntrl6.L2cacheMemory_request_type_LD:   64.962%
+  system.l1_cntrl6.L2cacheMemory_request_type_ST:   35.038%
 
-  system.l1_cntrl6.L2cacheMemory_access_mode_type_Supervisor:   77165    100%
+  system.l1_cntrl6.L2cacheMemory_access_mode_type_Supervisor:   77296    100%
 
 Cache Stats: system.l1_cntrl7.L1IcacheMemory
   system.l1_cntrl7.L1IcacheMemory_total_misses: 0
@@ -991,28 +991,28 @@ Cache Stats: system.l1_cntrl7.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl7.L1DcacheMemory
-  system.l1_cntrl7.L1DcacheMemory_total_misses: 76693
-  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 76693
+  system.l1_cntrl7.L1DcacheMemory_total_misses: 76288
+  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 76288
   system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl7.L1DcacheMemory_request_type_LD:   64.9799%
-  system.l1_cntrl7.L1DcacheMemory_request_type_ST:   35.0201%
+  system.l1_cntrl7.L1DcacheMemory_request_type_LD:   64.5737%
+  system.l1_cntrl7.L1DcacheMemory_request_type_ST:   35.4263%
 
-  system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor:   76693    100%
+  system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor:   76288    100%
 
 Cache Stats: system.l1_cntrl7.L2cacheMemory
-  system.l1_cntrl7.L2cacheMemory_total_misses: 76693
-  system.l1_cntrl7.L2cacheMemory_total_demand_misses: 76693
+  system.l1_cntrl7.L2cacheMemory_total_misses: 76288
+  system.l1_cntrl7.L2cacheMemory_total_demand_misses: 76288
   system.l1_cntrl7.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl7.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl7.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl7.L2cacheMemory_request_type_LD:   64.9799%
-  system.l1_cntrl7.L2cacheMemory_request_type_ST:   35.0201%
+  system.l1_cntrl7.L2cacheMemory_request_type_LD:   64.5737%
+  system.l1_cntrl7.L2cacheMemory_request_type_ST:   35.4263%
 
-  system.l1_cntrl7.L2cacheMemory_access_mode_type_Supervisor:   76693    100%
+  system.l1_cntrl7.L2cacheMemory_access_mode_type_Supervisor:   76288    100%
 
 Cache Stats: system.dir_cntrl0.probeFilter
   system.dir_cntrl0.probeFilter_total_misses: 0
@@ -1023,42 +1023,42 @@ Cache Stats: system.dir_cntrl0.probeFilter
 
 
 Memory controller: system.dir_cntrl0.memBuffer:
-  memory_total_requests: 806220
-  memory_reads: 593611
-  memory_writes: 212580
-  memory_refreshes: 39826
-  memory_total_request_delays: 51296531
-  memory_delays_per_request: 63.626
-  memory_delays_in_input_queue: 641947
-  memory_delays_behind_head_of_bank_queue: 20918876
-  memory_delays_stalled_at_head_of_bank_queue: 29735708
-  memory_stalls_for_bank_busy: 4484100
+  memory_total_requests: 806978
+  memory_reads: 594147
+  memory_writes: 212804
+  memory_refreshes: 39853
+  memory_total_request_delays: 51488975
+  memory_delays_per_request: 63.8047
+  memory_delays_in_input_queue: 640640
+  memory_delays_behind_head_of_bank_queue: 21056513
+  memory_delays_stalled_at_head_of_bank_queue: 29791822
+  memory_stalls_for_bank_busy: 4491676
   memory_stalls_for_random_busy: 0
-  memory_stalls_for_anti_starvation: 7559065
-  memory_stalls_for_arbitration: 6077618
-  memory_stalls_for_bus: 8234780
+  memory_stalls_for_anti_starvation: 7566963
+  memory_stalls_for_arbitration: 6096462
+  memory_stalls_for_bus: 8254664
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 2033604
-  memory_stalls_for_read_read_turnaround: 1346541
-  accesses_per_bank: 25391  25095  25195  25436  25423  25329  25505  25282  25433  25236  25299  25341  24983  25035  25236  25016  25189  25143  25202  25157  25159  25118  25288  25048  25026  24716  25150  24719  25030  25301  25457  25282  
+  memory_stalls_for_read_write_turnaround: 2034613
+  memory_stalls_for_read_read_turnaround: 1347444
+  accesses_per_bank: 25429  25104  25218  25413  25515  25350  25511  25319  25424  25266  25320  25413  25039  25054  25226  25087  25177  25156  25231  25182  25251  25130  25286  25091  25061  24766  25133  24750  25104  25281  25420  25271  
 
  --- Directory ---
  - Event Counts -
-GETX [218327 ] 218327
-GETS [404573 ] 404573
-PUT [578930 ] 578930
-Unblock [10 ] 10
-UnblockS [23132 ] 23132
-UnblockM [590609 ] 590609
-Writeback_Clean [8017 ] 8017
-Writeback_Dirty [111 ] 111
-Writeback_Exclusive_Clean [358112 ] 358112
-Writeback_Exclusive_Dirty [212481 ] 212481
+GETX [218472 ] 218472
+GETS [404812 ] 404812
+PUT [579033 ] 579033
+Unblock [12 ] 12
+UnblockS [23720 ] 23720
+UnblockM [590471 ] 590471
+Writeback_Clean [8200 ] 8200
+Writeback_Dirty [98 ] 98
+Writeback_Exclusive_Clean [357818 ] 357818
+Writeback_Exclusive_Dirty [212716 ] 212716
 Pf_Replacement [0 ] 0
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
-Memory_Data [593609 ] 593609
-Memory_Ack [212577 ] 212577
+Memory_Data [594143 ] 594143
+Memory_Ack [212804 ] 212804
 Ack [0 ] 0
 Shared_Ack [0 ] 0
 Shared_Data [0 ] 0
@@ -1067,22 +1067,22 @@ Exclusive_Data [0 ] 0
 All_acks_and_shared_data [0 ] 0
 All_acks_and_owner_data [0 ] 0
 All_acks_and_data_no_sharers [0 ] 0
-All_Unblocks [39 ] 39
+All_Unblocks [35 ] 35
 GETF [0 ] 0
 PUTF [0 ] 0
 
  - Transitions -
-NX  GETX [75 ] 75
-NX  GETS [86 ] 86
-NX  PUT [8138 ] 8138
+NX  GETX [62 ] 62
+NX  GETS [85 ] 85
+NX  PUT [8309 ] 8309
 NX  Pf_Replacement [0 ] 0
 NX  DMA_READ [0 ] 0
 NX  DMA_WRITE [0 ] 0
 NX  GETF [0 ] 0
 
-NO  GETX [7079 ] 7079
-NO  GETS [12854 ] 12854
-NO  PUT [570595 ] 570595
+NO  GETX [6897 ] 6897
+NO  GETS [12969 ] 12969
+NO  PUT [570535 ] 570535
 NO  Pf_Replacement [0 ] 0
 NO  DMA_READ [0 ] 0
 NO  DMA_WRITE [0 ] 0
@@ -1096,16 +1096,16 @@ S  DMA_READ [0 ] 0
 S  DMA_WRITE [0 ] 0
 S  GETF [0 ] 0
 
-O  GETX [8054 ] 8054
-O  GETS [14830 ] 14830
+O  GETX [8228 ] 8228
+O  GETS [15260 ] 15260
 O  PUT [0 ] 0
 O  Pf_Replacement [0 ] 0
 O  DMA_READ [0 ] 0
 O  DMA_WRITE [0 ] 0
 O  GETF [0 ] 0
 
-E  GETX [199886 ] 199886
-E  GETS [370858 ] 370858
+E  GETX [200078 ] 200078
+E  GETS [370598 ] 370598
 E  PUT [0 ] 0
 E  DMA_READ [0 ] 0
 E  DMA_WRITE [0 ] 0
@@ -1144,11 +1144,11 @@ NO_R  Exclusive_Data [0 ] 0
 NO_R  All_acks_and_data_no_sharers [0 ] 0
 NO_R  GETF [0 ] 0
 
-NO_B  GETX [17 ] 17
-NO_B  GETS [39 ] 39
-NO_B  PUT [197 ] 197
-NO_B  UnblockS [8245 ] 8245
-NO_B  UnblockM [590572 ] 590572
+NO_B  GETX [21 ] 21
+NO_B  GETS [35 ] 35
+NO_B  PUT [189 ] 189
+NO_B  UnblockS [8402 ] 8402
+NO_B  UnblockM [590438 ] 590438
 NO_B  Pf_Replacement [0 ] 0
 NO_B  DMA_READ [0 ] 0
 NO_B  DMA_WRITE [0 ] 0
@@ -1157,18 +1157,18 @@ NO_B  GETF [0 ] 0
 NO_B_X  GETX [0 ] 0
 NO_B_X  GETS [0 ] 0
 NO_B_X  PUT [0 ] 0
-NO_B_X  UnblockS [6 ] 6
-NO_B_X  UnblockM [11 ] 11
+NO_B_X  UnblockS [9 ] 9
+NO_B_X  UnblockM [12 ] 12
 NO_B_X  Pf_Replacement [0 ] 0
 NO_B_X  DMA_READ [0 ] 0
 NO_B_X  DMA_WRITE [0 ] 0
 NO_B_X  GETF [0 ] 0
 
 NO_B_S  GETX [0 ] 0
-NO_B_S  GETS [0 ] 0
+NO_B_S  GETS [1 ] 1
 NO_B_S  PUT [0 ] 0
-NO_B_S  UnblockS [13 ] 13
-NO_B_S  UnblockM [26 ] 26
+NO_B_S  UnblockS [14 ] 14
+NO_B_S  UnblockM [21 ] 21
 NO_B_S  Pf_Replacement [0 ] 0
 NO_B_S  DMA_READ [0 ] 0
 NO_B_S  DMA_WRITE [0 ] 0
@@ -1177,42 +1177,42 @@ NO_B_S  GETF [0 ] 0
 NO_B_S_W  GETX [0 ] 0
 NO_B_S_W  GETS [0 ] 0
 NO_B_S_W  PUT [0 ] 0
-NO_B_S_W  UnblockS [39 ] 39
+NO_B_S_W  UnblockS [36 ] 36
 NO_B_S_W  Pf_Replacement [0 ] 0
 NO_B_S_W  DMA_READ [0 ] 0
 NO_B_S_W  DMA_WRITE [0 ] 0
-NO_B_S_W  All_Unblocks [39 ] 39
+NO_B_S_W  All_Unblocks [35 ] 35
 NO_B_S_W  GETF [0 ] 0
 
 O_B  GETX [0 ] 0
 O_B  GETS [0 ] 0
 O_B  PUT [0 ] 0
-O_B  UnblockS [14829 ] 14829
+O_B  UnblockS [15259 ] 15259
 O_B  UnblockM [0 ] 0
 O_B  Pf_Replacement [0 ] 0
 O_B  DMA_READ [0 ] 0
 O_B  DMA_WRITE [0 ] 0
 O_B  GETF [0 ] 0
 
-NO_B_W  GETX [2028 ] 2028
-NO_B_W  GETS [3704 ] 3704
+NO_B_W  GETX [2020 ] 2020
+NO_B_W  GETS [3705 ] 3705
 NO_B_W  PUT [0 ] 0
 NO_B_W  UnblockS [0 ] 0
 NO_B_W  UnblockM [0 ] 0
 NO_B_W  Pf_Replacement [0 ] 0
 NO_B_W  DMA_READ [0 ] 0
 NO_B_W  DMA_WRITE [0 ] 0
-NO_B_W  Memory_Data [578780 ] 578780
+NO_B_W  Memory_Data [578884 ] 578884
 NO_B_W  GETF [0 ] 0
 
-O_B_W  GETX [54 ] 54
-O_B_W  GETS [101 ] 101
+O_B_W  GETX [46 ] 46
+O_B_W  GETS [110 ] 110
 O_B_W  PUT [0 ] 0
 O_B_W  UnblockS [0 ] 0
 O_B_W  Pf_Replacement [0 ] 0
 O_B_W  DMA_READ [0 ] 0
 O_B_W  DMA_WRITE [0 ] 0
-O_B_W  Memory_Data [14829 ] 14829
+O_B_W  Memory_Data [15259 ] 15259
 O_B_W  GETF [0 ] 0
 
 NO_W  GETX [0 ] 0
@@ -1324,34 +1324,34 @@ O_DR_B  All_acks_and_data_no_sharers [0 ] 0
 O_DR_B  GETF [0 ] 0
 
 WB  GETX [78 ] 78
-WB  GETS [181 ] 181
+WB  GETS [149 ] 149
 WB  PUT [0 ] 0
-WB  Unblock [10 ] 10
-WB  Writeback_Clean [8017 ] 8017
-WB  Writeback_Dirty [111 ] 111
-WB  Writeback_Exclusive_Clean [358112 ] 358112
-WB  Writeback_Exclusive_Dirty [212481 ] 212481
+WB  Unblock [12 ] 12
+WB  Writeback_Clean [8200 ] 8200
+WB  Writeback_Dirty [98 ] 98
+WB  Writeback_Exclusive_Clean [357818 ] 357818
+WB  Writeback_Exclusive_Dirty [212716 ] 212716
 WB  Pf_Replacement [0 ] 0
 WB  DMA_READ [0 ] 0
 WB  DMA_WRITE [0 ] 0
 WB  GETF [0 ] 0
 
-WB_O_W  GETX [2 ] 2
-WB_O_W  GETS [1 ] 1
+WB_O_W  GETX [0 ] 0
+WB_O_W  GETS [2 ] 2
 WB_O_W  PUT [0 ] 0
 WB_O_W  Pf_Replacement [0 ] 0
 WB_O_W  DMA_READ [0 ] 0
 WB_O_W  DMA_WRITE [0 ] 0
-WB_O_W  Memory_Ack [111 ] 111
+WB_O_W  Memory_Ack [98 ] 98
 WB_O_W  GETF [0 ] 0
 
-WB_E_W  GETX [1054 ] 1054
-WB_E_W  GETS [1919 ] 1919
+WB_E_W  GETX [1042 ] 1042
+WB_E_W  GETS [1898 ] 1898
 WB_E_W  PUT [0 ] 0
 WB_E_W  Pf_Replacement [0 ] 0
 WB_E_W  DMA_READ [0 ] 0
 WB_E_W  DMA_WRITE [0 ] 0
-WB_E_W  Memory_Ack [212466 ] 212466
+WB_E_W  Memory_Ack [212706 ] 212706
 WB_E_W  GETF [0 ] 0
 
 NO_F  GETX [0 ] 0
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
index 76e60ce82..54ab7e824 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
@@ -1,74 +1,74 @@
-system.cpu4: completed 10000 read, 5428 write accesses @1878499
-system.cpu2: completed 10000 read, 5257 write accesses @1890969
-system.cpu1: completed 10000 read, 5405 write accesses @1903259
-system.cpu0: completed 10000 read, 5442 write accesses @1918699
-system.cpu6: completed 10000 read, 5402 write accesses @1925379
-system.cpu5: completed 10000 read, 5453 write accesses @1936119
-system.cpu3: completed 10000 read, 5383 write accesses @1964689
-system.cpu7: completed 10000 read, 5477 write accesses @1974002
-system.cpu1: completed 20000 read, 10638 write accesses @3776021
-system.cpu2: completed 20000 read, 10480 write accesses @3783438
-system.cpu4: completed 20000 read, 10796 write accesses @3811601
-system.cpu0: completed 20000 read, 10807 write accesses @3816738
-system.cpu5: completed 20000 read, 10791 write accesses @3817028
-system.cpu6: completed 20000 read, 10880 write accesses @3864408
-system.cpu3: completed 20000 read, 10699 write accesses @3874782
-system.cpu7: completed 20000 read, 10804 write accesses @3897609
-system.cpu1: completed 30000 read, 15945 write accesses @5673660
-system.cpu2: completed 30000 read, 16019 write accesses @5707989
-system.cpu5: completed 30000 read, 16239 write accesses @5712028
-system.cpu0: completed 30000 read, 16267 write accesses @5714869
-system.cpu4: completed 30000 read, 16131 write accesses @5724848
-system.cpu6: completed 30000 read, 16235 write accesses @5805664
-system.cpu7: completed 30000 read, 16267 write accesses @5825319
-system.cpu3: completed 30000 read, 16142 write accesses @5867180
-system.cpu1: completed 40000 read, 21307 write accesses @7616560
-system.cpu5: completed 40000 read, 21585 write accesses @7616688
-system.cpu4: completed 40000 read, 21599 write accesses @7620249
-system.cpu2: completed 40000 read, 21389 write accesses @7632909
-system.cpu0: completed 40000 read, 21615 write accesses @7651849
-system.cpu6: completed 40000 read, 21564 write accesses @7709298
-system.cpu7: completed 40000 read, 21695 write accesses @7766209
-system.cpu3: completed 40000 read, 21615 write accesses @7866019
-system.cpu1: completed 50000 read, 26737 write accesses @9546228
-system.cpu0: completed 50000 read, 27083 write accesses @9562439
-system.cpu4: completed 50000 read, 27042 write accesses @9600931
-system.cpu5: completed 50000 read, 27029 write accesses @9601568
-system.cpu2: completed 50000 read, 26802 write accesses @9604629
-system.cpu6: completed 50000 read, 27075 write accesses @9624249
-system.cpu7: completed 50000 read, 27192 write accesses @9660438
-system.cpu3: completed 50000 read, 26887 write accesses @9811479
-system.cpu0: completed 60000 read, 32415 write accesses @11433179
-system.cpu1: completed 60000 read, 32076 write accesses @11442279
-system.cpu2: completed 60000 read, 32076 write accesses @11484389
-system.cpu5: completed 60000 read, 32515 write accesses @11499209
-system.cpu6: completed 60000 read, 32430 write accesses @11544838
-system.cpu7: completed 60000 read, 32529 write accesses @11565479
-system.cpu4: completed 60000 read, 32327 write accesses @11584140
-system.cpu3: completed 60000 read, 32340 write accesses @11706229
-system.cpu0: completed 70000 read, 37881 write accesses @13354669
-system.cpu1: completed 70000 read, 37501 write accesses @13371519
-system.cpu2: completed 70000 read, 37457 write accesses @13403638
-system.cpu5: completed 70000 read, 37825 write accesses @13427069
-system.cpu7: completed 70000 read, 37852 write accesses @13444129
-system.cpu6: completed 70000 read, 37717 write accesses @13454949
-system.cpu4: completed 70000 read, 37625 write accesses @13521929
-system.cpu3: completed 70000 read, 37731 write accesses @13621498
-system.cpu0: completed 80000 read, 43203 write accesses @15289219
-system.cpu5: completed 80000 read, 43091 write accesses @15290788
-system.cpu1: completed 80000 read, 42753 write accesses @15297039
-system.cpu6: completed 80000 read, 43000 write accesses @15306258
-system.cpu2: completed 80000 read, 42737 write accesses @15322288
-system.cpu7: completed 80000 read, 43196 write accesses @15371808
-system.cpu4: completed 80000 read, 43033 write accesses @15469939
-system.cpu3: completed 80000 read, 43097 write accesses @15545999
-system.cpu6: completed 90000 read, 48319 write accesses @17195251
-system.cpu0: completed 90000 read, 48512 write accesses @17243339
-system.cpu1: completed 90000 read, 48287 write accesses @17243789
-system.cpu2: completed 90000 read, 48214 write accesses @17248379
-system.cpu5: completed 90000 read, 48605 write accesses @17266969
-system.cpu7: completed 90000 read, 48606 write accesses @17318949
-system.cpu4: completed 90000 read, 48454 write accesses @17350499
-system.cpu3: completed 90000 read, 48532 write accesses @17502609
-system.cpu6: completed 100000 read, 53736 write accesses @19116079
+system.cpu4: completed 10000 read, 5412 write accesses @1871699
+system.cpu2: completed 10000 read, 5460 write accesses @1893369
+system.cpu1: completed 10000 read, 5378 write accesses @1906861
+system.cpu6: completed 10000 read, 5396 write accesses @1925998
+system.cpu0: completed 10000 read, 5377 write accesses @1932348
+system.cpu5: completed 10000 read, 5525 write accesses @1940098
+system.cpu3: completed 10000 read, 5395 write accesses @1950309
+system.cpu7: completed 10000 read, 5394 write accesses @1966559
+system.cpu1: completed 20000 read, 10544 write accesses @3781959
+system.cpu4: completed 20000 read, 10680 write accesses @3792439
+system.cpu2: completed 20000 read, 10687 write accesses @3801439
+system.cpu3: completed 20000 read, 10623 write accesses @3813939
+system.cpu0: completed 20000 read, 10834 write accesses @3843808
+system.cpu5: completed 20000 read, 10928 write accesses @3845319
+system.cpu6: completed 20000 read, 10782 write accesses @3845558
+system.cpu7: completed 20000 read, 10939 write accesses @3904539
+system.cpu2: completed 30000 read, 15884 write accesses @5673111
+system.cpu4: completed 30000 read, 16055 write accesses @5692488
+system.cpu1: completed 30000 read, 16005 write accesses @5703958
+system.cpu3: completed 30000 read, 16124 write accesses @5726919
+system.cpu5: completed 30000 read, 16307 write accesses @5771630
+system.cpu6: completed 30000 read, 16295 write accesses @5776079
+system.cpu0: completed 30000 read, 16283 write accesses @5776769
+system.cpu7: completed 30000 read, 16366 write accesses @5874559
+system.cpu3: completed 40000 read, 21574 write accesses @7627939
+system.cpu2: completed 40000 read, 21245 write accesses @7628738
+system.cpu1: completed 40000 read, 21306 write accesses @7628758
+system.cpu4: completed 40000 read, 21462 write accesses @7660680
+system.cpu0: completed 40000 read, 21631 write accesses @7675309
+system.cpu5: completed 40000 read, 21626 write accesses @7680509
+system.cpu6: completed 40000 read, 21716 write accesses @7696178
+system.cpu7: completed 40000 read, 21960 write accesses @7863749
+system.cpu0: completed 50000 read, 26830 write accesses @9562969
+system.cpu2: completed 50000 read, 26690 write accesses @9565708
+system.cpu3: completed 50000 read, 26994 write accesses @9575479
+system.cpu4: completed 50000 read, 26869 write accesses @9589449
+system.cpu1: completed 50000 read, 26670 write accesses @9611561
+system.cpu5: completed 50000 read, 27137 write accesses @9617389
+system.cpu6: completed 50000 read, 27275 write accesses @9658029
+system.cpu7: completed 50000 read, 27527 write accesses @9814359
+system.cpu0: completed 60000 read, 32249 write accesses @11423019
+system.cpu3: completed 60000 read, 32267 write accesses @11433399
+system.cpu2: completed 60000 read, 32022 write accesses @11474303
+system.cpu5: completed 60000 read, 32388 write accesses @11521948
+system.cpu4: completed 60000 read, 32356 write accesses @11528079
+system.cpu1: completed 60000 read, 32067 write accesses @11544409
+system.cpu6: completed 60000 read, 32659 write accesses @11548639
+system.cpu7: completed 60000 read, 32942 write accesses @11779569
+system.cpu3: completed 70000 read, 37638 write accesses @13336858
+system.cpu2: completed 70000 read, 37313 write accesses @13368779
+system.cpu0: completed 70000 read, 37676 write accesses @13377210
+system.cpu4: completed 70000 read, 37656 write accesses @13416889
+system.cpu6: completed 70000 read, 38021 write accesses @13465679
+system.cpu5: completed 70000 read, 37732 write accesses @13467391
+system.cpu1: completed 70000 read, 37360 write accesses @13477099
+system.cpu7: completed 70000 read, 38399 write accesses @13717039
+system.cpu3: completed 80000 read, 42978 write accesses @15269199
+system.cpu0: completed 80000 read, 42958 write accesses @15278319
+system.cpu2: completed 80000 read, 42507 write accesses @15310609
+system.cpu4: completed 80000 read, 42937 write accesses @15325761
+system.cpu6: completed 80000 read, 43416 write accesses @15354801
+system.cpu5: completed 80000 read, 43057 write accesses @15376839
+system.cpu1: completed 80000 read, 42520 write accesses @15380279
+system.cpu7: completed 80000 read, 43907 write accesses @15634198
+system.cpu3: completed 90000 read, 48403 write accesses @17192399
+system.cpu0: completed 90000 read, 48519 write accesses @17230959
+system.cpu1: completed 90000 read, 47845 write accesses @17249039
+system.cpu2: completed 90000 read, 47947 write accesses @17255499
+system.cpu6: completed 90000 read, 48741 write accesses @17263669
+system.cpu4: completed 90000 read, 48366 write accesses @17269639
+system.cpu5: completed 90000 read, 48485 write accesses @17297549
+system.cpu7: completed 90000 read, 49327 write accesses @17576399
+system.cpu0: completed 100000 read, 53893 write accesses @19129199
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
index f3d38cede..9fc5d7446 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr  4 2012 12:40:05
-gem5 started Apr  4 2012 14:27:12
-gem5 executing on sc2b0605
+gem5 compiled May  8 2012 15:12:50
+gem5 started May  8 2012 15:36:31
+gem5 executing on piton
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 19116079 because maximum number of loads reached
+Exiting @ tick 19129199 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
index 2aab7ff07..cad2377ee 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.019129                       # Nu
 sim_ticks                                    19129199                       # Number of ticks simulated
 final_tick                                   19129199                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 119117                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 363388                       # Number of bytes of host memory used
-host_seconds                                   160.48                       # Real time elapsed on the host
+host_tick_rate                                 146249                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 369604                       # Number of bytes of host memory used
+host_seconds                                   130.80                       # Real time elapsed on the host
 system.physmem.bytes_read                           0                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
index bcc5fa575..744f07dc5 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,15 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
-memories=system.physmem system.funcmem
+memories=system.funcmem system.physmem
 num_work_ids=16
-physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -19,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.sys_port_proxy.port[0]
+system_port=system.sys_port_proxy.slave[0]
 
 [system.cpu0]
 type=MemTest
@@ -34,9 +40,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[0]
-test=system.l1_cntrl0.sequencer.port[0]
+test=system.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu1]
 type=MemTest
@@ -51,9 +58,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[1]
-test=system.l1_cntrl1.sequencer.port[0]
+test=system.l1_cntrl1.sequencer.slave[0]
 
 [system.cpu2]
 type=MemTest
@@ -68,9 +76,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[2]
-test=system.l1_cntrl2.sequencer.port[0]
+test=system.l1_cntrl2.sequencer.slave[0]
 
 [system.cpu3]
 type=MemTest
@@ -85,9 +94,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[3]
-test=system.l1_cntrl3.sequencer.port[0]
+test=system.l1_cntrl3.sequencer.slave[0]
 
 [system.cpu4]
 type=MemTest
@@ -102,9 +112,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[4]
-test=system.l1_cntrl4.sequencer.port[0]
+test=system.l1_cntrl4.sequencer.slave[0]
 
 [system.cpu5]
 type=MemTest
@@ -119,9 +130,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[5]
-test=system.l1_cntrl5.sequencer.port[0]
+test=system.l1_cntrl5.sequencer.slave[0]
 
 [system.cpu6]
 type=MemTest
@@ -136,9 +148,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[6]
-test=system.l1_cntrl6.sequencer.port[0]
+test=system.l1_cntrl6.sequencer.slave[0]
 
 [system.cpu7]
 type=MemTest
@@ -153,9 +166,10 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[7]
-test=system.l1_cntrl7.sequencer.port[0]
+test=system.l1_cntrl7.sequencer.slave[0]
 
 [system.dir_cntrl0]
 type=Directory_Controller
@@ -175,7 +189,7 @@ version=0
 type=RubyDirectoryMemory
 map_levels=4
 numa_high_bit=6
-size=134217728
+size=268435456
 use_map=false
 version=0
 
@@ -201,8 +215,10 @@ tFaw=0
 version=0
 
 [system.funcmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=false
 latency=30
 latency_var=0
 null=false
@@ -221,6 +237,7 @@ issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
@@ -241,13 +258,14 @@ dcache=system.l1_cntrl0.cacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl0.cacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu0.test
+slave=system.cpu0.test
 
 [system.l1_cntrl1]
 type=L1Cache_Controller
@@ -260,6 +278,7 @@ issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl1.sequencer
 transitions_per_cycle=32
 version=1
@@ -280,13 +299,14 @@ dcache=system.l1_cntrl1.cacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl1.cacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=1
-physMemPort=system.physmem.port[1]
-port=system.cpu1.test
+slave=system.cpu1.test
 
 [system.l1_cntrl2]
 type=L1Cache_Controller
@@ -299,6 +319,7 @@ issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl2.sequencer
 transitions_per_cycle=32
 version=2
@@ -319,13 +340,14 @@ dcache=system.l1_cntrl2.cacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl2.cacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=2
-physMemPort=system.physmem.port[2]
-port=system.cpu2.test
+slave=system.cpu2.test
 
 [system.l1_cntrl3]
 type=L1Cache_Controller
@@ -338,6 +360,7 @@ issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl3.sequencer
 transitions_per_cycle=32
 version=3
@@ -358,13 +381,14 @@ dcache=system.l1_cntrl3.cacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl3.cacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=3
-physMemPort=system.physmem.port[3]
-port=system.cpu3.test
+slave=system.cpu3.test
 
 [system.l1_cntrl4]
 type=L1Cache_Controller
@@ -377,6 +401,7 @@ issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl4.sequencer
 transitions_per_cycle=32
 version=4
@@ -397,13 +422,14 @@ dcache=system.l1_cntrl4.cacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl4.cacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=4
-physMemPort=system.physmem.port[4]
-port=system.cpu4.test
+slave=system.cpu4.test
 
 [system.l1_cntrl5]
 type=L1Cache_Controller
@@ -416,6 +442,7 @@ issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl5.sequencer
 transitions_per_cycle=32
 version=5
@@ -436,13 +463,14 @@ dcache=system.l1_cntrl5.cacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl5.cacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=5
-physMemPort=system.physmem.port[5]
-port=system.cpu5.test
+slave=system.cpu5.test
 
 [system.l1_cntrl6]
 type=L1Cache_Controller
@@ -455,6 +483,7 @@ issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl6.sequencer
 transitions_per_cycle=32
 version=6
@@ -475,13 +504,14 @@ dcache=system.l1_cntrl6.cacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl6.cacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=6
-physMemPort=system.physmem.port[6]
-port=system.cpu6.test
+slave=system.cpu6.test
 
 [system.l1_cntrl7]
 type=L1Cache_Controller
@@ -494,6 +524,7 @@ issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl7.sequencer
 transitions_per_cycle=32
 version=7
@@ -514,30 +545,32 @@ dcache=system.l1_cntrl7.cacheMemory
 deadlock_threshold=1000000
 icache=system.l1_cntrl7.cacheMemory
 max_outstanding_requests=16
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=7
-physMemPort=system.physmem.port[7]
-port=system.cpu7.test
+slave=system.cpu7.test
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
 children=network profiler
 block_size_bytes=64
 clock=1
-mem_size=134217728
+mem_size=268435456
 no_mem_vec=false
 random_seed=1234
 randomization=false
@@ -775,11 +808,12 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-physmem=system.physmem
 ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-physMemPort=system.physmem.port[8]
-port=system.system_port
+slave=system.system_port
 
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
index d3193509d..379029232 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
@@ -7,8 +7,8 @@ RubySystem config:
   cycle_period: 1
   block_size_bytes: 64
   block_size_bits: 6
-  memory_size_bytes: 134217728
-  memory_size_bits: 27
+  memory_size_bytes: 268435456
+  memory_size_bits: 28
 
 Network Configuration
 ---------------------
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/23/2012 05:00:08
+Real time: May/08/2012 15:42:37
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 40
-Elapsed_time_in_minutes: 0.666667
-Elapsed_time_in_hours: 0.0111111
-Elapsed_time_in_days: 0.000462963
+Elapsed_time_in_seconds: 69
+Elapsed_time_in_minutes: 1.15
+Elapsed_time_in_hours: 0.0191667
+Elapsed_time_in_days: 0.000798611
 
-Virtual_time_in_seconds: 40.57
-Virtual_time_in_minutes: 0.676167
-Virtual_time_in_hours:   0.0112694
-Virtual_time_in_days:    0.00046956
+Virtual_time_in_seconds: 68.73
+Virtual_time_in_minutes: 1.1455
+Virtual_time_in_hours:   0.0190917
+Virtual_time_in_days:    0.000795486
 
 Ruby_current_time: 28725020
 Ruby_start_time: 0
 Ruby_cycles: 28725020
 
-mbytes_resident: 41.0898
-mbytes_total: 338.922
-resident_ratio: 0.121237
+mbytes_resident: 59.4102
+mbytes_total: 360.535
+resident_ratio: 0.164783
 
 ruby_cycles_executed: [ 28725021 28725021 28725021 28725021 28725021 28725021 28725021 28725021 ]
 
@@ -118,13 +118,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 22 count: 1233888 average: 0.00745367
 Resource Usage
 --------------
 page_size: 4096
-user_time: 40
+user_time: 68
 system_time: 0
-page_reclaims: 10928
+page_reclaims: 15745
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 168
+block_outputs: 256
 
 Network Stats
 -------------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
index 0a1ec6a6d..4cb3155a6 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:59:28
-gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:41:28
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 28725020 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
index 95c30ab1c..12fdf4aa3 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
@@ -4,21 +4,21 @@ sim_seconds                                  0.028725                       # Nu
 sim_ticks                                    28725020                       # Number of ticks simulated
 final_tick                                   28725020                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 711274                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 347060                       # Number of bytes of host memory used
-host_seconds                                    40.39                       # Real time elapsed on the host
-system.physmem.bytes_read                           0                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+host_tick_rate                                 417169                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 369192                       # Number of bytes of host memory used
+host_seconds                                    68.86                       # Real time elapsed on the host
 system.funcmem.bytes_read                           0                       # Number of bytes read from this memory
 system.funcmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
 system.funcmem.bytes_written                        0                       # Number of bytes written to this memory
 system.funcmem.num_reads                            0                       # Number of read requests responded to by this memory
 system.funcmem.num_writes                           0                       # Number of write requests responded to by this memory
 system.funcmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
 system.cpu0.num_reads                          100000                       # number of read accesses completed
 system.cpu0.num_writes                          53147                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
index 1dd8fc1b6..dfa7c1d18 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem system.funcmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[1]
+system_port=system.membus.slave[1]
 
 [system.cpu0]
 type=MemTest
@@ -49,7 +48,7 @@ test=system.cpu0.l1c.cpu_side
 
 [system.cpu0.l1c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -70,7 +69,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.test
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
 
 [system.cpu1]
 type=MemTest
@@ -93,7 +92,7 @@ test=system.cpu1.l1c.cpu_side
 
 [system.cpu1.l1c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -114,7 +113,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.test
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
 
 [system.cpu2]
 type=MemTest
@@ -137,7 +136,7 @@ test=system.cpu2.l1c.cpu_side
 
 [system.cpu2.l1c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -158,7 +157,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.test
-mem_side=system.toL2Bus.port[3]
+mem_side=system.toL2Bus.slave[2]
 
 [system.cpu3]
 type=MemTest
@@ -181,7 +180,7 @@ test=system.cpu3.l1c.cpu_side
 
 [system.cpu3.l1c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -202,7 +201,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.test
-mem_side=system.toL2Bus.port[4]
+mem_side=system.toL2Bus.slave[3]
 
 [system.cpu4]
 type=MemTest
@@ -225,7 +224,7 @@ test=system.cpu4.l1c.cpu_side
 
 [system.cpu4.l1c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -246,7 +245,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu4.test
-mem_side=system.toL2Bus.port[5]
+mem_side=system.toL2Bus.slave[4]
 
 [system.cpu5]
 type=MemTest
@@ -269,7 +268,7 @@ test=system.cpu5.l1c.cpu_side
 
 [system.cpu5.l1c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -290,7 +289,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu5.test
-mem_side=system.toL2Bus.port[6]
+mem_side=system.toL2Bus.slave[5]
 
 [system.cpu6]
 type=MemTest
@@ -313,7 +312,7 @@ test=system.cpu6.l1c.cpu_side
 
 [system.cpu6.l1c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -334,7 +333,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu6.test
-mem_side=system.toL2Bus.port[7]
+mem_side=system.toL2Bus.slave[6]
 
 [system.cpu7]
 type=MemTest
@@ -357,7 +356,7 @@ test=system.cpu7.l1c.cpu_side
 
 [system.cpu7.l1c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -378,11 +377,13 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu7.test
-mem_side=system.toL2Bus.port[8]
+mem_side=system.toL2Bus.slave[7]
 
 [system.funcmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=false
 latency=30000
 latency_var=0
 null=false
@@ -392,7 +393,7 @@ port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system
 
 [system.l2c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
 forward_snoops=true
@@ -412,8 +413,8 @@ tgts_per_mshr=16
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[0]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[0]
 
 [system.membus]
 type=Bus
@@ -423,17 +424,20 @@ clock=2
 header_cycles=1
 use_default_range=false
 width=16
-port=system.l2c.mem_side system.system_port system.physmem.port[0]
+master=system.physmem.port[0]
+slave=system.l2c.mem_side system.system_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[2]
+port=system.membus.master[0]
 
 [system.toL2Bus]
 type=Bus
@@ -443,5 +447,6 @@ clock=2
 header_cycles=1
 use_default_range=false
 width=16
-port=system.l2c.cpu_side system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
 
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
index c89b62243..cd078a3a4 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:09:36
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:37:08
+gem5 executing on piton
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 263488655 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
index 8183eaaf7..58bdafd11 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000263                       # Nu
 sim_ticks                                   263488655                       # Number of ticks simulated
 final_tick                                  263488655                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                                1938715                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 338552                       # Number of bytes of host memory used
-host_seconds                                   135.91                       # Real time elapsed on the host
+host_tick_rate                                1217695                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 343548                       # Number of bytes of host memory used
+host_seconds                                   216.38                       # Real time elapsed on the host
 system.physmem.bytes_read                     4057580                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  2644316                       # Number of bytes written to this memory
@@ -316,7 +316,7 @@ system.l2c.blocked_cycles::no_targets               0                       # nu
 system.l2c.blocked::no_mshrs                       14                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs   6964.928571                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks               40644                       # number of writebacks
@@ -645,7 +645,7 @@ system.cpu0.l1c.blocked_cycles::no_targets            0                       #
 system.cpu0.l1c.blocked::no_mshrs               69110                       # number of cycles access was blocked
 system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
 system.cpu0.l1c.avg_blocked_cycles::no_mshrs  3673.059398                       # average number of cycles each access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
 system.cpu0.l1c.writebacks::writebacks          11972                       # number of writebacks
@@ -741,7 +741,7 @@ system.cpu1.l1c.blocked_cycles::no_targets            0                       #
 system.cpu1.l1c.blocked::no_mshrs               68822                       # number of cycles access was blocked
 system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
 system.cpu1.l1c.avg_blocked_cycles::no_mshrs  3680.878237                       # average number of cycles each access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
 system.cpu1.l1c.writebacks::writebacks          11809                       # number of writebacks
@@ -837,7 +837,7 @@ system.cpu2.l1c.blocked_cycles::no_targets            0                       #
 system.cpu2.l1c.blocked::no_mshrs               68698                       # number of cycles access was blocked
 system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
 system.cpu2.l1c.avg_blocked_cycles::no_mshrs  3701.759105                       # average number of cycles each access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
 system.cpu2.l1c.writebacks::writebacks          11784                       # number of writebacks
@@ -933,7 +933,7 @@ system.cpu3.l1c.blocked_cycles::no_targets            0                       #
 system.cpu3.l1c.blocked::no_mshrs               68939                       # number of cycles access was blocked
 system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
 system.cpu3.l1c.avg_blocked_cycles::no_mshrs  3691.127910                       # average number of cycles each access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
 system.cpu3.l1c.writebacks::writebacks          11956                       # number of writebacks
@@ -1029,7 +1029,7 @@ system.cpu4.l1c.blocked_cycles::no_targets            0                       #
 system.cpu4.l1c.blocked::no_mshrs               68868                       # number of cycles access was blocked
 system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
 system.cpu4.l1c.avg_blocked_cycles::no_mshrs  3690.197653                       # average number of cycles each access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
 system.cpu4.l1c.writebacks::writebacks          11763                       # number of writebacks
@@ -1125,7 +1125,7 @@ system.cpu5.l1c.blocked_cycles::no_targets            0                       #
 system.cpu5.l1c.blocked::no_mshrs               68969                       # number of cycles access was blocked
 system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
 system.cpu5.l1c.avg_blocked_cycles::no_mshrs  3673.840624                       # average number of cycles each access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
 system.cpu5.l1c.writebacks::writebacks          11908                       # number of writebacks
@@ -1221,7 +1221,7 @@ system.cpu6.l1c.blocked_cycles::no_targets            0                       #
 system.cpu6.l1c.blocked::no_mshrs               68612                       # number of cycles access was blocked
 system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
 system.cpu6.l1c.avg_blocked_cycles::no_mshrs  3698.984332                       # average number of cycles each access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
 system.cpu6.l1c.writebacks::writebacks          11849                       # number of writebacks
@@ -1317,7 +1317,7 @@ system.cpu7.l1c.blocked_cycles::no_targets            0                       #
 system.cpu7.l1c.blocked::no_mshrs               69036                       # number of cycles access was blocked
 system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
 system.cpu7.l1c.avg_blocked_cycles::no_mshrs  3679.369981                       # average number of cycles each access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
 system.cpu7.l1c.writebacks::writebacks          11797                       # number of writebacks
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
index 80dfb592f..f9dd021f3 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/06/2012 15:56:56
+Real time: May/08/2012 15:36:35
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.56
-Virtual_time_in_minutes: 0.00933333
-Virtual_time_in_hours:   0.000155556
-Virtual_time_in_days:    6.48148e-06
+Virtual_time_in_seconds: 0.3
+Virtual_time_in_minutes: 0.005
+Virtual_time_in_hours:   8.33333e-05
+Virtual_time_in_days:    3.47222e-06
 
 Ruby_current_time: 349711
 Ruby_start_time: 0
 Ruby_cycles: 349711
 
-mbytes_resident: 41.7227
-mbytes_total: 225.164
-resident_ratio: 0.185334
+mbytes_resident: 42.2773
+mbytes_total: 215.703
+resident_ratio: 0.195998
 
 ruby_cycles_executed: [ 349712 ]
 
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11807
+page_reclaims: 11317
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 80
 
 Network Stats
 -------------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
index 81523aa56..56e348b35 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
@@ -1,11 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr  6 2012 15:45:29
-gem5 started Apr  6 2012 15:56:56
-gem5 executing on sc2b0605
+gem5 compiled May  8 2012 15:08:30
+gem5 started May  8 2012 15:36:34
+gem5 executing on piton
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
-print getting inst port 0
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 349711 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
index d91a58c37..715dd6b55 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000350                       # Nu
 sim_ticks                                      349711                       # Number of ticks simulated
 final_tick                                     349711                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1593950                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230572                       # Number of bytes of host memory used
-host_seconds                                     0.22                       # Real time elapsed on the host
+host_tick_rate                                2733901                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220884                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 system.physmem.bytes_read                           0                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
index 71708f39f..706512ef6 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/06/2012 15:57:36
+Real time: May/08/2012 15:36:38
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 1.05
-Virtual_time_in_minutes: 0.0175
-Virtual_time_in_hours:   0.000291667
-Virtual_time_in_days:    1.21528e-05
+Virtual_time_in_seconds: 0.56
+Virtual_time_in_minutes: 0.00933333
+Virtual_time_in_hours:   0.000155556
+Virtual_time_in_days:    6.48148e-06
 
 Ruby_current_time: 357561
 Ruby_start_time: 0
 Ruby_cycles: 357561
 
-mbytes_resident: 41.7969
-mbytes_total: 225.496
-resident_ratio: 0.18539
+mbytes_resident: 42.2305
+mbytes_total: 215.871
+resident_ratio: 0.195628
 
 ruby_cycles_executed: [ 357562 ]
 
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11804
+page_reclaims: 11327
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 72
 
 Network Stats
 -------------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
index 323ca5da6..45991493b 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
@@ -1,11 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr  6 2012 15:48:19
-gem5 started Apr  6 2012 15:57:35
-gem5 executing on sc2b0605
+gem5 compiled May  8 2012 15:14:18
+gem5 started May  8 2012 15:36:38
+gem5 executing on piton
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
-print getting inst port 0
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 357561 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
index d96ddc43e..a0c426ba8 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000358                       # Nu
 sim_ticks                                      357561                       # Number of ticks simulated
 final_tick                                     357561                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 507408                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230912                       # Number of bytes of host memory used
-host_seconds                                     0.70                       # Real time elapsed on the host
+host_tick_rate                                 908445                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221056                       # Number of bytes of host memory used
+host_seconds                                     0.39                       # Real time elapsed on the host
 system.physmem.bytes_read                           0                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
index f3c0c7ea2..3806bbb4c 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/06/2012 15:58:16
+Real time: May/08/2012 15:36:42
 
 Profiler Stats
 --------------
@@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.53
-Virtual_time_in_minutes: 0.00883333
-Virtual_time_in_hours:   0.000147222
-Virtual_time_in_days:    6.13426e-06
+Virtual_time_in_seconds: 0.28
+Virtual_time_in_minutes: 0.00466667
+Virtual_time_in_hours:   7.77778e-05
+Virtual_time_in_days:    3.24074e-06
 
-Ruby_current_time: 262451
+Ruby_current_time: 259241
 Ruby_start_time: 0
-Ruby_cycles: 262451
+Ruby_cycles: 259241
 
-mbytes_resident: 41.8164
-mbytes_total: 225.266
-resident_ratio: 0.185666
+mbytes_resident: 42.25
+mbytes_total: 215.77
+resident_ratio: 0.195811
 
-ruby_cycles_executed: [ 262452 ]
+ruby_cycles_executed: [ 259242 ]
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -66,17 +66,17 @@ Directory-0:0
 
 Busy Bank Count:0
 
-sequencer_requests_outstanding: [binsize: 1 max: 16 count: 984 average: 15.8354 | standard deviation: 1.13036 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 43 927 ]
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 998 average: 15.8297 | standard deviation: 1.12508 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 51 933 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 64 max: 6619 count: 969 average: 4277.35 | standard deviation: 1934.43 | 79 13 3 7 10 1 7 11 10 4 3 6 6 2 3 2 2 1 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 4 2 0 2 10 9 3 13 13 19 16 25 19 27 24 32 34 43 37 42 39 38 33 36 32 41 32 28 15 14 18 19 13 8 18 7 4 5 3 4 1 2 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 64 max: 6616 count: 51 average: 4258.78 | standard deviation: 2119.03 | 7 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 2 1 2 3 5 3 3 1 0 2 0 2 3 1 0 2 2 1 2 2 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 64 max: 6619 count: 869 average: 4491.44 | standard deviation: 1749.39 | 71 11 1 3 2 1 2 6 2 0 2 2 1 1 2 2 1 1 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 4 2 0 2 10 9 2 13 13 19 16 24 19 25 23 30 31 38 34 39 38 38 31 36 30 38 31 28 13 12 17 17 11 8 18 7 4 5 3 4 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 8 max: 1029 count: 49 average: 499.857 | standard deviation: 220.453 | 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 1 2 1 0 0 0 2 3 0 2 0 0 0 0 0 0 0 0 0 1 2 0 0 2 0 0 1 0 0 0 0 1 1 2 2 1 0 0 2 2 1 0 0 0 1 0 0 2 0 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache: [binsize: 1 max: 116 count: 91 average: 17.9121 | standard deviation: 38.4436 | 0 28 14 19 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 1 0 0 2 4 0 1 2 ]
-miss_latency_L2Cache: [binsize: 32 max: 6221 count: 45 average: 2770.13 | standard deviation: 2320.89 | 0 1 0 0 2 1 0 3 2 1 0 0 0 1 0 2 0 3 0 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 1 0 1 0 0 0 0 2 0 0 0 1 0 2 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 2 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
-miss_latency_Directory: [binsize: 64 max: 6619 count: 833 average: 4824.09 | standard deviation: 1289.25 | 0 0 0 4 7 1 6 9 7 3 3 6 5 1 2 1 1 1 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 4 2 0 2 9 7 2 12 13 19 14 25 18 25 24 31 34 43 36 40 39 37 31 35 31 41 32 28 14 14 17 19 12 8 18 7 4 4 3 4 1 2 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 64 max: 6727 count: 983 average: 4161.1 | standard deviation: 1947.91 | 87 10 3 3 7 4 15 8 10 8 2 11 4 4 5 1 1 1 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 2 0 0 2 3 0 5 4 2 2 11 11 6 16 17 20 23 28 30 31 31 35 36 41 23 36 40 40 30 35 40 27 26 16 14 15 25 13 8 11 10 8 5 4 3 2 0 1 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 32 max: 6030 count: 42 average: 4225.5 | standard deviation: 2062.87 | 6 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 0 0 2 1 1 0 3 0 1 0 0 1 2 0 1 0 1 1 0 1 1 1 0 1 2 1 0 0 0 1 0 1 1 0 0 1 1 1 0 0 1 ]
+miss_latency_ST: [binsize: 64 max: 6727 count: 883 average: 4395.44 | standard deviation: 1763.39 | 79 9 2 1 2 4 5 5 1 0 0 4 0 1 2 1 1 1 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 2 0 0 2 3 0 4 4 2 2 11 11 6 16 17 20 22 27 29 29 31 32 35 38 22 35 38 39 28 34 38 26 23 16 13 14 24 12 6 11 9 8 5 4 3 2 0 1 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 8 max: 937 count: 58 average: 546.845 | standard deviation: 215.598 | 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 3 0 0 0 0 0 0 0 0 0 0 0 1 2 4 0 2 1 0 0 0 1 0 0 1 1 0 1 3 1 0 2 1 1 0 0 0 2 0 2 1 1 2 1 0 1 0 0 0 0 0 0 1 1 2 0 1 1 1 0 0 0 0 0 1 0 3 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache: [binsize: 1 max: 116 count: 96 average: 13.6875 | standard deviation: 33.4703 | 0 30 16 20 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 2 1 0 0 3 ]
+miss_latency_L2Cache: [binsize: 32 max: 6221 count: 46 average: 2573.46 | standard deviation: 2204.04 | 0 1 0 0 0 2 0 0 2 1 0 3 2 2 0 1 0 2 0 0 0 0 1 0 0 1 1 1 2 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 1 0 1 0 0 0 0 2 0 0 0 1 0 3 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
+miss_latency_Directory: [binsize: 64 max: 6727 count: 841 average: 4721.37 | standard deviation: 1325.63 | 0 0 1 3 4 1 11 7 8 8 2 10 3 2 3 0 1 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 2 0 0 2 2 0 5 4 2 2 10 9 5 15 17 20 21 28 29 28 31 32 36 41 23 35 40 40 28 33 40 27 26 16 14 15 25 13 7 11 10 8 5 3 3 2 0 1 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -86,14 +86,15 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
 miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-imcomplete_dir_Times: 833
-miss_latency_LD_L1Cache: [binsize: 1 max: 116 count: 9 average: 27.1111 | standard deviation: 49.5568 | 0 2 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 ]
-miss_latency_LD_Directory: [binsize: 64 max: 6616 count: 42 average: 5165.57 | standard deviation: 838.074 | 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 2 1 2 3 5 3 3 1 0 2 0 2 3 1 0 2 2 1 2 2 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_L1Cache: [binsize: 1 max: 116 count: 82 average: 16.9024 | standard deviation: 37.2711 | 0 26 12 16 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 1 0 0 2 3 0 1 1 ]
-miss_latency_ST_L2Cache: [binsize: 32 max: 6221 count: 35 average:  3440 | standard deviation: 2206.6 | 0 0 0 0 0 1 0 2 1 1 0 0 0 1 0 2 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 1 0 1 0 0 0 0 2 0 0 0 1 0 2 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 2 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
-miss_latency_ST_Directory: [binsize: 64 max: 6619 count: 752 average: 5028.29 | standard deviation: 889.008 | 0 0 0 1 0 1 1 4 1 0 2 2 1 0 2 1 0 1 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 4 2 0 2 9 7 1 12 13 19 14 24 18 23 23 29 31 38 33 37 38 37 29 35 29 38 31 28 12 12 16 17 10 8 18 7 4 4 3 4 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH_L2Cache: [binsize: 8 max: 897 count: 10 average: 425.6 | standard deviation: 295.308 | 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH_Directory: [binsize: 8 max: 1029 count: 39 average: 518.897 | standard deviation: 197.26 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 2 3 0 2 0 0 0 0 0 0 0 0 0 1 2 0 0 2 0 0 1 0 0 0 0 1 1 2 2 1 0 0 1 1 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+imcomplete_dir_Times: 841
+miss_latency_LD_L1Cache: [binsize: 1 max: 116 count: 7 average: 17.7143 | standard deviation: 43.3436 | 0 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_LD_Directory: [binsize: 32 max: 6030 count: 35 average: 5067.06 | standard deviation: 870.007 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 0 0 2 1 1 0 3 0 1 0 0 1 2 0 1 0 1 1 0 1 1 1 0 1 2 1 0 0 0 1 0 1 1 0 0 1 1 1 0 0 1 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 116 count: 88 average: 13.4886 | standard deviation: 33.0312 | 0 26 14 19 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 2 1 0 0 2 ]
+miss_latency_ST_L2Cache: [binsize: 32 max: 6221 count: 38 average: 2985.71 | standard deviation: 2210.09 | 0 0 0 0 0 2 0 0 1 1 0 3 2 2 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 1 0 1 0 0 0 0 2 0 0 0 1 0 3 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
+miss_latency_ST_Directory: [binsize: 64 max: 6727 count: 757 average: 4975.6 | standard deviation: 846.532 | 0 0 0 1 0 1 1 4 1 0 0 3 0 0 2 0 1 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 2 0 0 2 2 0 4 4 2 2 10 9 5 15 17 20 20 27 28 26 31 29 35 38 22 34 38 39 26 32 38 26 23 16 13 14 24 12 5 11 9 8 5 3 3 2 0 1 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 1 average:     3 | standard deviation: 0 | 0 0 0 1 ]
+miss_latency_IFETCH_L2Cache: [binsize: 8 max: 910 count: 8 average: 615.25 | standard deviation: 325.21 | 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_Directory: [binsize: 8 max: 937 count: 49 average: 546.776 | standard deviation: 181.198 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 3 0 0 0 0 0 0 0 0 0 0 0 1 2 4 0 2 1 0 0 0 1 0 0 1 1 0 1 3 1 0 1 0 1 0 0 0 2 0 2 1 1 2 1 0 1 0 0 0 0 0 0 1 1 2 0 1 1 1 0 0 0 0 0 1 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -125,123 +126,123 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11804
-page_faults: 3
+page_reclaims: 11326
+page_faults: 0
 swaps: 0
-block_inputs: 1456
-block_outputs: 0
+block_inputs: 0
+block_outputs: 80
 
 Network Stats
 -------------
 
-total_msg_count_Request_Control: 5154 41232
-total_msg_count_Response_Data: 2646 190512
+total_msg_count_Request_Control: 5214 41712
+total_msg_count_Response_Data: 2676 192672
 total_msg_count_ResponseL2hit_Data: 123 8856
 total_msg_count_Response_Control: 3 24
 total_msg_count_Writeback_Data: 5019 361368
-total_msg_count_Writeback_Control: 201 1608
-total_msg_count_Persistent_Control: 2034 16272
-total_msgs: 15180 total_bytes: 619872
+total_msg_count_Writeback_Control: 222 1776
+total_msg_count_Persistent_Control: 2172 17376
+total_msgs: 15429 total_bytes: 623784
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 1.78671
-  links_utilized_percent_switch_0_link_0: 1.70737 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 1.86606 bw: 16000 base_latency: 1
+links_utilized_percent_switch_0: 1.81771
+  links_utilized_percent_switch_0_link_0: 1.73468 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 1.90074 bw: 16000 base_latency: 1
 
-  outgoing_messages_switch_0_link_0_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 869 62568 [ 0 0 0 0 869 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 41 2952 [ 0 0 0 0 41 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Data: 57 4104 [ 0 0 0 0 57 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Persistent_Control: 339 2712 [ 0 0 0 339 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Request_Control: 879 7032 [ 0 879 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Data: 22 1584 [ 0 0 0 0 22 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Data: 931 67032 [ 0 0 0 0 931 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Persistent_Control: 339 2712 [ 0 0 0 339 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Data: 49 3528 [ 0 0 0 0 49 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Persistent_Control: 362 2896 [ 0 0 0 362 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Request_Control: 889 7112 [ 0 889 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Data: 933 67176 [ 0 0 0 0 933 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Persistent_Control: 362 2896 [ 0 0 0 362 0 0 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 1.64269
-  links_utilized_percent_switch_1_link_0: 1.73061 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 1.55477 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_1_link_0_Request_Control: 879 7032 [ 0 879 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Writeback_Data: 874 62928 [ 0 0 0 0 874 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Persistent_Control: 339 2712 [ 0 0 0 339 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Request_Control: 839 6712 [ 0 0 839 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 25 1800 [ 0 0 0 0 25 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_1: 1.67826
+  links_utilized_percent_switch_1_link_0: 1.77576 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 1.58077 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_1_link_0_Request_Control: 889 7112 [ 0 889 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Writeback_Data: 884 63648 [ 0 0 0 0 884 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Persistent_Control: 362 2896 [ 0 0 0 362 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Request_Control: 849 6792 [ 0 0 849 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 28 2016 [ 0 0 0 0 28 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 41 2952 [ 0 0 0 0 41 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Data: 740 53280 [ 0 0 0 0 740 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 67 536 [ 0 0 0 0 67 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Data: 739 53208 [ 0 0 0 0 739 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 74 592 [ 0 0 0 0 74 0 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 1.49114
-  links_utilized_percent_switch_2_link_0: 1.54715 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 1.43513 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_2_link_0_Request_Control: 839 6712 [ 0 0 839 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Response_Data: 22 1584 [ 0 0 0 0 22 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Data: 742 53424 [ 0 0 0 0 742 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 67 536 [ 0 0 0 0 67 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Persistent_Control: 339 2712 [ 0 0 0 339 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Data: 835 60120 [ 0 0 0 0 835 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Writeback_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_2: 1.51693
+  links_utilized_percent_switch_2_link_0: 1.57228 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 1.46157 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_2_link_0_Request_Control: 849 6792 [ 0 0 849 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Data: 740 53280 [ 0 0 0 0 740 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 74 592 [ 0 0 0 0 74 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Persistent_Control: 362 2896 [ 0 0 0 362 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Data: 841 60552 [ 0 0 0 0 841 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
 
 switch_3_inlinks: 3
 switch_3_outlinks: 3
-links_utilized_percent_switch_3: 1.64018
-  links_utilized_percent_switch_3_link_0: 1.64278 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_3_link_1: 1.73061 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_3_link_2: 1.54715 bw: 16000 base_latency: 1
+links_utilized_percent_switch_3: 1.67097
+  links_utilized_percent_switch_3_link_0: 1.66486 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 1.77576 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_3_link_2: 1.57228 bw: 16000 base_latency: 1
 
-  outgoing_messages_switch_3_link_0_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Data: 869 62568 [ 0 0 0 0 869 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 41 2952 [ 0 0 0 0 41 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Writeback_Data: 57 4104 [ 0 0 0 0 57 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Request_Control: 879 7032 [ 0 879 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Writeback_Data: 874 62928 [ 0 0 0 0 874 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Persistent_Control: 339 2712 [ 0 0 0 339 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_2_Request_Control: 839 6712 [ 0 0 839 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_2_Response_Data: 22 1584 [ 0 0 0 0 22 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_2_Writeback_Data: 742 53424 [ 0 0 0 0 742 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_2_Writeback_Control: 67 536 [ 0 0 0 0 67 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_2_Persistent_Control: 339 2712 [ 0 0 0 339 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Writeback_Data: 49 3528 [ 0 0 0 0 49 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Request_Control: 889 7112 [ 0 889 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Writeback_Data: 884 63648 [ 0 0 0 0 884 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Persistent_Control: 362 2896 [ 0 0 0 362 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_2_Request_Control: 849 6792 [ 0 0 849 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_2_Response_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_2_Writeback_Data: 740 53280 [ 0 0 0 0 740 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_2_Writeback_Control: 74 592 [ 0 0 0 0 74 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_2_Persistent_Control: 362 2896 [ 0 0 0 362 0 0 0 0 0 0 ] base_latency: 1
 
 Cache Stats: system.l1_cntrl0.L1IcacheMemory
-  system.l1_cntrl0.L1IcacheMemory_total_misses: 49
-  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 49
+  system.l1_cntrl0.L1IcacheMemory_total_misses: 57
+  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 57
   system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
   system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
 
   system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH:   100%
 
-  system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor:   49    100%
+  system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor:   57    100%
 
 Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 830
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 830
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 832
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 832
   system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   5.06024%
-  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   94.9398%
+  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   4.20673%
+  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   95.7933%
 
-  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   830    100%
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   832    100%
 
  --- L1Cache ---
  - Event Counts -
-Load [51 ] 51
-Ifetch [49 ] 49
-Store [870 ] 870
+Load [42 ] 42
+Ifetch [58 ] 58
+Store [885 ] 885
 Atomic [0 ] 0
-L1_Replacement [19023 ] 19023
-Data_Shared [7 ] 7
+L1_Replacement [19139 ] 19139
+Data_Shared [4 ] 4
 Data_Owner [1 ] 1
-Data_All_Tokens [949 ] 949
+Data_All_Tokens [954 ] 954
 Ack [0 ] 0
 Ack_All_Tokens [1 ] 1
 Transient_GETX [0 ] 0
@@ -253,21 +254,21 @@ Transient_Local_GETS_Last_Token [0 ] 0
 Persistent_GETX [0 ] 0
 Persistent_GETS [0 ] 0
 Persistent_GETS_Last_Token [0 ] 0
-Own_Lock_or_Unlock [339 ] 339
-Request_Timeout [548 ] 548
+Own_Lock_or_Unlock [362 ] 362
+Request_Timeout [556 ] 556
 Use_TimeoutStarverX [0 ] 0
 Use_TimeoutStarverS [0 ] 0
-Use_TimeoutNoStarvers [870 ] 870
+Use_TimeoutNoStarvers [882 ] 882
 Use_TimeoutNoStarvers_NoMig [0 ] 0
 
  - Transitions -
-NP  Load [42 ] 42
-NP  Ifetch [49 ] 49
-NP  Store [788 ] 788
+NP  Load [35 ] 35
+NP  Ifetch [57 ] 57
+NP  Store [797 ] 797
 NP  Atomic [0 ] 0
 NP  Data_Shared [0 ] 0
 NP  Data_Owner [0 ] 0
-NP  Data_All_Tokens [79 ] 79
+NP  Data_All_Tokens [72 ] 72
 NP  Ack [0 ] 0
 NP  Transient_GETX [0 ] 0
 NP  Transient_Local_GETX [0 ] 0
@@ -276,7 +277,7 @@ NP  Transient_Local_GETS [0 ] 0
 NP  Persistent_GETX [0 ] 0
 NP  Persistent_GETS [0 ] 0
 NP  Persistent_GETS_Last_Token [0 ] 0
-NP  Own_Lock_or_Unlock [167 ] 167
+NP  Own_Lock_or_Unlock [178 ] 178
 
 I  Load [0 ] 0
 I  Ifetch [0 ] 0
@@ -302,7 +303,7 @@ S  Load [0 ] 0
 S  Ifetch [0 ] 0
 S  Store [0 ] 0
 S  Atomic [0 ] 0
-S  L1_Replacement [7 ] 7
+S  L1_Replacement [4 ] 4
 S  Data_Shared [0 ] 0
 S  Data_Owner [0 ] 0
 S  Data_All_Tokens [0 ] 0
@@ -339,73 +340,73 @@ O  Persistent_GETS_Last_Token [0 ] 0
 O  Own_Lock_or_Unlock [0 ] 0
 
 M  Load [0 ] 0
-M  Ifetch [0 ] 0
+M  Ifetch [1 ] 1
 M  Store [0 ] 0
 M  Atomic [0 ] 0
-M  L1_Replacement [81 ] 81
+M  L1_Replacement [86 ] 86
 M  Transient_GETX [0 ] 0
 M  Transient_Local_GETX [0 ] 0
 M  Transient_GETS [0 ] 0
 M  Transient_Local_GETS [0 ] 0
 M  Persistent_GETX [0 ] 0
 M  Persistent_GETS [0 ] 0
-M  Own_Lock_or_Unlock [9 ] 9
+M  Own_Lock_or_Unlock [14 ] 14
 
-MM  Load [8 ] 8
+MM  Load [7 ] 7
 MM  Ifetch [0 ] 0
-MM  Store [71 ] 71
+MM  Store [76 ] 76
 MM  Atomic [0 ] 0
-MM  L1_Replacement [786 ] 786
+MM  L1_Replacement [794 ] 794
 MM  Transient_GETX [0 ] 0
 MM  Transient_Local_GETX [0 ] 0
 MM  Transient_GETS [0 ] 0
 MM  Transient_Local_GETS [0 ] 0
 MM  Persistent_GETX [0 ] 0
 MM  Persistent_GETS [0 ] 0
-MM  Own_Lock_or_Unlock [13 ] 13
+MM  Own_Lock_or_Unlock [14 ] 14
 
 M_W  Load [0 ] 0
 M_W  Ifetch [0 ] 0
 M_W  Store [0 ] 0
 M_W  Atomic [0 ] 0
-M_W  L1_Replacement [382 ] 382
+M_W  L1_Replacement [262 ] 262
 M_W  Transient_GETX [0 ] 0
 M_W  Transient_Local_GETX [0 ] 0
 M_W  Transient_GETS [0 ] 0
 M_W  Transient_Local_GETS [0 ] 0
 M_W  Persistent_GETX [0 ] 0
 M_W  Persistent_GETS [0 ] 0
-M_W  Own_Lock_or_Unlock [1 ] 1
+M_W  Own_Lock_or_Unlock [3 ] 3
 M_W  Use_TimeoutStarverX [0 ] 0
 M_W  Use_TimeoutStarverS [0 ] 0
-M_W  Use_TimeoutNoStarvers [83 ] 83
+M_W  Use_TimeoutNoStarvers [87 ] 87
 M_W  Use_TimeoutNoStarvers_NoMig [0 ] 0
 
-MM_W  Load [1 ] 1
+MM_W  Load [0 ] 0
 MM_W  Ifetch [0 ] 0
-MM_W  Store [11 ] 11
+MM_W  Store [12 ] 12
 MM_W  Atomic [0 ] 0
-MM_W  L1_Replacement [7361 ] 7361
+MM_W  L1_Replacement [7507 ] 7507
 MM_W  Transient_GETX [0 ] 0
 MM_W  Transient_Local_GETX [0 ] 0
 MM_W  Transient_GETS [0 ] 0
 MM_W  Transient_Local_GETS [0 ] 0
 MM_W  Persistent_GETX [0 ] 0
 MM_W  Persistent_GETS [0 ] 0
-MM_W  Own_Lock_or_Unlock [17 ] 17
+MM_W  Own_Lock_or_Unlock [18 ] 18
 MM_W  Use_TimeoutStarverX [0 ] 0
 MM_W  Use_TimeoutStarverS [0 ] 0
-MM_W  Use_TimeoutNoStarvers [787 ] 787
+MM_W  Use_TimeoutNoStarvers [795 ] 795
 MM_W  Use_TimeoutNoStarvers_NoMig [0 ] 0
 
 IM  Load [0 ] 0
 IM  Ifetch [0 ] 0
 IM  Store [0 ] 0
 IM  Atomic [0 ] 0
-IM  L1_Replacement [9875 ] 9875
+IM  L1_Replacement [10013 ] 10013
 IM  Data_Shared [0 ] 0
 IM  Data_Owner [1 ] 1
-IM  Data_All_Tokens [786 ] 786
+IM  Data_All_Tokens [794 ] 794
 IM  Ack [0 ] 0
 IM  Transient_GETX [0 ] 0
 IM  Transient_Local_GETX [0 ] 0
@@ -416,8 +417,8 @@ IM  Transient_Local_GETS_Last_Token [0 ] 0
 IM  Persistent_GETX [0 ] 0
 IM  Persistent_GETS [0 ] 0
 IM  Persistent_GETS_Last_Token [0 ] 0
-IM  Own_Lock_or_Unlock [118 ] 118
-IM  Request_Timeout [494 ] 494
+IM  Own_Lock_or_Unlock [120 ] 120
+IM  Request_Timeout [493 ] 493
 
 SM  Load [0 ] 0
 SM  Ifetch [0 ] 0
@@ -465,10 +466,10 @@ IS  Load [0 ] 0
 IS  Ifetch [0 ] 0
 IS  Store [0 ] 0
 IS  Atomic [0 ] 0
-IS  L1_Replacement [531 ] 531
-IS  Data_Shared [7 ] 7
+IS  L1_Replacement [473 ] 473
+IS  Data_Shared [4 ] 4
 IS  Data_Owner [0 ] 0
-IS  Data_All_Tokens [84 ] 84
+IS  Data_All_Tokens [88 ] 88
 IS  Ack [0 ] 0
 IS  Transient_GETX [0 ] 0
 IS  Transient_Local_GETX [0 ] 0
@@ -479,8 +480,8 @@ IS  Transient_Local_GETS_Last_Token [0 ] 0
 IS  Persistent_GETX [0 ] 0
 IS  Persistent_GETS [0 ] 0
 IS  Persistent_GETS_Last_Token [0 ] 0
-IS  Own_Lock_or_Unlock [13 ] 13
-IS  Request_Timeout [53 ] 53
+IS  Own_Lock_or_Unlock [14 ] 14
+IS  Request_Timeout [62 ] 62
 
 I_L  Load [0 ] 0
 I_L  Ifetch [0 ] 0
@@ -584,50 +585,50 @@ IS_L  Own_Lock_or_Unlock [0 ] 0
 IS_L  Request_Timeout [0 ] 0
 
 Cache Stats: system.l2_cntrl0.L2cacheMemory
-  system.l2_cntrl0.L2cacheMemory_total_misses: 839
-  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 839
+  system.l2_cntrl0.L2cacheMemory_total_misses: 849
+  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 849
   system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l2_cntrl0.L2cacheMemory_request_type_GETS:   10.0119%
-  system.l2_cntrl0.L2cacheMemory_request_type_GETX:   89.9881%
+  system.l2_cntrl0.L2cacheMemory_request_type_GETS:   10.3651%
+  system.l2_cntrl0.L2cacheMemory_request_type_GETX:   89.6349%
 
-  system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   839    100%
+  system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   849    100%
 
  --- L2Cache ---
  - Event Counts -
-L1_GETS [91 ] 91
+L1_GETS [92 ] 92
 L1_GETS_Last_Token [0 ] 0
-L1_GETX [788 ] 788
+L1_GETX [797 ] 797
 L1_INV [0 ] 0
 Transient_GETX [0 ] 0
 Transient_GETS [0 ] 0
 Transient_GETS_Last_Token [0 ] 0
-L2_Replacement [779 ] 779
+L2_Replacement [793 ] 793
 Writeback_Tokens [0 ] 0
-Writeback_Shared_Data [3 ] 3
-Writeback_All_Tokens [871 ] 871
+Writeback_Shared_Data [2 ] 2
+Writeback_All_Tokens [882 ] 882
 Writeback_Owned [0 ] 0
 Data_Shared [0 ] 0
 Data_Owner [0 ] 0
 Data_All_Tokens [0 ] 0
 Ack [0 ] 0
 Ack_All_Tokens [0 ] 0
-Persistent_GETX [154 ] 154
-Persistent_GETS [16 ] 16
+Persistent_GETX [163 ] 163
+Persistent_GETS [18 ] 18
 Persistent_GETS_Last_Token [0 ] 0
-Own_Lock_or_Unlock [169 ] 169
+Own_Lock_or_Unlock [181 ] 181
 
  - Transitions -
-NP  L1_GETS [81 ] 81
-NP  L1_GETX [754 ] 754
+NP  L1_GETS [84 ] 84
+NP  L1_GETX [760 ] 760
 NP  L1_INV [0 ] 0
 NP  Transient_GETX [0 ] 0
 NP  Transient_GETS [0 ] 0
 NP  Writeback_Tokens [0 ] 0
-NP  Writeback_Shared_Data [2 ] 2
-NP  Writeback_All_Tokens [781 ] 781
+NP  Writeback_Shared_Data [1 ] 1
+NP  Writeback_All_Tokens [796 ] 796
 NP  Writeback_Owned [0 ] 0
 NP  Data_Shared [0 ] 0
 NP  Data_Owner [0 ] 0
@@ -636,19 +637,19 @@ NP  Ack [0 ] 0
 NP  Persistent_GETX [0 ] 0
 NP  Persistent_GETS [0 ] 0
 NP  Persistent_GETS_Last_Token [0 ] 0
-NP  Own_Lock_or_Unlock [145 ] 145
+NP  Own_Lock_or_Unlock [152 ] 152
 
-I  L1_GETS [3 ] 3
+I  L1_GETS [4 ] 4
 I  L1_GETS_Last_Token [0 ] 0
 I  L1_GETX [0 ] 0
 I  L1_INV [0 ] 0
 I  Transient_GETX [0 ] 0
 I  Transient_GETS [0 ] 0
 I  Transient_GETS_Last_Token [0 ] 0
-I  L2_Replacement [25 ] 25
+I  L2_Replacement [28 ] 28
 I  Writeback_Tokens [0 ] 0
 I  Writeback_Shared_Data [1 ] 1
-I  Writeback_All_Tokens [31 ] 31
+I  Writeback_All_Tokens [36 ] 36
 I  Writeback_Owned [0 ] 0
 I  Data_Shared [0 ] 0
 I  Data_Owner [0 ] 0
@@ -666,7 +667,7 @@ S  L1_INV [0 ] 0
 S  Transient_GETX [0 ] 0
 S  Transient_GETS [0 ] 0
 S  Transient_GETS_Last_Token [0 ] 0
-S  L2_Replacement [2 ] 2
+S  L2_Replacement [1 ] 1
 S  Writeback_Tokens [0 ] 0
 S  Writeback_Shared_Data [0 ] 0
 S  Writeback_All_Tokens [0 ] 0
@@ -687,10 +688,10 @@ O  L1_INV [0 ] 0
 O  Transient_GETX [0 ] 0
 O  Transient_GETS [0 ] 0
 O  Transient_GETS_Last_Token [0 ] 0
-O  L2_Replacement [2 ] 2
+O  L2_Replacement [1 ] 1
 O  Writeback_Tokens [0 ] 0
 O  Writeback_Shared_Data [0 ] 0
-O  Writeback_All_Tokens [4 ] 4
+O  Writeback_All_Tokens [2 ] 2
 O  Data_Shared [0 ] 0
 O  Data_All_Tokens [0 ] 0
 O  Ack [0 ] 0
@@ -700,13 +701,13 @@ O  Persistent_GETS [0 ] 0
 O  Persistent_GETS_Last_Token [0 ] 0
 O  Own_Lock_or_Unlock [0 ] 0
 
-M  L1_GETS [7 ] 7
-M  L1_GETX [33 ] 33
+M  L1_GETS [4 ] 4
+M  L1_GETX [36 ] 36
 M  L1_INV [0 ] 0
 M  Transient_GETX [0 ] 0
 M  Transient_GETS [0 ] 0
-M  L2_Replacement [748 ] 748
-M  Persistent_GETX [21 ] 21
+M  L2_Replacement [763 ] 763
+M  Persistent_GETX [24 ] 24
 M  Persistent_GETS [4 ] 4
 M  Own_Lock_or_Unlock [0 ] 0
 
@@ -716,18 +717,18 @@ I_L  L1_INV [0 ] 0
 I_L  Transient_GETX [0 ] 0
 I_L  Transient_GETS [0 ] 0
 I_L  Transient_GETS_Last_Token [0 ] 0
-I_L  L2_Replacement [2 ] 2
+I_L  L2_Replacement [0 ] 0
 I_L  Writeback_Tokens [0 ] 0
 I_L  Writeback_Shared_Data [0 ] 0
-I_L  Writeback_All_Tokens [55 ] 55
+I_L  Writeback_All_Tokens [48 ] 48
 I_L  Writeback_Owned [0 ] 0
 I_L  Data_Shared [0 ] 0
 I_L  Data_Owner [0 ] 0
 I_L  Data_All_Tokens [0 ] 0
 I_L  Ack [0 ] 0
-I_L  Persistent_GETX [132 ] 132
-I_L  Persistent_GETS [12 ] 12
-I_L  Own_Lock_or_Unlock [24 ] 24
+I_L  Persistent_GETX [138 ] 138
+I_L  Persistent_GETS [14 ] 14
+I_L  Own_Lock_or_Unlock [29 ] 29
 
 S_L  L1_GETS [0 ] 0
 S_L  L1_GETS_Last_Token [0 ] 0
@@ -751,71 +752,71 @@ S_L  Persistent_GETS_Last_Token [0 ] 0
 S_L  Own_Lock_or_Unlock [0 ] 0
 
 Memory controller: system.dir_cntrl0.memBuffer:
-  memory_total_requests: 1596
-  memory_reads: 835
-  memory_writes: 761
-  memory_refreshes: 547
-  memory_total_request_delays: 1074
-  memory_delays_per_request: 0.672932
-  memory_delays_in_input_queue: 139
-  memory_delays_behind_head_of_bank_queue: 6
-  memory_delays_stalled_at_head_of_bank_queue: 929
-  memory_stalls_for_bank_busy: 268
+  memory_total_requests: 1605
+  memory_reads: 843
+  memory_writes: 762
+  memory_refreshes: 541
+  memory_total_request_delays: 1171
+  memory_delays_per_request: 0.729595
+  memory_delays_in_input_queue: 153
+  memory_delays_behind_head_of_bank_queue: 2
+  memory_delays_stalled_at_head_of_bank_queue: 1016
+  memory_stalls_for_bank_busy: 265
   memory_stalls_for_random_busy: 0
   memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 74
-  memory_stalls_for_bus: 361
+  memory_stalls_for_arbitration: 87
+  memory_stalls_for_bus: 390
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 153
-  memory_stalls_for_read_read_turnaround: 73
-  accesses_per_bank: 46  42  72  75  73  65  78  39  46  46  48  32  36  37  38  55  48  51  51  51  51  45  60  38  39  64  62  41  48  31  39  49  
+  memory_stalls_for_read_write_turnaround: 196
+  memory_stalls_for_read_read_turnaround: 78
+  accesses_per_bank: 36  45  70  85  76  62  82  41  44  46  52  30  33  46  34  56  43  52  47  46  58  35  52  38  37  64  59  60  46  39  40  51  
 
  --- Directory ---
  - Event Counts -
-GETX [789 ] 789
-GETS [84 ] 84
-Lockdown [170 ] 170
-Unlockdown [169 ] 169
+GETX [795 ] 795
+GETS [105 ] 105
+Lockdown [181 ] 181
+Unlockdown [181 ] 181
 Own_Lock_or_Unlock [0 ] 0
 Own_Lock_or_Unlock_Tokens [0 ] 0
-Data_Owner [2 ] 2
+Data_Owner [1 ] 1
 Data_All_Tokens [762 ] 762
 Ack_Owner [0 ] 0
-Ack_Owner_All_Tokens [65 ] 65
+Ack_Owner_All_Tokens [72 ] 72
 Tokens [0 ] 0
-Ack_All_Tokens [2 ] 2
+Ack_All_Tokens [1 ] 1
 Request_Timeout [0 ] 0
-Memory_Data [835 ] 835
-Memory_Ack [760 ] 760
+Memory_Data [841 ] 841
+Memory_Ack [762 ] 762
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
 DMA_WRITE_All_Tokens [0 ] 0
 
  - Transitions -
-O  GETX [748 ] 748
-O  GETS [81 ] 81
-O  Lockdown [5 ] 5
+O  GETX [755 ] 755
+O  GETS [84 ] 84
+O  Lockdown [4 ] 4
 O  Unlockdown [0 ] 0
 O  Own_Lock_or_Unlock [0 ] 0
 O  Own_Lock_or_Unlock_Tokens [0 ] 0
 O  Data_Owner [0 ] 0
 O  Data_All_Tokens [0 ] 0
 O  Tokens [0 ] 0
-O  Ack_All_Tokens [2 ] 2
+O  Ack_All_Tokens [1 ] 1
 O  DMA_READ [0 ] 0
 O  DMA_WRITE [0 ] 0
 O  DMA_WRITE_All_Tokens [0 ] 0
 
-NO  GETX [3 ] 3
-NO  GETS [3 ] 3
-NO  Lockdown [149 ] 149
+NO  GETX [2 ] 2
+NO  GETS [4 ] 4
+NO  Lockdown [162 ] 162
 NO  Unlockdown [0 ] 0
 NO  Own_Lock_or_Unlock [0 ] 0
 NO  Own_Lock_or_Unlock_Tokens [0 ] 0
-NO  Data_Owner [2 ] 2
-NO  Data_All_Tokens [759 ] 759
+NO  Data_Owner [1 ] 1
+NO  Data_All_Tokens [761 ] 761
 NO  Ack_Owner [0 ] 0
-NO  Ack_Owner_All_Tokens [65 ] 65
+NO  Ack_Owner_All_Tokens [72 ] 72
 NO  Tokens [0 ] 0
 NO  DMA_READ [0 ] 0
 NO  DMA_WRITE [0 ] 0
@@ -823,11 +824,11 @@ NO  DMA_WRITE [0 ] 0
 L  GETX [4 ] 4
 L  GETS [0 ] 0
 L  Lockdown [0 ] 0
-L  Unlockdown [168 ] 168
+L  Unlockdown [181 ] 181
 L  Own_Lock_or_Unlock [0 ] 0
 L  Own_Lock_or_Unlock_Tokens [0 ] 0
 L  Data_Owner [0 ] 0
-L  Data_All_Tokens [3 ] 3
+L  Data_All_Tokens [1 ] 1
 L  Ack_Owner [0 ] 0
 L  Ack_Owner_All_Tokens [0 ] 0
 L  Tokens [0 ] 0
@@ -836,8 +837,8 @@ L  DMA_WRITE [0 ] 0
 L  DMA_WRITE_All_Tokens [0 ] 0
 
 O_W  GETX [0 ] 0
-O_W  GETS [0 ] 0
-O_W  Lockdown [1 ] 1
+O_W  GETS [17 ] 17
+O_W  Lockdown [0 ] 0
 O_W  Unlockdown [0 ] 0
 O_W  Own_Lock_or_Unlock [0 ] 0
 O_W  Own_Lock_or_Unlock_Tokens [0 ] 0
@@ -846,8 +847,8 @@ O_W  Data_All_Tokens [0 ] 0
 O_W  Ack_Owner [0 ] 0
 O_W  Tokens [0 ] 0
 O_W  Ack_All_Tokens [0 ] 0
-O_W  Memory_Data [1 ] 1
-O_W  Memory_Ack [759 ] 759
+O_W  Memory_Data [0 ] 0
+O_W  Memory_Ack [762 ] 762
 O_W  DMA_READ [0 ] 0
 O_W  DMA_WRITE [0 ] 0
 O_W  DMA_WRITE_All_Tokens [0 ] 0
@@ -855,7 +856,7 @@ O_W  DMA_WRITE_All_Tokens [0 ] 0
 L_O_W  GETX [34 ] 34
 L_O_W  GETS [0 ] 0
 L_O_W  Lockdown [0 ] 0
-L_O_W  Unlockdown [1 ] 1
+L_O_W  Unlockdown [0 ] 0
 L_O_W  Own_Lock_or_Unlock [0 ] 0
 L_O_W  Own_Lock_or_Unlock_Tokens [0 ] 0
 L_O_W  Data_Owner [0 ] 0
@@ -863,8 +864,8 @@ L_O_W  Data_All_Tokens [0 ] 0
 L_O_W  Ack_Owner [0 ] 0
 L_O_W  Tokens [0 ] 0
 L_O_W  Ack_All_Tokens [0 ] 0
-L_O_W  Memory_Data [5 ] 5
-L_O_W  Memory_Ack [1 ] 1
+L_O_W  Memory_Data [4 ] 4
+L_O_W  Memory_Ack [0 ] 0
 L_O_W  DMA_READ [0 ] 0
 L_O_W  DMA_WRITE [0 ] 0
 L_O_W  DMA_WRITE_All_Tokens [0 ] 0
@@ -930,7 +931,7 @@ NO_W  Data_All_Tokens [0 ] 0
 NO_W  Ack_Owner [0 ] 0
 NO_W  Tokens [0 ] 0
 NO_W  Ack_All_Tokens [0 ] 0
-NO_W  Memory_Data [814 ] 814
+NO_W  Memory_Data [822 ] 822
 NO_W  DMA_READ [0 ] 0
 NO_W  DMA_WRITE [0 ] 0
 NO_W  DMA_WRITE_All_Tokens [0 ] 0
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
index 6fdfc5df5..2d7dcae80 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
@@ -1,11 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr  6 2012 14:55:37
-gem5 started Apr  6 2012 15:58:16
-gem5 executing on sc2b0605
+gem5 compiled May  8 2012 15:11:25
+gem5 started May  8 2012 15:36:42
+gem5 executing on piton
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
-print getting inst port 0
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 262451 because Ruby Tester completed
+Exiting @ tick 259241 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
index 4d6cc8d4c..29c84ee49 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000259                       # Nu
 sim_ticks                                      259241                       # Number of ticks simulated
 final_tick                                     259241                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1346552                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230676                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_tick_rate                                2436767                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220952                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 system.physmem.bytes_read                           0                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
index 373d15ce7..5a24f618a 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/06/2012 15:58:55
+Real time: May/08/2012 15:36:31
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.47
-Virtual_time_in_minutes: 0.00783333
-Virtual_time_in_hours:   0.000130556
-Virtual_time_in_days:    5.43981e-06
+Virtual_time_in_seconds: 0.26
+Virtual_time_in_minutes: 0.00433333
+Virtual_time_in_hours:   7.22222e-05
+Virtual_time_in_days:    3.00926e-06
 
 Ruby_current_time: 205611
 Ruby_start_time: 0
 Ruby_cycles: 205611
 
-mbytes_resident: 41.4375
-mbytes_total: 225.051
-resident_ratio: 0.18416
+mbytes_resident: 42.1211
+mbytes_total: 215.602
+resident_ratio: 0.195365
 
 ruby_cycles_executed: [ 205612 ]
 
@@ -127,11 +127,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11717
-page_faults: 4
+page_reclaims: 11276
+page_faults: 0
 swaps: 0
-block_inputs: 1448
-block_outputs: 0
+block_inputs: 16
+block_outputs: 80
 
 Network Stats
 -------------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
index f718b0a21..1f028aa91 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
@@ -1,11 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr  6 2012 14:43:55
-gem5 started Apr  6 2012 15:58:55
-gem5 executing on sc2b0605
+gem5 compiled May  8 2012 15:12:50
+gem5 started May  8 2012 15:36:31
+gem5 executing on piton
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
-print getting inst port 0
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 205611 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
index fa4f833bd..35d1a046f 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000206                       # Nu
 sim_ticks                                      205611                       # Number of ticks simulated
 final_tick                                     205611                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1440620                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230456                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
+host_tick_rate                                2474305                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220780                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 system.physmem.bytes_read                           0                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
index 4e312b4ac..3b6b0e305 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/06/2012 15:39:16
+Real time: May/08/2012 15:36:56
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.43
-Virtual_time_in_minutes: 0.00716667
-Virtual_time_in_hours:   0.000119444
-Virtual_time_in_days:    4.97685e-06
+Virtual_time_in_seconds: 0.29
+Virtual_time_in_minutes: 0.00483333
+Virtual_time_in_hours:   8.05556e-05
+Virtual_time_in_days:    3.35648e-06
 
 Ruby_current_time: 280571
 Ruby_start_time: 0
 Ruby_cycles: 280571
 
-mbytes_resident: 41.168
-mbytes_total: 224.66
-resident_ratio: 0.18328
+mbytes_resident: 41.6914
+mbytes_total: 214.977
+resident_ratio: 0.193935
 
 ruby_cycles_executed: [ 280572 ]
 
@@ -121,11 +121,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11677
-page_faults: 1
+page_reclaims: 11172
+page_faults: 0
 swaps: 0
-block_inputs: 624
-block_outputs: 0
+block_inputs: 0
+block_outputs: 72
 
 Network Stats
 -------------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
index 2a84a1173..4e724cd5b 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
@@ -1,11 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr  6 2012 14:39:05
-gem5 started Apr  6 2012 15:39:15
-gem5 executing on sc2b0605
+gem5 compiled May  8 2012 15:36:31
+gem5 started May  8 2012 15:36:56
+gem5 executing on piton
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby
 Global frequency set at 1000000000 ticks per second
-print getting inst port 0
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 280571 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
index 4e6b3fd3d..c5e74a2ba 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000281                       # Nu
 sim_ticks                                      280571                       # Number of ticks simulated
 final_tick                                     280571                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                2823981                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230056                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_tick_rate                                2565590                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220140                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 system.physmem.bytes_read                           0                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-- 
2.30.2