From 4a745e62b4889e09a7243a34e03769c2b4e575a2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 17 Mar 2021 13:00:28 +0000 Subject: [PATCH] link up SVP64 RM Mode decoding into PowerDecoder2 --- src/soc/decoder/power_decoder2.py | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 71617bfd..ffb677c1 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -992,7 +992,7 @@ class PowerDecode2(PowerDecodeSubset): self.crout_svdec = crout_svdec # and SVP64 RM mode decoder - m.submodules.sv_rm_dec = self.rm_dec + m.submodules.sv_rm_dec = rm_dec = self.rm_dec # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec reg = Signal(5, reset_less=True) @@ -1170,6 +1170,14 @@ class PowerDecode2(PowerDecodeSubset): comb += e.write_fast1.eq(dec_o.fast_out) comb += e.write_fast2.eq(dec_o2.fast_out) + if self.svp64_en: + # connect up SVP64 RM Mode decoding + fn = self.op_get("function_unit") + comb += rm_dec.fn_in.eq(fn) # decode needs to know if LD/ST type + comb += rm_dec.ptype_in.eq(op.SV_Ptype) # Single/Twin predicated + comb += rm_dec.rc_in.eq(rc_out) # Rc=1 + comb += rm_dec.rm_in.eq(self.sv_rm) # SVP64 RM mode + # sigh this is exactly the sort of thing for which the # decoder is designed to not need. MTSPR, MFSPR and others need # access to the XER bits. however setting e.oe is not appropriate -- 2.30.2