From 4a76b425cc0588ef5a8e46c06eecbfab869a35d9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 May 2019 08:44:59 -0700 Subject: [PATCH] Misspell --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 1b45085be..328f0e3c3 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -567,7 +567,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // Attempt another wideports_split here because there // exists the possibility that different bits of a port - // could be an input and output, therefore parse_xiager() + // could be an input and output, therefore parse_xaiger() // could not combine it into a wideport auto r = wideports_split(w->name.str()); wire = module->wire(r.first); -- 2.30.2