From 4ab0834c969ff24a69228ec18915c976d32d765e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 6 Jun 2020 19:59:30 +0100 Subject: [PATCH] expand regwid to 64 in l0_cache test --- src/soc/experiment/l0_cache.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index 09d0e5f1..1a941a47 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -36,6 +36,7 @@ from nmigen.lib.coding import PriorityEncoder # for testing purposes from soc.experiment.testmem import TestMemory + class PortInterface(RecordObject): """PortInterface @@ -568,7 +569,7 @@ def data_merger_merge(dut): def test_l0_cache(): - dut = TstL0CacheBuffer() + dut = TstL0CacheBuffer(regwid=64) #vl = rtlil.convert(dut, ports=dut.ports()) #with open("test_basic_l0_cache.il", "w") as f: # f.write(vl) -- 2.30.2