From 4aec50a863b72b461352b84b15bdb9978c229db9 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 25 Jun 2020 09:18:53 +0200
Subject: [PATCH] optimization, all items should have same attributes

---
 frontends/verific/verific.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 89d734c40..6637c214d 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1112,6 +1112,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 			MapIter mibus;
 			FOREACH_NET_OF_NETBUS(netbus, mibus, net) {
 				import_attributes(wire->attributes, net, nl);
+				break;
 			}
 
 			RTLIL::Const initval = Const(State::Sx, GetSize(wire));
-- 
2.30.2