From 4b0b7b213b0211ff869605d5d750ed487f30584c Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 11 Jul 2021 01:36:18 +0100 Subject: [PATCH] --- openpower/sv/propagation.mdwn | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/openpower/sv/propagation.mdwn b/openpower/sv/propagation.mdwn index c95a6874f..1d6e8242a 100644 --- a/openpower/sv/propagation.mdwn +++ b/openpower/sv/propagation.mdwn @@ -208,24 +208,14 @@ vec2/3/4, that would be handled by swizzle reordering): Again it is the 24 bit `RM` that is interpreted differently: -| 0...4 | 5.7 | 8 | 10 | 12 | 14 | 16 | 18..23 | -| ----- | --- | -- | -- | -- | -- | -- | ------ | -| en0-4 | rsv |mi0 |mi1 |mi2 |mo0 |mo1 | rsv | - -The shape indices 0-3 are numbered 0-3 whilst the masks are bitmasks -that indicate src or dest to which the associated shape (0-3) is to -be applied. A zero mask indicates that the Shape is not to be applied. -Note that whilst the masks are unary encoded the Shape indices sh0-3 -are not: this must be taken into consideration when ORing occurs. - -The mask is encoded as follows: - -* bit 0 indicates that the first svp64 EXTRA field is reshaped -* bit 1 indicates that the second svp64 EXTRA field is reshaped -* bit 2 indicates that the third sv64 EXTRA field is reshaped -* bit 3 indicates that the fourth svp64 EXTRA field reshaped - -This allows even instructions that have 2 destination registers to be reshaped. +| 0 | 2 | 4 | 6 | 8 | 10.14 | 15..23 | +| -- | -- | -- | -- | -- | ----- | ------ | +|mi0 |mi1 |mi2 |mo0 |mo1 | en0-4 | rsv | + +si0-2 and so0-1 each select SVSHAPE0-3 to apply to a given register. +si0-2 apply to RA, RB, RC respectively, as input registers, and +likewise so0-1 apply to output registers. en0-4 indicate whether the +SVSHAPE is actively applied or not. # setvl -- 2.30.2