From 4b238fb9c21d072eb03d10fa51693cd2060876fe Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 19 Jul 2020 20:39:35 +0100 Subject: [PATCH] update to expose signals at top-level of issuer --- src/soc/simple/issuer.py | 13 +++++++++++-- src/soc/simple/test/test_issuer.py | 10 +++++----- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 5e88deaf..9b4f8b0e 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -47,8 +47,11 @@ class TestIssuer(Elaboratable): # instruction go/monitor self.go_insn_i = Signal(reset_less=True) self.pc_o = Signal(64, reset_less=True) - self.pc_i = Data(64, "pc") # set "ok" to indicate "please change me" - self.busy_o = core.busy_o + self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me" + self.core_start_i = Signal() + self.core_bigendian_i = Signal() + self.busy_o = Signal(reset_less=True) + self.halted_o = Signal(reset_less=True) self.memerr_o = Signal(reset_less=True) # FAST regfile read /write ports for PC and MSR @@ -67,6 +70,12 @@ class TestIssuer(Elaboratable): m.submodules.core = core = self.core m.submodules.imem = imem = self.imem + # busy/halted signals from core + comb += self.busy_o.eq(core.busy_o) + comb += self.halted_o.eq(core.core_terminated_o) + comb += self.core_start_i.eq(core.core_start_i) + comb += self.core_bigendian_i.eq(core.bigendian_i) + # temporary hack: says "go" immediately for both address gen and ST l0 = core.l0 ldst = core.fus.fus['ldst0'] diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index 9d70e88a..804d7ba7 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -103,10 +103,10 @@ class TestRunner(FHDLTestCase): for test in self.test_data: # get core going - yield core.bigendian_i.eq(bigendian) - yield core.core_start_i.eq(1) + yield issuer.core_bigendian_i.eq(bigendian) + yield issuer.core_start_i.eq(1) yield - yield core.core_start_i.eq(0) + yield issuer.core_start_i.eq(0) yield Settle() print(test.name) @@ -154,7 +154,7 @@ class TestRunner(FHDLTestCase): yield from wait_for_busy_hi(core) yield from wait_for_busy_clear(core) - terminated = yield core.core_terminated_o + terminated = yield issuer.halted_o print ("terminated", terminated) print ("sim", code) @@ -170,7 +170,7 @@ class TestRunner(FHDLTestCase): # Memory check yield from check_sim_memory(self, l0, sim, code) - terminated = yield core.core_terminated_o + terminated = yield issuer.halted_o if terminated: break -- 2.30.2