From 4b335e68600b55ac6bc6a67e76088103c21718ba Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 3 Jun 2020 14:18:02 +0100 Subject: [PATCH] add a simple class containing all FunctionUnits --- src/soc/fu/compunits/compunits.py | 36 ++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py index 7eaecdb3..5f8ea2bd 100644 --- a/src/soc/fu/compunits/compunits.py +++ b/src/soc/fu/compunits/compunits.py @@ -42,7 +42,7 @@ see: # imports -from nmigen import Cat +from nmigen import Elaboratable, Module from nmigen.cli import rtlil from soc.experiment.compalu_multi import MultiCompUnit @@ -126,15 +126,49 @@ class ShiftRotFunctionUnit(FunctionUnitBaseSingle): # TODO: ReservationStations-based. +# simple one-only function unit class, for test purposes +class AllFunctionUnits(Elaboratable): + def __init__(self): + self.fus = {} + for (name, qty, kls) in (('alu', 1, ALUFunctionUnit), + ('cr', 1, CRFunctionUnit), + ('branch', 1, BranchFunctionUnit), + ('logical', 1, LogicalFunctionUnit), + ('shiftrot', 1, ShiftRotFunctionUnit)): + for i in range(qty): + self.fus["%s%d" % (name, i)] = kls() + + def elaborate(self, platform): + m = Module() + for (name, fu) in self.fus.items(): + setattr(m.submodules, name, fu) + return m + + def __iter__(self): + for (name, fu) in self.fus.items(): + yield from fu.ports() + + def ports(self): + return list(self) + def tst_single_fus_il(): for (name, kls) in (('alu', ALUFunctionUnit), ('cr', CRFunctionUnit), ('branch', BranchFunctionUnit), + ('logical', LogicalFunctionUnit), ('shiftrot', ShiftRotFunctionUnit)): fu = kls() vl = rtlil.convert(fu, ports=fu.ports()) with open("fu_%s.il" % name, "w") as f: f.write(vl) + +def tst_all_fus(): + dut = AllFunctionUnits() + vl = rtlil.convert(dut, ports=dut.ports()) + with open("all_fus.il", "w") as f: + f.write(vl) + if __name__ == '__main__': tst_single_fus_il() + tst_all_fus() -- 2.30.2