From 4b33c83ed2a9cdf8ad91be5f1c8f66608d8e9cf3 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 5 Sep 2021 14:11:21 +0100 Subject: [PATCH] --- openpower/sv/ldst.mdwn | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 777559924..acc973725 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -11,6 +11,31 @@ Links: * * [[simple_v_extension/specification/ld.x]] +# Rationale + +All Vector ISAs dating back fifty years have extensive and comprehensive +Load and Store operations that go far beyond the capabilities of Scalar +RISC or CISC processors, yet at their heart on an individual element +basis may be found to be no different from RISC Scalar equivalents. + +The resource savings from Vector LD/ST are significant and stem from +the fact that one single instruction can trigger a dozen (or in some +microarchitectures such as Cray or NEC SX Aurora) hundreds of element +level Memory accesses. + +Additionally, and simply: if the Arithmetic side of an ISA supports +Vector Operations, then in order to keep the ALUs 100% occupied the +Memory infrastructure (and the ISA itself) correspondingly needs Vector +Memory Operations as well. + +Vectorised Load and Store also presents an extra dimension (literslly) +which creates scenarios unique to Vector applications, that a Scalar +(and even a SIMD) ISA simply never encounters. SVP64 endeavours to +add such modes without changing the behaviour of the underlying Base +(Scalar) v3.0B operations. + +# Modes overview + Vectorisation of Load and Store requires creation, from scalar operations, a number of different modes: -- 2.30.2