From 4b443ec0a071074334b29f3a972949a889f61cd4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 22 Dec 2020 15:02:32 +0000 Subject: [PATCH] add SPBlock_512W64B8W to memory.py --- experiments12/memory.py | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/experiments12/memory.py b/experiments12/memory.py index 84fcdcf..81782dd 100644 --- a/experiments12/memory.py +++ b/experiments12/memory.py @@ -1,4 +1,4 @@ -from nmigen import * +from nmigen import Elaboratable, Cat, Module, Signal, Instance from nmigen.cli import rtlil @@ -10,13 +10,22 @@ class ADD(Elaboratable): def elaborate(self, platform): m = Module() - m.d.sync += self.f.eq(self.a + self.b) - #a = Signal(9) - #q = Signal(64) - #d = Signal(64) - #we = Signal(8) - #sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d, i_we=we) - #m.submodules += sram + result = Signal.like(self.f) + m.d.sync += result.eq(self.a + self.b) + + # 64k SRAM instance + a = Signal(9) + q = Signal(64) # output + d = Signal(64) # input + we = Signal(8) + sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d, i_we=we) + m.submodules += sram + + # connect up some arbitrary signals + m.d.comb += a.eq(Cat(self.a, self.b, self.a[0])) + m.d.comb += d.eq(result) + m.d.comb += self.f.eq(q) + return m -- 2.30.2