From 4b59d19ffdb4857e14328d8d783176b97ccde23e Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 10 May 2016 16:30:02 +0200 Subject: [PATCH] re PR target/70927 ([6 only] avx512dq instructions emitted even with -mavx512vl -mno-avx512dq) PR target/70927 * config/i386/sse.md (_andnot3), *3): For !TARGET_AVX512DQ and EVEX encoding, use vp*[dq] instead of v*p[sd] instructions and adjust mode attribute accordingly. * gcc.target/i386/avx512vl-logic-1.c: New test. * gcc.target/i386/avx512vl-logic-2.c: New test. * gcc.target/i386/avx512dq-logic-2.c: New test. From-SVN: r236083 --- gcc/ChangeLog | 8 + gcc/config/i386/sse.md | 98 +++++---- gcc/testsuite/ChangeLog | 7 + .../gcc.target/i386/avx512dq-logic-2.c | 196 ++++++++++++++++++ .../gcc.target/i386/avx512vl-logic-1.c | 132 ++++++++++++ .../gcc.target/i386/avx512vl-logic-2.c | 196 ++++++++++++++++++ 6 files changed, 598 insertions(+), 39 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx512dq-logic-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-logic-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-logic-2.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index eaa91286153..dfbb1c3e073 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2016-05-10 Jakub Jelinek + + PR target/70927 + * config/i386/sse.md (_andnot3), + *3): For !TARGET_AVX512DQ and EVEX encoding, + use vp*[dq] instead of v*p[sd] instructions and adjust mode attribute + accordingly. + 2016-05-10 Bill Schmidt PR target/70963 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e993f9cdc3a..dd1ff960f53 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -2783,54 +2783,61 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_insn "_andnot3" - [(set (match_operand:VF_128_256 0 "register_operand" "=x,v") + [(set (match_operand:VF_128_256 0 "register_operand" "=x,x,v,v") (and:VF_128_256 (not:VF_128_256 - (match_operand:VF_128_256 1 "register_operand" "0,v")) - (match_operand:VF_128_256 2 "vector_operand" "xBm,vm")))] + (match_operand:VF_128_256 1 "register_operand" "0,x,v,v")) + (match_operand:VF_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] "TARGET_SSE && " { static char buf[128]; const char *ops; const char *suffix; - switch (get_attr_mode (insn)) - { - case MODE_V8SF: - case MODE_V4SF: - suffix = "ps"; - break; - default: - suffix = ""; - } - switch (which_alternative) { case 0: ops = "andn%s\t{%%2, %%0|%%0, %%2}"; break; case 1: + case 2: + case 3: ops = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; break; default: gcc_unreachable (); } - /* There is no vandnp[sd] in avx512f. Use vpandn[qd]. */ - if ( && !TARGET_AVX512DQ) + switch (get_attr_mode (insn)) { + case MODE_V8SF: + case MODE_V4SF: + suffix = "ps"; + break; + case MODE_OI: + case MODE_TI: + /* There is no vandnp[sd] in avx512f. Use vpandn[qd]. */ suffix = GET_MODE_INNER (mode) == DFmode ? "q" : "d"; ops = "vpandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + break; + default: + suffix = ""; } snprintf (buf, sizeof (buf), ops, suffix); return buf; } - [(set_attr "isa" "noavx,avx") + [(set_attr "isa" "noavx,avx,avx512dq,avx512f") (set_attr "type" "sselog") - (set_attr "prefix" "orig,maybe_evex") + (set_attr "prefix" "orig,maybe_vex,evex,evex") (set (attr "mode") - (cond [(and (match_test " == 16") + (cond [(and (match_test "") + (and (eq_attr "alternative" "1") + (match_test "!TARGET_AVX512DQ"))) + (const_string "") + (eq_attr "alternative" "3") + (const_string "") + (and (match_test " == 16") (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")) (const_string "") (match_test "TARGET_AVX") @@ -2870,7 +2877,10 @@ } [(set_attr "type" "sselog") (set_attr "prefix" "evex") - (set_attr "mode" "")]) + (set (attr "mode") + (if_then_else (match_test "TARGET_AVX512DQ") + (const_string "") + (const_string "XI")))]) (define_expand "3" [(set (match_operand:VF_128_256 0 "register_operand") @@ -2889,10 +2899,10 @@ "ix86_fixup_binary_operands_no_copy (, mode, operands);") (define_insn "*3" - [(set (match_operand:VF_128_256 0 "register_operand" "=x,v") + [(set (match_operand:VF_128_256 0 "register_operand" "=x,x,v,v") (any_logic:VF_128_256 - (match_operand:VF_128_256 1 "vector_operand" "%0,v") - (match_operand:VF_128_256 2 "vector_operand" "xBm,vm")))] + (match_operand:VF_128_256 1 "vector_operand" "%0,x,v,v") + (match_operand:VF_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] "TARGET_SSE && && ix86_binary_operator_ok (, mode, operands)" { @@ -2900,43 +2910,50 @@ const char *ops; const char *suffix; - switch (get_attr_mode (insn)) - { - case MODE_V8SF: - case MODE_V4SF: - suffix = "ps"; - break; - default: - suffix = ""; - } - switch (which_alternative) { case 0: ops = "%s\t{%%2, %%0|%%0, %%2}"; break; case 1: + case 2: + case 3: ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; break; default: gcc_unreachable (); } - /* There is no vp[sd] in avx512f. Use vp[dq]. */ - if ( && !TARGET_AVX512DQ) + switch (get_attr_mode (insn)) { + case MODE_V8SF: + case MODE_V4SF: + suffix = "ps"; + break; + case MODE_OI: + case MODE_TI: + /* There is no vp[sd] in avx512f. Use vp[qd]. */ suffix = GET_MODE_INNER (mode) == DFmode ? "q" : "d"; ops = "vp%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + break; + default: + suffix = ""; } snprintf (buf, sizeof (buf), ops, suffix); return buf; } - [(set_attr "isa" "noavx,avx") + [(set_attr "isa" "noavx,avx,avx512dq,avx512f") (set_attr "type" "sselog") - (set_attr "prefix" "orig,maybe_evex") + (set_attr "prefix" "orig,maybe_evex,evex,evex") (set (attr "mode") - (cond [(and (match_test " == 16") + (cond [(and (match_test "") + (and (eq_attr "alternative" "1") + (match_test "!TARGET_AVX512DQ"))) + (const_string "") + (eq_attr "alternative" "3") + (const_string "") + (and (match_test " == 16") (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")) (const_string "") (match_test "TARGET_AVX") @@ -2961,7 +2978,7 @@ ops = ""; /* There is no vp[sd] in avx512f. Use vp[dq]. */ - if (( == 64 || ) && !TARGET_AVX512DQ) + if (!TARGET_AVX512DQ) { suffix = GET_MODE_INNER (mode) == DFmode ? "q" : "d"; ops = "p"; @@ -2974,7 +2991,10 @@ } [(set_attr "type" "sselog") (set_attr "prefix" "evex") - (set_attr "mode" "")]) + (set (attr "mode") + (if_then_else (match_test "TARGET_AVX512DQ") + (const_string "") + (const_string "XI")))]) (define_expand "copysign3" [(set (match_dup 4) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 58d0c8db438..deec34e8bbd 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2016-05-10 Jakub Jelinek + + PR target/70927 + * gcc.target/i386/avx512vl-logic-1.c: New test. + * gcc.target/i386/avx512vl-logic-2.c: New test. + * gcc.target/i386/avx512dq-logic-2.c: New test. + 2016-05-10 Bill Schmidt PR target/70963 diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-logic-2.c b/gcc/testsuite/gcc.target/i386/avx512dq-logic-2.c new file mode 100644 index 00000000000..e358ff56848 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512dq-logic-2.c @@ -0,0 +1,196 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512vl -mavx512dq" } */ + +#include + +__m128d +f1 (__m128d a, __m128d b) +{ + register __m128d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_and_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vandpd\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128d +f2 (__m128d a, __m128d b) +{ + register __m128d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_or_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vorpd\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128d +f3 (__m128d a, __m128d b) +{ + register __m128d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_xor_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vxorpd\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128d +f4 (__m128d a, __m128d b) +{ + register __m128d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_andnot_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vandnpd\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128 +f5 (__m128 a, __m128 b) +{ + register __m128 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_and_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vandps\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128 +f6 (__m128 a, __m128 b) +{ + register __m128 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_or_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vorps\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128 +f7 (__m128 a, __m128 b) +{ + register __m128 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_xor_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vxorps\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128 +f8 (__m128 a, __m128 b) +{ + register __m128 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_andnot_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vandnps\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m256d +f9 (__m256d a, __m256d b) +{ + register __m256d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_and_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vandpd\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256d +f10 (__m256d a, __m256d b) +{ + register __m256d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_or_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vorpd\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256d +f11 (__m256d a, __m256d b) +{ + register __m256d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_xor_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vxorpd\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256d +f12 (__m256d a, __m256d b) +{ + register __m256d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_andnot_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vandnpd\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256 +f13 (__m256 a, __m256 b) +{ + register __m256 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_and_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vandps\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256 +f14 (__m256 a, __m256 b) +{ + register __m256 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_or_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vorps\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256 +f15 (__m256 a, __m256 b) +{ + register __m256 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_xor_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vxorps\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256 +f16 (__m256 a, __m256 b) +{ + register __m256 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_andnot_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vandnps\[^\n\r\]*ymm\[0-9\]" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-logic-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-logic-1.c new file mode 100644 index 00000000000..ec5f3d980c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-logic-1.c @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512vl -mno-avx512dq" } */ + +#include + +__m128d +f1 (__m128d a, __m128d b) +{ + return _mm_and_pd (a, b); +} + +/* { dg-final { scan-assembler-times "vandpd\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128d +f2 (__m128d a, __m128d b) +{ + return _mm_or_pd (a, b); +} + +/* { dg-final { scan-assembler-times "vorpd\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128d +f3 (__m128d a, __m128d b) +{ + return _mm_xor_pd (a, b); +} + +/* { dg-final { scan-assembler-times "vxorpd\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128d +f4 (__m128d a, __m128d b) +{ + return _mm_andnot_pd (a, b); +} + +/* { dg-final { scan-assembler-times "vandnpd\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128 +f5 (__m128 a, __m128 b) +{ + return _mm_and_ps (a, b); +} + +/* { dg-final { scan-assembler-times "vandps\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128 +f6 (__m128 a, __m128 b) +{ + return _mm_or_ps (a, b); +} + +/* { dg-final { scan-assembler-times "vorps\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128 +f7 (__m128 a, __m128 b) +{ + return _mm_xor_ps (a, b); +} + +/* { dg-final { scan-assembler-times "vxorps\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128 +f8 (__m128 a, __m128 b) +{ + return _mm_andnot_ps (a, b); +} + +/* { dg-final { scan-assembler-times "vandnps\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m256d +f9 (__m256d a, __m256d b) +{ + return _mm256_and_pd (a, b); +} + +/* { dg-final { scan-assembler-times "vandpd\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256d +f10 (__m256d a, __m256d b) +{ + return _mm256_or_pd (a, b); +} + +/* { dg-final { scan-assembler-times "vorpd\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256d +f11 (__m256d a, __m256d b) +{ + return _mm256_xor_pd (a, b); +} + +/* { dg-final { scan-assembler-times "vxorpd\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256d +f12 (__m256d a, __m256d b) +{ + return _mm256_andnot_pd (a, b); +} + +/* { dg-final { scan-assembler-times "vandnpd\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256 +f13 (__m256 a, __m256 b) +{ + return _mm256_and_ps (a, b); +} + +/* { dg-final { scan-assembler-times "vandps\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256 +f14 (__m256 a, __m256 b) +{ + return _mm256_or_ps (a, b); +} + +/* { dg-final { scan-assembler-times "vorps\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256 +f15 (__m256 a, __m256 b) +{ + return _mm256_xor_ps (a, b); +} + +/* { dg-final { scan-assembler-times "vxorps\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256 +f16 (__m256 a, __m256 b) +{ + return _mm256_andnot_ps (a, b); +} + +/* { dg-final { scan-assembler-times "vandnps\[^\n\r\]*ymm\[0-9\]" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-logic-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-logic-2.c new file mode 100644 index 00000000000..7ccef279a8b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-logic-2.c @@ -0,0 +1,196 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512vl -mno-avx512dq" } */ + +#include + +__m128d +f1 (__m128d a, __m128d b) +{ + register __m128d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_and_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vpandq\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128d +f2 (__m128d a, __m128d b) +{ + register __m128d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_or_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vporq\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128d +f3 (__m128d a, __m128d b) +{ + register __m128d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_xor_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vpxorq\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128d +f4 (__m128d a, __m128d b) +{ + register __m128d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_andnot_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vpandnq\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128 +f5 (__m128 a, __m128 b) +{ + register __m128 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_and_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vpandd\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128 +f6 (__m128 a, __m128 b) +{ + register __m128 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_or_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vpord\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128 +f7 (__m128 a, __m128 b) +{ + register __m128 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_xor_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vpxord\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m128 +f8 (__m128 a, __m128 b) +{ + register __m128 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm_andnot_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vpandnd\[^\n\r\]*xmm\[0-9\]" 1 } } */ + +__m256d +f9 (__m256d a, __m256d b) +{ + register __m256d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_and_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vpandq\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256d +f10 (__m256d a, __m256d b) +{ + register __m256d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_or_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vporq\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256d +f11 (__m256d a, __m256d b) +{ + register __m256d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_xor_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vpxorq\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256d +f12 (__m256d a, __m256d b) +{ + register __m256d c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_andnot_pd (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vpandnq\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256 +f13 (__m256 a, __m256 b) +{ + register __m256 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_and_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vpandd\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256 +f14 (__m256 a, __m256 b) +{ + register __m256 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_or_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vpord\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256 +f15 (__m256 a, __m256 b) +{ + register __m256 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_xor_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vpxord\[^\n\r\]*ymm\[0-9\]" 1 } } */ + +__m256 +f16 (__m256 a, __m256 b) +{ + register __m256 c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + c = _mm256_andnot_ps (c, b); + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-times "vpandnd\[^\n\r\]*ymm\[0-9\]" 1 } } */ -- 2.30.2